Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link
25	Yuta Aiba, Yusuke Higashi, Hitomi Tanaka, Hiroki Tanaka, Fumie Kikushima, Toshio Fujisawa, Hideko Mukaida, Masayuki Miura, Tomoya Sanuki	Demonstration of Recovery Annealing on 7-Bits per Cell 3D Flash Memory at Cryogenic Operation for Bit Cost Scalability and Sustainability.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jiamin Li, Yilong Dong, Longyang Lin, Joanne Si Ying Tan, Fong Jia Yi, Jerald Yoo	Wireless Body-Area Network Transceiver ICs with Concurrent Body-Coupled Powering and Communication using Single Electrode.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Jaehan Park, Cheonhoo Jeon, Donggyu Minn, Heesung Roh, Jae-Yoon Sim	A 6.5nW, -73.5dBm Sensitivity, Cryptographic Wake-Up Receiver with a PUF-based OTP and Temperature-Insensitive Code Recovery.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Mark Daniel Alea, Ali Safa, Flavio Giacomozzi, Andrea Adami, Inci Rüya Temel, Leandro Lorenzelli, Georges G. E. Gielen	A Fingertip-Mimicking 12×16 200μm-Resolution e-skin Taxel Readout Chip with per-Taxel Spiking Readout and Embedded Receptive Field Processing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zhao Zhang 0004, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto	ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Martijn Timmermans, Marco Fattori, Pieter Harpe, Yao-Hong Liu, Eugenio Cantatore	A 3-320 fJ/conv.step Continuous Time Level Crossing ADC with Dynamic Self-Biasing Comparators Achieving 61.4 dB-SNDR.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Victor Grimblatt, Chip-Hong Chang, Ricardo Reis 0001, Anupam Chattopadhyay, Andrea Calimera (eds.)	VLSI-SoC: Technology Advancement on SoC Design - 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4-8, 2021, Revised and Extended Selected Papers	VLSI-SoC (Selected Papers)	2022	DBLP DOI BibTeX RDF
25		IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25		2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, Taiwan, April 18-21, 2022	VLSI-DAT	2022	DBLP DOI BibTeX RDF
25	Jingtong Hu	Session details: Session 4B: VLSI for Machine Learning and Artifical Intelligence 2.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
25	Jingtong Hu	Session details: Session 3B: VLSI for Machine Learning and Artifical Intelligence 1.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
25	Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni	A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H.-J. Cho, K. Rim, S. D. Kwon	Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang	A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Omid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, Drew A. Hall	Helix: An Electrochemical CMOS DNA Synthesizer.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Liang Zhao, Z. Chen, Dan Manea, S. Li, J. Li, Y. Zhu, Z. Sui, Zhichao Lu	Highly Reliable 40nm Embedded Dual-Interface-Switching RRAM Technology for Display Driver IC Applications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu	Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Dong-Jin Chang, Seung-Tak Ryu	A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yoshinori Nishi, John W. Poulton, Xi Chen 0033, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson 0002, William J. Dally, C. Thomas Gray	A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Jaeyong Jeong, Seong Kwang Kim, Jongmin Kim, Dae-Myeong Geum, Jisung Lee, Seung-Young Park, Sanghyeon Kim	3D stackable cryogenic InGaAs HEMTs for heterogeneous and monolithic 3D integrated highly scalable quantum computing systems.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka	A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim	A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos	A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Jun-Chau Chien, Zong-Jun Cheng, Shu-Yan Chuang, Hsiu-Cheng Yeh, Guan-Yu Huang, Hung-Yu Hou, Yi-Ting Chen, Wei-Yang Weng, Chi-Yang Tseng, Liang-In Lin	A Scalable Standing-Wave-Oscillator-based Imager with Near-Field-Modulated Pixels Achieving 64% Filling Factor for RF Intraoperative Imaging.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Heimanu Niebojewski, Benoit Bertrand, E. Nowak, Thomas Bedecarrats, Bruna Cardoso Paz, Lauriane Contamin, Pierre-André Mortemousque, V. Labracherie, L. Brevard, H. Sahin, Jean Charbonnier, C. Thomas, Myriam Assous, Mikaël Cassé, Matias Urdampilleta, Yann-Michel Niquet, François Perruchot, Fred Gaillard, Silvano De Franceschi, Tristan Meunier, Maud Vinet	Specificities of linear Si QD arrays integration and characterization.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Woyu Zhang, Shaocong Wang, Yi Li, Xiaoxin Xu, Danian Dong, Nanjia Jiang, Fei Wang, Zeyu Guo 0002, Renrui Fang, Chunmeng Dou, Kai Ni, Zhongrui Wang, Dashan Shang, Ming Liu 0022	Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Jeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun-Hyeok Yang, Hyun-Sik Kim	A Fully-Integrated 0.9W/mm2 79.1%-Efficiency 200MHz Multi-Phase Buck Converter with Flying-Capacitor-Based Inter-Inductor Current Balancing Technique.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu	A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Rajiv V. Joshi, John Timmerwilke, Kevin Tien, Mark Yeck, Sudipto Chakraborty	A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Gyeong-Gu Kang, Ji-Hun Lee, Se-Un Shin, Gyu-Hyeong Cho, Hyun-Sik Kim	A 5.6W-Power 96.6%-Efficiency Boost-Oriented SIDO Step-Up/Down DC-DC Converter Embedding Buck Conversion with an Energy-Balancing Capacitor.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yunhee Lee, Woonghee Lee 0005, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong	0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yuh-Jier Mii	Semiconductor Innovations, from Device to System.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Juhyuk Park, Dae-Myeong Geum, Woojin Baek, Johnson Shieh, Sanghyeon Kim	Monolithic 3D sequential integration realizing 1600-PPI red micro-LED display on Si CMOS driver IC.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Phan Dang Hung, Hongseok Shin, Yechan Park, Kim-Hoang Nguyen, Donghee Cho, Sohmyung Ha, Chul Kim, Minkyu Je	A 96.5%-Power-Efficiency Hybrid Buck-Boost Photovoltaic Energy Harvester Employing Adaptive FOCV MPPT Control for >98% MPPT Efficiency Across a 10, 000× Dynamic Range.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Rahul Gulve, Navid Sarhangnejad, Gairik Dutta, Motasem Sakr, Don Nguyen, Roberto Rangel, Wenzheng Chen, Zhengfan Xia, Mian Wei, Nikita Gusev, Esther Y. H. Lin, Xiaonong Sun, Leo Hanxu, Nikola Katic, Ameer Abdelhadi, Andreas Moshovos, Kiriakos N. Kutulakos, Roman Genov	A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Naoaki Nishimura, Atsushi Matamura, Preston Birdsong, Shaolong Liu, Abhishek Bandyopadhyay, Mariana T. Markova, Rajeev Morajkar	Common-mode Stable Multilevel Output Stage with EMI Reduction Feedback Loop for Class-D audio Amplifier.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Zijie Zheng, Chen Sun 0010, Leming Jiao, Dong Zhang, Zuopu Zhou, Xiaolin Wang, Gan Liu, Qiwen Kong, Yue Chen, Kai Ni, Xiao Gong	Boosting the Memory Window of the BEOL-Compatible MFMIS Ferroelectric/ Anti-Ferroelectric FETs by Charge Injection.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Suresh Venkatesan, James Lee, Simon Chun Kiat Goh, Brian Pile, Daniel Meerovich, Jinyu Mo, Yang Jing, Lucas Soldano, Baochang Xu, Yu Zhang, Aaron Voon-Yew Thean, Yeow Kheng Lim	A Wafer Scale Hybrid Integration Platform for Co-packaged Photonics using a CMOS based Optical InterposerTM.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto	Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Goeun Baek, Seunghun Bae, Minki Lee, Hyuncheol Park, Kangseop Lee, Jae-Yoon Sim, Moonjoo Lee, Ho-Jin Song	13-K Tnoise Cryo-CMOS Parametric Amplifier at 80 mK for Quantum Computers.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Konrad Seidel, David Lehninger, Raik Hoffmann, Tarek Ali, Maximilian Lederer, Ricardo Revello, Konstantin Mertens, Kati Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, Andreas Heinig, Thomas Kämpfe, Hannes Mähne, Kerstin Bernert, Steffen Thiem	Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yimai Peng, Gordy Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, Julien Bourgeois, David T. Blaauw, Dennis Sylvester	A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake, Takashi Watanabe, Kunihiko Araki, Naoki Nei, Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara, Hiroyuki Kawashima, Yusaku Kobayashi, Tomoyuki Hirano, Keiji Tatani	A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Seok-Hee Lee	The Rise of Memory in the Ever-Changing AI Era - From Memory to More-Than-Memory.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Youngmin Kim, Hongjong Park, Iljin Lee, Joonhoi Hur, Sangmin Yoo	High Efficiency 29-/38-GHz Hybrid Transceiver Front-Ends Utilizing Si CMOS and GaAs HEMT for 5G NR Millimeter-Wave Mobile Applications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon	A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kirby Maxey, C. H. Naylor, K. P. O'Brien, A. Penumatcha, Adedapo Oni, C. Mokhtarzadeh, C. J. Dorow, C. Rogan, B. Holybee, T. Tronic, D. Adams, N. Arefin, A. Sen Gupta, C.-C. Lin, T. Zhong, S. Lee, A. Kitamura, R. Bristol, S. B. Clendenning, U. Avci, M. Metz	300 mm MOCVD 2D CMOS Materials for More (Than) Moore Scaling.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Seki Kim, Hyongmin Lee, Yongjin Lee, Dongha Lee, Byeongbae Lee, Jahoon Jin, Susie Kim, Miri Noh, Kwonwoo Kang, Sangho Kim, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee	A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	H.-B. Jo, I.-G. Lee, J.-M. Baek, S. T. Lee, S.-M. Choi, H.-J. Kim, H.-S. Jeong, W.-S. Park, J.-H. Yoo, H.-Y. Lee, D. Y. Yun, SW. Son, D.-H. Ko, Tae-Woo Kim, H.-M. Kwon, S.-K. Kim, Jun-Gyu Kim, J. Yun, T. Kim, J. H. Lee, J.-H. Lee, C.-S. Shin, K.-S. Seo, Dae-Hyun Kim	Lg = 130 nm GAA MBCFETs with three-level stacked In0.53Ga0.47As nanosheets.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Miguel Urteaga, Zach Griffith, A. Arias-Purdue, A. Carter, Petra Rowell, J. Hacker, B. Brar	InP HBT Technologies for sub-THz Communications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong	A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Byeongwoo Koo, Sunghan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho, Michael Choi, Jongshin Shin	A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi	High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, N. Pinho, Tomas Webers, Dimitrios Velenis, A. Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke	(Why do we need) Wireless Heterogeneous Integration (anyway?).	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kyosuke Kobinata, Tatsuya Funaki, Yoshiaki Satake, Hitoshi Matsuno, Seiji Hidaka, Shunsuke Abe, Hiroyuki Ito, Chih-Cheng Hsiao, Sheng Yi Li, Young-Suk Kim, Takayuki Ohba	Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D Functional Interposer for Power Delivery Network.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kunihiro Hatakeyama, Yu Okubo, Tomohiro Nakagome, Masahiro Makino, Hiroshi Takashima, Takahiro Akutsu, Takehide Sawamoto, Masanori Nagase, Tatsuo Noguchi, Shoji Kawahito	A Hybrid Indirect ToF Image Sensor for Long-Range 3D Depth Measurement under High Ambient Light Conditions.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hiroshi Fuketa, Ippei Akita, Tomohiro Ishikawa, Hanpei Koike, Takahiro Mori	A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kyoung-Jun Moon, Dong-Ryeol Oh, Young-Hyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyo-Chul Shin, Young-Jae Cho, Michael Choi, Jongshin Shin	A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	M. Y. Song, C. M. Lee, S. Y. Yang, G. L. Chen, K. M. Chen, I J. Wang, Y. C. Hsin, K. T. Chang, C. F. Hsu, S. H. Li, J. H. Wei, T. Y. Lee, M. F. Chang, X. Y. Bao, C. H. Diaz, S. J. Lin	High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Nail Etkin Can Akkaya, Gary Chan, Hung-Jen Liao, Yih Wang, Jonathan Chang	A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Zih-Sing Fu, Yu-Chi Lee, Alex Park 0002, Chia-Hsiang Yang	A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Xiaohui Lin 0012, Mohamed Megahed, Tejasvi Anand	A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono	A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Taras Ravsher, Daniele Garbin, Andrea Fantini, Robin Degraeve, Sergiu Clima, Gabriele Luca Donadio, Shreya Kundu, Hubert Hody, Wouter Devulder, Jan Van Houdt, Valeri Afanas'ev, Romain Delhougne, Gouri Sankar Kar	Enhanced performance and low-power capability of SiGeAsSe-GeSbTe 1S1R phase-change memory operated in bipolar mode.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Qirui Zhang 0001, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester	A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu	A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Can Livanelioglu, Woojun Choi, Donghwan Kim, Jiawei Liao, Rosario M. Incandela, Giorgio Cristiano, Taekwang Jang	A 0.0014 mm2, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, J. De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi	Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Luc Enthoven, Job van Staveren, Jiang Gong, Masoud Babaie, Fabio Sebastiano	A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hyunjin Shin, Sangkyung Won, Dohui Kim, Byunghun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi 0001, Jongwook Kye	A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Chia-Chi Kuo, Rihito Kuroda	A 4-Tap CMOS Time-of-Flight Image Sensor with In-pixel Analog Memory Array Achieving 10Kfps High-Speed Range Imaging and Depth Precision Enhancement.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Shota Kitamura, Naohiko Kimizuka, Akiko Honjo, Koichi Baba, Toshihiro Kurobe, Hideomi Kumano, Takuya Toyofuku, Kouhei Takeuchi, Shota Nishimura, Akihiko Kato, Tomoyuki Hirano, Yusuke Oike	Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae	A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yuanqing Huang, Yogesh Ramadass, Dongsheng Brian Ma	A 90.7% 4-W 3P4S Hybrid Switching Converter Using Adaptive VCF Rebalancing Technique and Switching Node Dual-Edge tdead Modulation for Extreme 48V/1V Direct DC-DC Conversion.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	C. Safranski, Guohan Hu, J. Z. Sun, P. Hashemi, S. L. Brown, L. Buzi, C. P. D'Emic, E. R. J. Edwards, Eileen A. Galligan, M. G. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, Kenneth F. Latzko, Philip Louis Trouilloud, S. Zare, Daniel Christopher Worledge	Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Pai-Ying Liao, Sami Alajlouni, Mengwei Si, Zhuocheng Zhang, Zehao Lin, Jinhyun Noh, Calista Wilk, Ali Shakouri, Peide D. Ye	Thermal Studies of BEOL-compatible Top-Gated Atomically Thin ALD In2O3 FETs.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst	TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Yimai Peng, Seokhyeon Jeong, Kyojin Choo, Yejoong Kim, Li-Yu Chen, Rohit Rothe, Li Xu 0006, Ilya Gurin, Omid Oliaei, Vadim Tsinker, Stephen Bart, Peter Hartwell, David T. Blaauw, Dennis Sylvester	A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS Biasing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung	A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang	A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kazunori Hasebe, Shinichirou Etou, Daisuke Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe, Tomohiro Matsumoto, Yasushi Katayama	A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Wei Zhu 0017, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kai Wang, Yan Wang 0023	A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Wenxuan Sun, Woyu Zhang, Jie Yu 0027, Yi Li, Zeyu Guo 0002, Jinru Lai, Danian Dong, Xu Zheng, Fei Wang, Shaoyang Fan, Xiaoxin Xu, Dashan Shang, Ming Liu	3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm2) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Subhajit Ray, Peter R. Kinget	A 31-Feature, 80nW, 0.53mm2 Audio Analog Feature Extractor based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders 0001, Steven Hsu, Amit Agarwal 0001, Vivek De, Sanu Mathew	A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie	A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas 0003, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina	Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang	A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Z. Wei, W. Kim, Z. Wang, L. Hu, D. Jung, J. Zhang, Y. Huai	Accurate and Fast STT-MRAM Endurance Evaluation Using a Novel Metric for Asymmetric Bipolar Stress and Deep Learning.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Dae-Myeong Geum, Jinha Lim, Junho Jang, Seungyeop Ahn, SeongKwang Kim, Joonsup Shim, Bong Ho Kim, Juhyuk Park, Woo Jin Baek, Jaeyong Jeong, Sanghyeon Kim	A sub-micron-thick InGaAs broadband (400-1700 nm) photodetectors with a high external quantum efficiency (>70%).	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Zehao Lin, Mengwei Si, Peide D. Ye	Ultra-Fast Operation of BEOL-Compatible Atomic-Layer-Deposited In2O3 Fe-FETs: Achieving Memory Performance Enhancement with Memory Window of 2.5 V and High Endurance > 109 Cycles without VT Drift Penalty.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Martin van den Brink, Anthony Yen, Paul van Wijnen, Michael Lercel, Boudewijn Sluijk	Holistic Patterning to Advance Semiconductor Manufacturing in the 2020s and Beyond.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw	A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni	Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Teruki Someya, Vincent Van Hoek, Jan A. Angevare, Sining Pan, Kofi A. A. Makinwa	A 210nW BJT-based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -15°C to 85°C.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Xiao Lyu, Pragya R. Shrestha, Mengwei Si, Panni Wang, Junkang Li, Kin P. Cheung, Shimeng Yu, Peide D. Ye	Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto	On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné	Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
25	Wei Zhu 0017, Ruitao Wang, Jian Zhang, Jiawen Wang, Chenguang Li, Yan Wang 0023	An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF