Search results for "NMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng	Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits.	ISQED	2003	DBLP DOI BibTeX RDF
67	Susanta Sengupta	An input-free NMOS VT extractor circuit in presence of body effects.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
58	Scott Miller, Mihai Sima, Michael McGuire	Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays.	DSD	2007	DBLP DOI BibTeX RDF
58	Hsin-Chyh Hsu, Ming-Dou Ker	Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask.	ISQED	2006	DBLP DOI BibTeX RDF
55	Soman Purushothaman	A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD.	EIT	2008	DBLP DOI BibTeX RDF
47	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
47	Chris Hyung-Il Kim, Hendrawan Soeleman, Kaushik Roy 0001	Ultra-low-power DLMS adaptive filter for hearing aid applications.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
47	Ming-Dou Ker, Che-Hao Chuang	ESD protection circuits with novel MOS-bounded diode structures.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
47	Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo	ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process.	ISQED	2002	DBLP DOI BibTeX RDF	ESD, ESD protection circuit, substrate-triggered technique
47	Dingming Xie, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
43	Gerhard Nebel, Thomas Baglin, Iker San Sebastian, Holger Sedlak, Uwe Weder	A very low drop voltage regulator using an NMOS output transistor.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
43	Boonchai Boonchu, Wanlop Surakampontorn	A new NMOS four-quadrant analog multiplier.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
43	Walid Elgharbawy, Magdy A. Bayoumi	New Bulk Dynamic Threshold NMOS Schemes for Low-Energy Subthreshold Domino-Like Circui.	ISVLSI	2004	DBLP DOI BibTeX RDF
43	Yusuf Leblebici, Sung-Mo Kang	Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
37	Seokkee Kim, Soo-Ik Chae	Implementation of a simple 8-bit microprocessor with reversible energy recovery logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor
37	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
35	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Stress aware layout optimization.	ISPD	2008	DBLP DOI BibTeX RDF
35	S. Vatti, Christos Papavassiliou	New LC oscillator topology in CMOS 0.18µm technology.	ISCAS	2006	DBLP DOI BibTeX RDF
35	H. C. Srinivasaiah, Navakanta Bhat	Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment.	VLSI Design	2004	DBLP DOI BibTeX RDF	Disposable spacer, Transmission of moments technique, Plackett-Burman design, Sensitivity analysis, Statistical modeling, CMOS technology, Response surface methodology, Monte carlo analysis
35	Mineo Kaneko	Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
32	Ahmad Sabirin Zoolfakar, Hashimah Hashim	Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	ion implantation, depletion, Enhancement, transistor
32	Elias Kougianos, Saraju P. Mohanty	Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective.	VLSI Design	2007	DBLP DOI BibTeX RDF
32	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Low-power domino circuits using NMOS pull-up on off-critical paths.	ASP-DAC	2005	DBLP DOI BibTeX RDF
32	Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai	Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
32	Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang	NMOS Energy Recovery Logic.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
32	Y. G. Chen, James B. Kuo	A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
32	Andrzej Krasniewski, Alexander Albicki	Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications.	DAC	1985	DBLP DOI BibTeX RDF
25	Fatemeh Eslami, Mihai Sima	Capacitive Boosting for FPGA Interconnection Networks.	FPL	2011	DBLP DOI BibTeX RDF	capacitive boosting, nMOS pass transistor multiplexers, FPGA interconnection network
25	Seokkee Kim, Soo-Ik Chae	Complexity reduction in an nRERL microprocessor.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer skipping, clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), reversibility breaking, microprocessor, complexity reduction
25	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
25	Chris Hyung-Il Kim, Kaushik Roy 0001	Ultra-low power DLMS adaptive filter for hearing aid applications.	ISLPED	2001	DBLP DOI BibTeX RDF	DLMS adaptive filter, sub-CMOS, sub-pseudo NMOS, sub-threshold operation, parallel architecture
25	Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama	Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.	ISMVL	1995	DBLP DOI BibTeX RDF	quantum interference devices, MOS logic circuits, quantum device model, super pass gate, multiple-valued digital systems, VLSI devices, super pass transistor, multiple-valued VLSI systems, multiple-signal-level detection, multiple-valued universal logic module, multiple-valued image processing system, NMOS circuit, VLSI, multivalued logic circuits, semiconductor device models
25	Jien-Chung Lo, Suchai Thanawastien	On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	combinational totally self-checking 1-out-of-3 code checkers, NMOS, TSC goal, fault sequences, minimum fault sequences, MOS integrated circuits, logic testing, logic design, automatic testing, integrated logic circuits
25	In-Shek Hsu, Trieu-Kien Truong, Leslie J. Deutsch, Irving S. Reed	A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	dual-basis multiplier, Massey-Omura normal basis multiplier, Scott-Tavares-Peppard standard basis multiplier, NMOS technology, VLSI, VLSI architecture, multiplying circuits, finite field multipliers, field effect integrated circuits
25	James W. Watterson, Jill J. Hallenbeck	Modulo 3 Residue Checker: New Results on Performance and Cost.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage
23	Maziyar Khorasani, Leendert van den Berg, Philip A. Marshall, Meysam Zargham, Vincent C. Gaudet, Duncan G. Elliott, Stephane Martel	Low-power static and dynamic high-voltage CMOS level-shifter circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Edward K. F. Lee, Anthony Lam, Taihu Li	A 0.65V rail-to-rail constant gm opamp for biomedical applications.	ISCAS	2008	DBLP DOI BibTeX RDF
23	Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee	Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.	VLSI Design	2008	DBLP DOI BibTeX RDF
23	Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha	Vt balancing and device sizing towards high yield of sub-threshold static logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	variability, sub-threshold
23	Chun-Chen Yeh, Eugenio Culurciello	Nonvolatile Flash Memories in Silicon-on-sapphire CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Minsik Ahn, Chang-Ho Lee, Joy Laskar	CMOS High Power SPDT Switch using Multigate Structure.	ISCAS	2007	DBLP DOI BibTeX RDF
23	Rajani Kuchipudi, Hamid Mahmoodi	Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.	ISQED	2007	DBLP DOI BibTeX RDF
23	Edward K. Lee 0002, Eusebiu Matei, Ravi S. Ananth	A 0.9 V rail-to-rail constant gm amplifier for implantable biomedical applications.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Bahman Kheradmand Boroujeni, Fatemeh Aezinia, Ali Afzali-Kusha	High performance circuit techniques for dynamic OR gates.	ISCAS	2006	DBLP DOI BibTeX RDF
23	Rabiul Islam, Adam Brand, Dave Lippincott	Low power SRAM techniques for handheld products.	ISLPED	2005	DBLP DOI BibTeX RDF	back-bias, bitcell, memory, leakage
23	Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt	On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST).	IOLTS	2005	DBLP DOI BibTeX RDF
23	Cassondra Neau, Kaushik Roy 0001	Optimal body bias selection for leakage improvement and process compensation over different technology generations.	ISLPED	2003	DBLP DOI BibTeX RDF	band-to-band tunneling, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling, body bias
23	Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu	Low-power and low-voltage fully parallel content-addressable memory.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
23	J. Bhattacharjee, D. Mukherjee, Joy Laskar	A monolithic CMOS VCO for wireless LAN applications.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
23	H. C. Srinivasaiah, Navakanta Bhat	Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
23	Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae	An 8-b nRERL microprocessor for ultra-low-energy applications.	ASP-DAC	2001	DBLP DOI BibTeX RDF
23	Rong Lin, Kevin E. Kerr, André S. Botha	A Novel Approach for CMOS Parallel Counter Design.	EUROMICRO	1999	DBLP DOI BibTeX RDF	parallel counter and compressor, low power high speed CMOS circuit design, VLSI design, Arithmetic circuit, partial product reduction
23	Dinesh Somasekhar, Kaushik Roy 0001	LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
23	Tamara I. Ahrens, Thomas H. Lee	A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances.	ISLPED	1998	DBLP DOI BibTeX RDF
23	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
23	Kanji Hirabayashi	Self-checking CMOS circuits using pass-transistor logic.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF
23	Hans-Joachim Wunderlich, Wolfgang Rosenstiel	On fault modeling for dynamic MOS circuits.	DAC	1986	DBLP DOI BibTeX RDF	dynamic MOS, fault modeling, random testing, test pattern generation
20	Xin Ming, Jian-Jun Kuang, Xin-Ce Gong, Jie Zhang 0068, Zhuo Wang 0007, Bo Zhang 0027	An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
20	Minkyung Kim 0014, Hyeongseok Seo, Songhyeon Kim, Jung-Hoon Chun, Seong-Jin Kim, Jaehyuk Choi 0001	6.11 A 320x240 CMOS LiDAR Sensor with 6-Transistor nMOS-Only SPAD Analog Front-End and Area-Efficient Priority Histogram Memory.	ISSCC	2024	DBLP DOI BibTeX RDF
20	Hyunjun Park, Woojoong Jung, Minsu Kim, Hyung-Min Lee	A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis Inverse Biasing.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
20	Tiedong Cheng, Ziyu Xiao, Jianping Guo, Lijun Xu	A low power high area-efficiency NMOS LDO with fast adaptive bias.	Integr.	2023	DBLP DOI BibTeX RDF
20	Jaejin Kim, Gunmo Koo, Seongmin Lee 0010, Jae Hoon Shim, Kunhee Cho	An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
20	Jinseok Park, Seungchan Lee, Songcheol Hong	A 24-40 GHz Differential SPDT Switch With an NMOS and PMOS Alternating Structure and Leakage-Canceling Capacitors.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Yian Luo, Junhang Zhang, Jiacheng Hao, Xiaojin Zhao	A 2.5 pJ/bit PVT-Tolerant True Random Number Generator Based on Native-NMOS-Regulated Ring Oscillator.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Xiaguang Li, Keping Wang, Yixin Zhou, Yanjie Pan, Fanyi Meng, Kaixue Ma	A Wide Input Range All-NMOS Rectifier With Gate Voltage Boosting Technique for Wireless Power Transfer.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
20	Bhawna Rawat, Poornima Mittal	A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
20	PuYang Zheng, Xiao Sha, Dyumaan Arvind, Yang Xie, Milutin Stanacevic	Ultra-low $I_{Q}$ Fully Integrated NMOS LDO with Enhanced Load Regulation and Startup for RF Energy Harvesting Sensors.	MWSCAS	2023	DBLP DOI BibTeX RDF
20	Carlos Alfredo Pelcastre Ortega, Mónico Linares Aranda	Hourglass and Semi-Hourglass layout techniques to improve radiation hardening of NMOS devices.	CCE	2023	DBLP DOI BibTeX RDF
20	Engin Çagdas, Hüseyin Aniktar, M. Emin Tunbak, Volkan Fenercioglu, S. Ebru Arikan, A. Ulvi Caliskan	Modeling and Validation of an Isolated NMOS Transistor in a 0.25 μm SiGe-C BiCMOS Process.	ICECS	2023	DBLP DOI BibTeX RDF
20	Tong Wu, Lei Zhu, Yifa Wang, Jianping Guo, Dihu Chen	A Fully Integrated High-Efficiency All-NMOS Charge Pump for Wide Input Range Ultra-Low Dropout Regulator.	ICTA	2023	DBLP DOI BibTeX RDF
20	Wen-Yang Hsu, Joan Aymerich, Xiaolin Yang, Chutham Sawigun, Philippe Coppejans, Carolina Mora Lopez	A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range.	ESSCIRC	2023	DBLP DOI BibTeX RDF
20	Zhe Liu 0038, Chirn Chye Boon, Yangtao Dong, Kaituo Yang	A 2.4dB NF +4.1dBm IIP3 Differential Dual-Feedforward-Based Noise-Cancelling LNTA With Complementary NMOS and PMOS Configuration.	ESSCIRC	2023	DBLP DOI BibTeX RDF
20	Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi	SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation.	ICICDT	2023	DBLP DOI BibTeX RDF
20	Abhinav Saxena, Anurag Yadav, Subodh Wairya	Design Analysis of an Energy-Efficient Low-Power Dynamic Comparator Using NMOS Based Preamplifier.	ICCCNT	2023	DBLP DOI BibTeX RDF
20	Nachiket V. Desai, Han Wui Then, Jingshu Yu, Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De	A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
20	Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx	Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
20	Kai Yu 0008, Yangrun Zhou, Sizhen Li, Mo Huang	A 23-pW NMOS-Only Voltage Reference With Optimum Body Selection for Process Compensation.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
20	Dharmaray Nedalgi, Saroja V. Siddamal	Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
20	Honglin Xu, Hao Zhang, Junjie Wu	A 28V NMOS power switch and bootstrap driver with integrated PA gate driver.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
20	Yu Zhang, Xiao Zhao, Yongqing Wang, Liyuan Dong	A fully integrated overshoot-reduction low-dropout regulator based on hybrid NMOS/PMOS power transistors technique for SoC applications.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
20	Luchang He, Xi Li 0012, Siqiu Xu, Guochang Pan, Chenchen Xie, Houpeng Chen, Zhitang Song	A Fast-Transient-Response NMOS LDO with Wide Load-Capacitance Range for Cross-Point Memory.	Sensors	2022	DBLP DOI BibTeX RDF
20	Boqi Song, Changchun Chai, Fuxing Li, Chanrong Jiang, Yintang Yang	Two novel PSRR enhancement techniques for voltage reference of depletion NMOS.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
20	Yifa Wang, Tong Wu, Jianping Guo	A Charge Pump Based 1.5A NMOS LDO with 1.0~6.5V Input Range and 110mV Dropout Voltage.	ICTA	2022	DBLP DOI BibTeX RDF
20	Bumkil Lee, Dongsheng Brian Ma	A 20 MHz On-Chip All-NMOS 3-Level DC-DC Converter With Interception Coupling Dead-Time Control and 3-Switch Bootstrap Gate Driver.	IEEE Trans. Ind. Electron.	2021	DBLP DOI BibTeX RDF
20	Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui	The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates.	IEEE Access	2021	DBLP DOI BibTeX RDF
20	Shashank Tiwari, Jayanta Mukherjee 0002	An Inductorless Wideband Gm-Boosted Balun LNA With nMOS-pMOS Configuration and Capacitively Coupled Loads for Sub-GHz IoT Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
20	Haixiao Cao, Xu Yang, Wuhua Li, Yong Ding 0003, Wanyuan Qu	An Impedance Adapting Compensation Scheme for High Current NMOS LDO Design.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
20	Michele Caselli, Chris van Liempd, Andrea Boni, Stefano Stanzione	A low-power native NMOS-based bandgap reference operating from -55°C to 125°C with Li-Ion battery compatibility.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
20	Carlos H. S. Coelho, João Antonio Martino, Marcello Bellodi, Eddy Simoen, Anabela Veloso, Paula Ghedini Der Agopian	Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
20	Michelly de Souza, Sylvain Barraud, Mikaël Cassé, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello	Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors.	ESSDERC	2021	DBLP DOI BibTeX RDF
20	Sameer H. Jain, Dimitri Lederer, Arvind Kumar, Sudesh Saroop, Chris Prindle, P. Srinivasan 0002, Wen Liu, Ravi Achanta, Erdem Kaltalioglu, Stephen Moss, Greg Freeman, Paul Colestock	Novel mmWave NMOS Device for High Pout mmWave Power Amplifiers in 45RFSOI.	ESSDERC	2021	DBLP DOI BibTeX RDF
20	Yasuyuki Morishita, Satoshi Maeda	Characterization of NMOS-based ESD Protection for Wide-range Pulse Immunity.	IRPS	2021	DBLP DOI BibTeX RDF
20	Sagar Premnath Karalkar, Vishal Ganesan, Milova Paul, Kyong Jin Hwang, Robert Gauthier 0002	Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp.	IRPS	2021	DBLP DOI BibTeX RDF
20	Mengjie Song, Chenchang Zhan, Lidan Wang, Litao Wu, Bangdong Sun	A 127 nA Quiescent Current Capacitorless NMOS LDO with Fast-Transient Response.	ICTA	2021	DBLP DOI BibTeX RDF
20	Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx	A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS.	ESSCIRC	2021	DBLP DOI BibTeX RDF
20	Sorapong Wachirarattanapornkul	Uniformly Distributed RC Filters Based-on NMOS Transistor-Only.	IECC	2021	DBLP DOI BibTeX RDF
20	Nachiket V. Desai, Harish K. Krishnamurthy, William J. Lambert, Jingshu Yu, Han Wui Then, Nicolas Butzen, Sheldon Weng, Christopher Schaef, N. Nidhi, Marko Radosavljevic, Johann Rode, Justin Sandford, Kaladhar Radhakrishnan, Krishnan Ravichandran, Bernhard Sell, James W. Tschanz, Vivek De	A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
20	PuYang Zheng, Xiao Sha, Milutin Stanacevic	Analysis of the Sub-µA Fully Integrated NMOS LDO for Backscattering System.	SoCC	2021	DBLP DOI BibTeX RDF
20	Hiroshi Iwai	NMOS LSI Development from 1970's to the beginning of 1980's.	ASICON	2021	DBLP DOI BibTeX RDF
20	Fan Chen, Dapeng Liu, Long Chen, Shuai Tao, Jun You, Zebin Kong	The Relationship between Packaging Structures, Chip Area and Thermal Resistance of NMOS Semiconductor in Transient Dual Interface Method.	EITCE	2021	DBLP DOI BibTeX RDF