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Publication years (Num. hits)
1988-1991 (24) 1992 (25) 1993 (28) 1994 (30) 1995 (50) 1996 (57) 1997 (50) 1998 (46) 1999 (57) 2000 (54) 2001 (64) 2002 (51) 2003 (77) 2004 (81) 2005 (83) 2006 (74) 2007 (54) 2008 (45) 2009 (26) 2010 (22) 2011-2012 (21) 2013 (15) 2014-2015 (17) 2016-2018 (19) 2019-2021 (17) 2022-2024 (6)
Publication types (Num. hits)
article(253) book(2) incollection(1) inproceedings(821) phdthesis(16)
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Found 1093 publication records. Showing 1093 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
86Marc Tremblay, Bill Joy 0001, Ken Shin A three dimensional register file for superscalar processors. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
78Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye A technique to determine power-efficient, high-performance superscalar processors. Search on Bibsonomy HICSS (1) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
76Enric Tejedor, Rosa M. Badia COMP Superscalar: Bringing GRID Superscalar and GCM Together. Search on Bibsonomy CCGRID The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Grid Component Model, Grid-unaware applications, concurrency exploitation, performance optimization, Component-based software engineering
72Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe Load Balancing in Superscalar Architectures. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
63Josep Lluís Larriba-Pey, Daniel Jiménez-González, Juan J. Navarro An Analysis of Superscalar Sorting Algorithms on an R8000 Processor. Search on Bibsonomy SCCC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF superscalar sorting algorithms, R8000 processor, in-memory sorting algorithms, Quick sort, Heap sort, Multiway merge, parallel algorithms, locality, superscalar architectures, Radix sort, Bucket sort
63Larry Carter, Jeanne Ferrante, Susan Flynn Hummel Hierarchical tiling for improved superscalar performance. Search on Bibsonomy IPPS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage
59Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. Search on Bibsonomy Theory Comput. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
59Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero A cost effective architecture for vectorizable numerical and multimedia applications. Search on Bibsonomy SPAA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
59Vimal K. Reddy, Eric Rotenberg Coverage of a microarchitecture-level fault check regimen in a superscalar processor. Search on Bibsonomy DSN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
59Rosa M. Badia, Jesús Labarta, Raül Sirvent, Josep M. Pérez, José M. Cela, Rogeli Grima Programming Grid Applications with GRID Superscalar. Search on Bibsonomy J. Grid Comput. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Grid programming models, Grid middleware
59André Seznec, Eric Toullec, Olivier Rochecouste Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. Search on Bibsonomy MICRO The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
57Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede Superscalar Coprocessor for High-Speed Curve-Based Cryptography. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor
57Graham P. Jones, Nigel P. Topham A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. Search on Bibsonomy MICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Access Decoupling, Superscalar, out of order execution, latency hiding
57Avi Mendelson, Neeraj Suri Designing High-Performance & Reliable Superscalar Architectures: The out of Order Reliable Superscalar (O3RS) Approach. Search on Bibsonomy DSN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Transient Errors/Recovery, Pipelines, Superscalar architectures
55Bo Kågström Management of Deep Memory Hierarchies - Recursive Blocked Algorithms and Hybrid Data Structures for Dense Matrix Computations. Search on Bibsonomy PARA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF automatic variable blocking, hybrid data structures, superscalar kernels, SMP parallelization, library software, ESSL, RECSY, periodic systems, factorizations, recursion, superscalar, LAPACK, level 3 BLAS, dense linear algebra, GEMM-based, SLICOT, matrix equations
55Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung Register renaming for x86 superscalar design. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
55Roger Collins, Gordon B. Steven Instruction Scheduling for a Superscalar Architecture. Search on Bibsonomy EUROMICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
55Steven Wallace, Nirav Dagli, Nader Bagherzadeh Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF centralized instruction window, four instructions per cycle, compact layout, full-custom design, computer architecture, microprocessor chips, superscalar architecture, superscalar microprocessor, out-of-order issue, 100 MHz
51Rafael R. dos Santos, Philippe Olivier Alexandre Navaux Analysing a Multistreamed Superscalar Speculative Fetch Mechanism. Search on Bibsonomy Euro-Par The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
51Anthony C. J. Fox, Neal A. Harman Algebraic Models of Superscalar Microprocessor Implementations: A Case Study. Search on Bibsonomy Prospects for Hardware Foundations The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
51Soohong P. Kim, Raymond Hoare, Henry G. Dietz VLIW Across Multiple Superscalar Processors on a Single Chip. Search on Bibsonomy IEEE PACT The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
49Krishna M. Kavi, Roberto Giorgi, Joseph Arul Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF superscalar, Thread Level Parallelism, Multithreaded architectures, decoupled architectures, dataflow architectures
48Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001 A mechanistic performance model for superscalar out-of-order processors. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
48Patrick Ndai, Swarup Bhunia, Amit Agarwal 0001, Kaushik Roy 0001 Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors
48Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning. Search on Bibsonomy DSN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF overclocking, Reliability, Fault-Tolerant Computing, Dynamic, Superscalar processor
48Dmitry V. Ponomarev, Gurhan Kucuk, Kanad Ghose Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF energy-efficient datapath, Superscalar processor, power reduction, dynamic instruction scheduling
48Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose Power efficient comparators for long arguments in superscalar processors. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low-power comparators, superscalar datapath
48Kanad Ghose Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session). Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF instruction dispatching, instruction issue, window buffer, superscalar processor, power minimization
48Chris Stolte, Robert P. Bosch Jr., Pat Hanrahan, Mendel Rosenblum Visualizing Application Behavior on Superscalar Processors. Search on Bibsonomy INFOVIS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Computer systems visualization, superscalar processors, visualization systems
48Bernard Goossens, Duc Thang Vu Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors
46W. Lynn Gallagher, Chuan-lin Wu Evaluation of a memory hierarchy for the MTS multithreaded processor. Search on Bibsonomy ICPADS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
42Yinong Zhang, George B. Adams III Performance Modeling and Code Partitioning for the DS Architecture. Search on Bibsonomy ISCA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
42Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya Performance Comparison of ILP Machines with Cycle Time Evaluation. Search on Bibsonomy ISCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
42Kiyeon Lee, Shayne Evans, Sangyeun Cho Accurately approximating superscalar processor performance from traces. Search on Bibsonomy ISPASS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
42Tarek M. Taha, D. Scott Wills An Instruction Throughput Model of Superscalar Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Modeling techniques, Pipeline processors, Modeling of computer architecture
42Mojtaba Shakeri, Abolfazl Toroghi Haghighat, Mohammad K. Akbari Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors. Search on Bibsonomy ITNG The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
42Josep M. Pérez, Rosa M. Badia, Jesús Labarta Including SMP in Grids as Execution Platform and Other Extensions in GRID Superscalar. Search on Bibsonomy e-Science The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
42Emil Talpes, Diana Marculescu Execution cache-based microarchitecture for power-efficient superscalar processors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Vasilis Dialinos, Rosa M. Badia, Raül Sirvent, Josep M. Pérez, Jesús Labarta Implementing phylogenetic inference with GRID superscalar. Search on Bibsonomy CCGRID The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. Search on Bibsonomy MICRO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Tejas Karkhanis, James E. Smith 0001 A First-Order Superscalar Processor Model. Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Jessica H. Tseng, Krste Asanovic Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. Search on Bibsonomy ISCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
42Tony Werner, Venkatesh Akella An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. Search on Bibsonomy ASYNC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
42Victor V. Zyuban, Peter M. Kogge Optimization of high-performance superscalar architectures for energy efficiency. Search on Bibsonomy ISLPED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
42Simonjit Dutta, Manoj Franklin Control Flow Prediction Schemes for Wide-Issue Superscalar Processors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP)
42Esther Stümpel, Michael Thies, Uwe Kastens VLIW Compilation Techniques for Superscalar Architectures. Search on Bibsonomy CC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
42Andreas Unger, Eberhard Zehendner Tuning the GNU Instruction Scheduler to Superscalar Microprocessors. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
42Manu Gulati, Nader Bagherzadeh Performance Study of a Multithreaded Superscalar Microprocessor. Search on Bibsonomy HPCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multithreading, instruction-level parallelism, Superscalars, out-of-order execution
42Hong Chich Chou, Chung-Ping Chung An Optimal Instruction Scheduler for Superscalar Processor. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
42Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv VLIW Compilation Techniques in a Superscalar Environment. Search on Bibsonomy PLDI The full citation details ... 1994 DBLP  DOI  BibTeX  RDF profiling directed feedback, compiler optimizations, software pipelining, VLIW, superscalars, global scheduling, IBM RS/6000
42Michael D. Smith 0001, Mark Horowitz, Monica S. Lam Efficient Superscalar Performance Through Boosting. Search on Bibsonomy ASPLOS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
40Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras Low power microarchitecture with instruction reuse. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
40Jessica H. Tseng, Krste Asanovic A Speculative Control Scheme for an Energy-Efficient Banked Register Fil. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF speculative control, Low-power, superscalar, register file, simultaneous multithreading
40William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang Tolerating data access latency with register preloading. Search on Bibsonomy ICS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF VLIW/superscalar processor, load latency, register preload, register file, data dependence analysis
40Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras Interval-based models for run-time DVFS orchestration in superscalar processors. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling
40Rosa M. Badia, D. Du, Eduardo Huedo, Antonis C. Kokossis, Ignacio Martín Llorente, Rubén S. Montero, Marc de Palol, Raül Sirvent, Constantino Vázquez Integration of GRID Superscalar and GridWay Metascheduler with the DRMAA OGF Standard. Search on Bibsonomy Euro-Par The full citation details ... 2008 DBLP  DOI  BibTeX  RDF DRMAA, GRID superscalar, GridWay Metascheduler, Grid Computing
40William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame Modeling Assembly Instruction Timing in Superscalar Architectures. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF assembly-level analysis, performance estimation, superscalar architectures
40Jorge E. Carrillo, Paul Chow The effect of reconfigurable units in superscalar processors. Search on Bibsonomy FPGA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF OneChip, superscalar processors, reconfigurable processors
40Pierre Michaud, André Seznec, Stéphan Jourdan Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. Search on Bibsonomy IEEE PACT The full citation details ... 1999 DBLP  DOI  BibTeX  RDF instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
40Santiago Rodríguez de la Fuente, M. Isabel García Clemente, Rafael Méndez Cavanillas Teaching computer architecture with a new superscalar processor emulator. Search on Bibsonomy ITiCSE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF education, pipeline, emulation, cache memory, superscalar
40Srivatsan Srinivasan, Lizy Kurian John On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF hardware resource allocation, superscalar processor, pseudorandom sequences, reorder buffer
40Steven Wallace, Nader Bagherzadeh Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
40Frank P. Burns, Albert Koelmans, Alexandre Yakovlev Analysing Superscalar Processor Architectures with Coloured Petri Nets. Search on Bibsonomy Int. J. Softw. Tools Technol. Transf. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Asynchronous processors, Modelling, Real-time systems, Worst case execution time, Coloured Petri nets, Superscalar processors
40James O. Bondi, Ashwini K. Nanda, Simonjit Dutta Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. Search on Bibsonomy MICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
40Shlomit S. Pinter, Adi Yoaz Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors. Search on Bibsonomy MICRO The full citation details ... 1996 DBLP  DOI  BibTeX  RDF LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
40Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park Scheduling of conditional branches using SSA form for superscalar/VLIW processors. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF conditional branches scheduling, very long instruction word processors, compensation code, optimization, computational complexity, complexity, parallel architectures, processor scheduling, superscalar processors, instruction sets, instruction set, VLIW processors, code motion, global scheduling, conditional branches, SSA
40John-David Wellman, Edward S. Davidson The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF resource conflict methodology, early-stage design space exploration, superscalar RISC processors, execution trace driven simulation, hardware element model, analysis program, performance evaluation, virtual machines, computer architecture, reduced instruction set computing, design cycle
40Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa A superscalar RISC processor with pseudo vector processing feature. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF superscalar RISC processor, pseudo vector processing, architectural extension, floating-point registers, scoreboard-based dependency check, pipeline stage optimization, 267 MFLOPS, 1.2 Gbyte/s, performance evaluation, performance, computer architecture, memory access, reduced instruction set computing, vector processor systems
40Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker Sentinel Scheduling for VLIW and Superscalar Processors. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
34Steven Swanson, Luke K. McDowell, Michael M. Swift, Susan J. Eggers, Henry M. Levy An evaluation of speculative instruction execution on simultaneous multithreaded processors. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF multiprocessors, multithreading, Instruction-level parallelism, speculation, thread-level parallelism, simultaneous multithreading
34Dean M. Tullsen, Susan J. Eggers, Henry M. Levy Simultaneous Multithreading: Maximizing On-Chip Parallelism. Search on Bibsonomy ISCA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
34Omer Khan, Sandip Kundu A model to exploit power-performance efficiency in superscalar processors via structure resizing. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF modeling, power
34Shruti Patil, Venkatesan Muthukumar Maximizing Resource Utilization by Slicing of Superscalar Architecture. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Thomas Kottke, Andreas Steininger A Fail-Silent Reconfigurable Superscalar Processor. Search on Bibsonomy PRDC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Tejas Karkhanis, James E. Smith 0001 Automated design of application specific superscalar processors: an analytical approach. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance model, analytical model, design optimization, energy model, application specific processors
34Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith 0001 An approach for implementing efficient superscalar CISC processors. Search on Bibsonomy HPCA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Houman Homayoun, Ted H. Szymanski Reducing the Instruction Queue Leakage Power in Superscalar Processors. Search on Bibsonomy CCECE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Jie S. Hu, Greg M. Link, Johnsy K. John, Shuai Wang 0006, Sotirios G. Ziavras Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Kuo-Su Hsiao, Chung-Ho Chen An efficient wakeup design for energy reduction in high-performance superscalar processors. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF issue window, wakeup logic, low power, high performance
34Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch Design of superscalar processor with multi-bank register file. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Ingomar Wenzel, Raimund Kirner, Peter P. Puschner, Bernhard Rieder Principles of Timing Anomalies in Superscalar Processors. Search on Bibsonomy QSIC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Marc Epalza, Paolo Ienne, Daniel Mlynek Adding Limited Reconfigurability to Superscalar Processors. Search on Bibsonomy IEEE PACT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Anne Bracy, Prashant Prahlad, Amir Roth Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth. Search on Bibsonomy MICRO The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Marc Epalza, Paolo Ienne, Daniel Mlynek Dynamic Reallocation of Functional Units in Superscalar Processors. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Mark D. Aagaard, Byron Cook, Nancy A. Day, Robert B. Jones A framework for superscalar microprocessor correctness statements. Search on Bibsonomy Int. J. Softw. Tools Technol. Transf. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Microprocessor correctness, Commuting diagrams, Formal verification, Pipelines
34Ryuichi Takahashi, Hajime Ohiwa Situated Learning on FPGA for Superscalar Microprocessor Design Education. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Tarek M. Taha, D. Scott Wills An Instruction Throughput Model of Superscalar Processors. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Santithorn Bunchua, D. Scott Wills, Linda M. Wills Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34J. L. Silva, R. M. Costa, G. H. R. Jorge RtrASSoc - An Adaptable Superscalar Reconfigurable System-On-Chip. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Ing-Jer Huang, Ping-Huei Xie Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh A Comparison of Asymptotically Scalable Superscalar Processors. Search on Bibsonomy Theory Comput. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Christoforos E. Kozyrakis, David A. Patterson 0001 Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks. Search on Bibsonomy MICRO The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Ravishankar Rao, Mark Oskin, Frederic T. Chong HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space. Search on Bibsonomy HiPC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
34Victor V. Zyuban, Peter M. Kogge Inherently Lower-Power High-Performance Superscalar Architectures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Low power microarchitecture, multicluster architecture, energy-efficient configurations, energy models
34Joydeep Ray, James C. Hoe, Babak Falsafi Dual use of superscalar datapath for transient-fault detection and recovery. Search on Bibsonomy MICRO The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Miroslav N. Velev Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors. Search on Bibsonomy TACAS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Seongwoo Kim, Arun K. Somani SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors. Search on Bibsonomy PRDC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
34Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado A Power Perspective of Value Speculation for Superscalar Microprocessors. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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