Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
122 | Kelly D. Larson |
Translation of an existing VMM-based SystemVerilog testbench to OVM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 237, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
OVM, VMM, testbenches, SystemVerilog |
96 | Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler |
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 50, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
89 | Tom Fitzpatric |
System Verilog for VHDL Users. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1334-1341, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
78 | Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji |
SystemC and SystemVerilog: Where do They Fit? Where are They Going? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 122-129, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
68 | Clifford E. Cummings |
SystemVerilog implicit port enhancements accelerate system design & verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 231-236, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
*, .name, Verilog EMACS mode, implicit ports, Verilog, instantiation, SystemVerilog |
60 | Doron Bustan, John Havlicek |
Some Complexity Results for SystemVerilog Assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 18th International Conference, CAV 2006, Seattle, WA, USA, August 17-20, 2006, Proceedings, pp. 205-218, 2006, Springer, 3-540-37406-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Alexander Krupp, Wolfgang Müller 0003 |
Classification trees for random tests and functional coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1031-1032, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil |
Synthesis of synchronous assertions with guarded atomic actions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 15-24, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Brian Bailey |
Was it worth the wait? Yes! ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(2), pp. 160-161, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
verification, formal verification, design reuse, testbench, SystemVerilog |
42 | Albert Chiang, Wei-Hua Han, Bhanu Kapoor |
Validating physical access layer of WiMAX using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 356-359, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Hai H. Wang, Shengchao Qin, Jun Sun 0001, Jin Song Dong |
Realizing Live Sequence Charts in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TASE ![In: First Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering, TASE 2007, June 5-8, 2007, Shanghai, China, pp. 379-388, 2007, IEEE Computer Society, 0-7695-2856-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
36 | Yingpan Wu, Lixin Yu, Wei Zhuang, Jianyong Wang |
A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 8th IEEE/ACIS International Conference on Computer and Information Science, IEEE/ACIS ICIS 2009, June 1-3, 2009, Shanghai, China, pp. 1049-1054, 2009, IEEE Computer Society, 978-0-7695-3641-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang |
A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 79-88, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler |
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 542-549, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
36 | A. Bernstein, M. Burton, Frank Ghenassia |
How to bridge the abstraction gap in system level modeling and design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 910-914, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
36 | Kausik Datta, Partha Pratim Das |
Assertion Based Verification Using HDVL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 319-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Rishiyur S. Nikhil |
Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). ![Search on Bibsonomy](Pics/bibsonomy.png) |
GPCE ![In: Generative Programming and Component Engineering, 8th International Conference, GPCE 2009, Denver, Colorado, USA, October 4-5, 2009, Proceedings, pp. 1-2, 2009, ACM, 978-1-60558-494-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing |
26 | Michael Siegel, Adriana Maggiore, Christian Pichler |
Untwist your brain: efficient debugging and diagnosis of complex assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 644-647, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SystemVerilog assertions, debugging, assertions, fault localization, functional verification, root cause analysis |
26 | Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch |
Building a standard ESL design and verification methodology: is it just a dream? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 370-371, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
modeling rapid hardware prototyping, design, verification, methodology, systemC, RTL, ESL, C/C++, systemVerilog |
26 | Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee |
Formal hardware specification languages for protocol compliance verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(1), pp. 1-32, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Heterogeneous Hardware Logic, Hierarchical Annotated Action Diagrams, Lava, Objective VHDL, OpenVera, SpecC, Specification and Description Language, The Unified Modeling Language, Java, Statecharts, SystemC, Message Sequence Charts, Esterel, Live Sequence Charts, timing diagrams, hardware monitors, SystemVerilog, e, Property Specification Language |
26 | James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois |
ESys.Net: a new solution for embedded systems modeling and simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 107-114, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog |
24 | Bilal Majeed, Conor Ryan, Jack McEllin, Ayman Youssef, Douglas Mota Dias, Aidan Murphy, Samuel Carvalho |
Evolving Behavioural Level Sequence Detectors in SystemVerilog Using Grammatical Evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAART (3) ![In: Proceedings of the 15th International Conference on Agents and Artificial Intelligence, ICAART 2023, Volume 3, Lisbon, Portugal, February 22-24, 2023., pp. 475-483, 2023, SCITEPRESS, 978-989-758-623-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Wei-Ting Yeh, Chung-Lun Chang, Shang-Chih Yin, Chien-Hung Tsai |
Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCCE ![In: 12th IEEE Global Conference on Consumer Electronics, GCCE 2023, Nara, Japan, October 10-13, 2023, pp. 1172-1175, 2023, IEEE, 979-8-3503-4018-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Michael Kwaku Tetteh, Douglas Mota Dias, Conor Ryan |
Grammatical Evolution of Complex Digital Circuits in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SN Comput. Sci. ![In: SN Comput. Sci. 3(3), pp. 188, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Christos Sapsanis, Martin Villemur, Andreas G. Andreou |
Real Number Modeling of a SAR ADC behavior using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2022, Villasimius, Italy, June 12-15, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-6703-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviades A. Hatzopoulos |
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 37(5), pp. 685-700, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Michael Kwaku Tetteh, Douglas Mota Dias, Conor Ryan |
Evolution of Complex Combinational Logic Circuits Using Grammatical Evolution with SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroGP ![In: Genetic Programming - 24th European Conference, EuroGP 2021, Held as Part of EvoStar 2021, Virtual Event, April 7-9, 2021, Proceedings, pp. 146-161, 2021, Springer, 978-3-030-72811-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Yuichi Kamina, Keisuke Iwai, Takashi Matsubara 0002, Takakazu Kurokawa |
A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR (Workshops) ![In: Eighth International Symposium on Computing and Networking Workshops, CANDAR 2020 Workshops, Naha, Japan, November 24-27, 2020, pp. 87-92, 2020, IEEE, 978-1-7281-9919-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif, Wasi Haider Butt |
A model-driven framework for design and verification of embedded systems through SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 23(3-4), pp. 179-223, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
UVM-based Verification of a Digital PLL Using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, Rhodes, Greece, July 1-3, 2019, pp. 23-28, 2019, IEEE, 978-1-7281-2103-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 22nd Euromicro Conference on Digital System Design, DSD 2019, Kallithea, Greece, August 28-30, 2019, pp. 124-128, 2019, IEEE, 978-1-7281-2862-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Mina Louis, Mohamed Dessouky, Ashraf Salem |
PLL Real Number Modeling in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, July 15-18, 2019, pp. 257-260, 2019, IEEE, 978-1-7281-1201-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Juan-José Crespo, German Maglione Mathey, José L. Sánchez 0002, Francisco J. Alfaro-Cortes, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001 |
Methodology for Decoupled Simulation of SystemVerilog HDL Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCS ![In: 17th International Conference on High Performance Computing & Simulation, HPCS 2019, Dublin, Ireland, July 15-19, 2019, pp. 741-746, 2019, IEEE, 978-1-7281-4484-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
Design of a Digital PLL Real Number Model Using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, Thessaloniki, Greece, May 13-15, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1184-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Athanasios Mekras, Alkiviadis A. Hatzopoulos |
Design of a SystemVerilog-Based VCO Real Number Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, Thessaloniki, Greece, May 13-15, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1184-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos |
UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, pp. 97-102, 2018, IEEE, 978-1-5386-6365-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe |
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, pp. 34-42, 2018, IEEE Computer Society, 978-1-5386-5883-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Michael Bedford Taylor |
Basejump STL: systemverilog needs a standard template library for hardware design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018, pp. 73:1-73:6, 2018, ACM, 978-1-5386-4114-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos |
Efficiency evaluation of a SystemVerilog-based real number model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4788-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif |
Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 21(1), pp. 1-36, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Ka Lok Man, Chi-Un Lei, Hemangee K. Kapoor, Tomas Krilavicius, Jieming Ma, Nan Zhang |
PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Informatics ![In: Comput. Informatics 35(1), pp. 143-176, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
24 | Oriol Arcas-Abella, Nehir Sönmez |
Bluespec SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 165-172, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Aamir M. Khan, Muhammad Rashid |
Generation of SystemVerilog Observers from SysML and MARTE/CCSL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 19th IEEE International Symposium on Real-Time Distributed Computing, ISORC 2016, York, United Kingdom, May 17-20, 2016, pp. 61-68, 2016, IEEE Computer Society, 978-1-4673-9032-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Rashid, Muhammad Waseem Anwar, Farooque Azam |
Expressing embedded systems verification aspects at higher abstraction level - SystemVerilog in Object Constraint Language (SVOCL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SysCon ![In: Annual IEEE Systems Conference, SysCon 2016, Orlando, FL, USA, April 18-21, 2016, pp. 1-7, 2016, IEEE, 978-1-4673-9519-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Ji-Eun Jang, Jaeha Kim |
PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8), pp. 1908-1917, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky |
SystemVerilog assertion debugging: A visualization and pattern matching model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACRIM ![In: IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2015, Victoria, BC, Canada, August 24-26, 2015, pp. 385-390, 2015, IEEE, 978-1-4673-7788-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Jeremy Ridgeway |
Performance of a SystemVerilog Sudoku Solver with VCS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 16th International Workshop on Microprocessor and SOC Test and Verification, MTV 2015, Austin, TX, USA, December 3-4, 2015, pp. 60-66, 2015, IEEE Computer Society, 978-1-5090-0885-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Sara Marconi, Elia Conti, Jorgen Christiansen, Pisana Placidi |
Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSE ![In: IEEE International Symposium on Systems Engineering, ISSE 2015, Rome, Italy, September 28-30, 2015, pp. 391-397, 2015, IEEE, 978-1-4799-1920-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Sara Marconi, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, Tomasz Hemperek |
A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2015, Rome, Italy, May 5-6, 2015, pp. 35-41, 2015, Springer, 978-3-319-47912-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Yunzhong Zhu, Tao Li, Jingpeng Guo, Haiyang Zhou, Fangfa Fu |
A novel low-cost interface design for SystemC and SystemVerilog Co-simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Ning Zhou, Xinyan Gao, Jinzhao Wu, Jianchao Wei, Dakui Li |
Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Appl. Math. ![In: J. Appl. Math. 2014, pp. 194574:1-194574:15, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou |
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 20(1), pp. 7:1-7:23, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Abhishek Jain 0003, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar |
Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1401.3554, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
24 | Jaeha Kim, Si-Jung Yang, Ji-Eun Jang |
PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Xinyan Gao, Ning Zhou, Jinzhao Wu, Dakui Li |
Wu's Characteristic Set Method for SystemVerilog Assertions Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Appl. Math. ![In: J. Appl. Math. 2013, pp. 740194:1-740194:14, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Dave Rich |
The unique challenges of debugging design and verification code jointly in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-7, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
24 | Jonathan Bromley |
If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1-7, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
24 | Kaiming Ho |
SystemVerilog: The new standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013, pp. 1, 2013, IEEE, 978-2-9530504-8-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
24 | Ji-Eun Jang, Si-Jung Yang, Jaeha Kim |
Event-driven simulation of Volterra series models in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013, San Jose, CA, USA, September 22-25, 2013, pp. 1-4, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim |
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, pp. 137:1-137:7, 2013, ACM, 978-1-4503-2071-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang 0006 |
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 29(2), pp. 23-31, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou |
A formal method to improve SystemVerilog functional coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, USA, November 9-10, 2012, pp. 56-63, 2012, IEEE Computer Society, 978-1-4673-2897-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Sangook Moon |
Systemverilog-based approach of a design of multiplication server farms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUFN ![In: Fourth International Conference on Ubiquitous and Future Networks, ICUFN 2012, Puket, Thailand, July 4-6, 2012, pp. 478-479, 2012, IEEE, 978-1-4673-1377-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Sergio H. M. Durand, Vanderlei Bonato |
A tool to support Bluespec SystemVerilog coding based on UML diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: 38th Annual Conference on IEEE Industrial Electronics Society, IECON 2012, Montreal, QC, Canada, October 25-28, 2012, pp. 4670-4675, 2012, IEEE, 978-1-4673-2419-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim |
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-1555-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Jomu George Mani Paret, Otmane Aït Mohamed |
Modeling discrete event system with distributions using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 129-132, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Dominic Richards, David R. Lester |
A monadic approach to automated reasoning for Bluespec SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Innov. Syst. Softw. Eng. ![In: Innov. Syst. Softw. Eng. 7(2), pp. 85-95, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Brian Keng, Sean Safarpour, Andreas G. Veneris |
Automated debugging of SystemVerilog assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 323-328, 2011, IEEE, 978-1-61284-208-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Hans Eveking, Tobias Dornes, Martin Schweikert |
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011, pp. 17-24, 2011, IEEE Computer Society, 978-1-4577-1744-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Ryuichi Takahashi, Yoshiyasu Takefuji |
SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, USA, June 5-6, 2011, pp. 112-113, 2011, IEEE Computer Society, 978-1-4577-0548-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song |
Design and verification of an application-specific PLD using VHDL and SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011, pp. 159-162, 2011, IEEE, 978-1-61284-192-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton |
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DIFTS@FMCAD ![In: Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, Austin, USA, November 3, 2011, 2011, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
24 | Arash Saifhashemi, Peter A. Beerel |
SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPA ![In: 33th Communicating Process Architectures Conference, CPA 2011, organised under the auspices of WoTUG, Limerick, Ireland, June 19th, 2011, pp. 287-302, 2011, IOS Press, 978-1-60750-773-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Myoung-Keun You, Gi-Yong Song |
SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(5), pp. 989-992, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Bahram Hakhamaneshi, Behnam S. Arad |
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: Proceedings of the ISCA 25th International Conference on Computers and Their Applications, CATA 2010, March 24-26, 2010, Sheraton Waikiki Hotel, Honolulu, Hawaii, USA, pp. 224-227, 2010, ISCA, 978-1-880843-75-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
24 | Alexander Bol, Wolfgang Müller 0003, Alexander Krupp |
Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Dresden, Germany, February 22-24, 2010, pp. 167-176, 2010, Fraunhofer Verlag. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
24 | David Rich |
A Solution to the Lack of Multiple Inheritance in SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK, pp. 16-21, 2010, ECSI, Electronic Chips & Systems design Initiative. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
24 | Dominic Richards, David R. Lester |
A Prototype Embedding of Bluespec SystemVerilog in the PVS Theorem Prover. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NASA Formal Methods ![In: Second NASA Formal Methods Symposium - NFM 2010, Washington D.C., USA, April 13-15, 2010. Proceedings, pp. 139-148, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
24 | Chengjie Zang, Shinji Kimura |
Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6), pp. 1454-1463, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Ivan Kastelan, Zoran Krajacevic |
Synthesizable SystemVerilog Assertions as a Methodology for SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS-EERC ![In: First IEEE Eastern European Conference on the Engineering of Computer Based Systems, ECBS-EERC 2009, Novi Sad, Serbia, September 7-8, 2009, pp. 120-127, 2009, IEEE Computer Society, 978-0-7695-3759-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Robert C. Page, Sakar Jain |
Verification of the CoreNet Fabric with SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009, pp. 73-78, 2009, IEEE Computer Society, 978-0-7695-4000-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson |
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 256-261, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Ka Lok Man |
PAFSV: A process algebraic framework for SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMCSIT ![In: Proceedings of the International Multiconference on Computer Science and Information Technology, IMCSIT 2008, Wisla, Poland, 20-22 October 2008, pp. 535-542, 2008, IEEE, 978-83-60810-14-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Ronald W. Mehler |
SystemVerilog Maximum Performance Maneuvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSV ![In: Proceedings of the 2008 International Conference on Modeling, Simulation & Visualization Methods, MSV 2008, Las Vegas, Nevada, USA, July 14-17, 2008, pp. 202-205, 2008, CSREA Press, 1-60132-081-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
24 | Tingjun Wen, Tadeusz Kwasniewski |
Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMAS ![In: 2008 IEEE International Behavioral Modeling and Simulation Workshop, BMAS 2008, San Jose, CA, USA, September 25-26, 2008, pp. 29-34, 2008, IEEE, 978-1-4244-2896-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Peter Jensen, Wolfgang Ecker, Thomas Kruse, Martin Zambaldi |
SystemVerilog: Interface Based Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2004, September 14-17, 2004, Lille, France, Proceedings, pp. 505-518, 2004, ECSI. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Martin Zambaldi, Wolfgang Ecker, Thomas Kruse, Wolfgang Müller 0003 |
The Formal Simulation Semantics of SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2004, September 14-17, 2004, Lille, France, Proceedings, pp. 568-578, 2004, ECSI. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
24 | Phil Moorby |
Design for Verification with SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 378-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | David I. Rich |
The Evolution of SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(4), pp. 82-84, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
18 | Daniel Gajski, Todd M. Austin, Steve Svoboda |
What input-language is the best choice for high level synthesis (HLS)? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 857-858, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
18 | Perry Alexander |
Rosetta: Standardization at the System Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 42(1), pp. 108-110, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough |
Instrumenting AMS assertion verification on commercial platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 21:1-21:47, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion |
18 | Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 |
Intel® atomTM processor core made FPGA-synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 209-218, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
intel atom, synthesizable core, fpga, emulator |
18 | Christian Dax, Felix Klaedtke, Martin Lange |
On Regular Temporal Logics with Past, . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP (2) ![In: Automata, Languages and Programming, 36th Internatilonal Colloquium, ICALP 2009, Rhodes, Greece, July 5-12, 2009, Proceedings, Part II, pp. 175-187, 2009, Springer, 978-3-642-02929-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti |
Inline Assertions - Embedding Formal Properties in a Test Bench. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 71-76, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Alon Gluska, Lior Libis |
Shortening the verification cycle with synthesizable abstract models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 454-459, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
verification, logic design, abstract modeling |
18 | Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks |
H.264 Decoder: A Case Study in Multiple Design Points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 165-174, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Nathaniel J. August |
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 423-428, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pre-silicon, validation, mixed-signal |
18 | Dennis Brophy |
IEEE Market-Oriented Standards Process and the EDA Industry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 729, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi |
Heterogeneous Behavioral Hierarchy Extensions for SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4), pp. 765-780, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|