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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 259 occurrences of 134 keywords
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Results
Found 226 publication records. Showing 226 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
63 | Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
An optimized BIST test pattern generator for delay testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 94-100, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test |
53 | Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck |
Deterministic test generation for non-classical faults on the gate level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 244-251, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST |
52 | María José López, Mar Martínez, Salvador Bracho |
A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 245-258, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
deterministic generation, VLSI, built-in-self-test, integrated circuit |
46 | Wei-Lun Wang, Kuen-Jong Lee |
Accelerated test pattern generators for mixed-mode BIST environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 368-373, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics |
45 | Bei Cao, Liyi Xiao, Yongsheng Wang |
A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 266-269, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri |
An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 260-265, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
An adjacency-based test pattern generator for low power BIST design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 459-464, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length |
41 | H. Daniel Schnurmann, Eric Lindbloom, Robert G. Carpenter |
The Weighted Random Test-Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(7), pp. 695-700, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Fault-detecting patterns, testing, heuristic algorithm, test-pattern generator, large-scale integration, testing algorithms, weighted random patterns |
41 | Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
An effective BIST scheme for carry-save and carry-propagate array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 298-302, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic |
40 | Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham |
Efficient multisine testing of analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 234-238, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits |
39 | Avijit Dutta, Nur A. Touba |
Synthesis of Efficient Linear Test Pattern Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 206-214, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Gregor Papa, Tomasz Garbolino, Franc Novak |
Deterministic Test Pattern Generator Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 204-213, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir |
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 221-226, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Hyung Ki Lee, Dong Sam Ha |
SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 660-666, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
39 | Nan-Cheng Li, Sying-Jyan Wang |
A Reseeding Technique for LFSR-Based BIST Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 200-205, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Reseedling, LFST, BIST, Test Pattern Generator, Pseudo-Random Testing |
38 | Jing-Yang Jou |
An effective BIST design for PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 286-292, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register |
38 | Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly |
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 403-, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel |
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 456-462, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm |
36 | Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee |
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 556-561, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR |
36 | Spyros Tragoudas, Dimitrios Karayiannis |
A fast nonenumerative automatic test pattern generator for pathdelay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 1050-1057, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Aiman H. El-Maleh, Yahya E. Osais |
A retiming-based test pattern generator design for built-in self test of data path architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 550-553, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Dhiraj K. Pradhan, Mitrajit Chatterjee |
GLFSR-a new test pattern generator for built-in-self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2), pp. 238-247, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke |
A new low power test pattern generator using a variable-length ring counter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 248-252, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Chien-In Henry Chen, Kiran George |
Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 111-116, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng |
Pseudofunctional testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1535-1546, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Gang Zeng, Hideo Ito |
Concurrent core test for SOC using shared test set and scan chain disable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1045-1050, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault |
A Ring Architecture Strategy for BIST Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 223-231, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
pseudo-random testing, deterministic BIST, logic BIST |
32 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 306-311, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa |
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 109-122, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction |
31 | Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault |
A Ring Architecture Strategy for BIST Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 418-423, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Zhe Zhao, Bahram Pouya, Nur A. Touba |
BETSY: synthesizing circuits for a specified BIST environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 144-153, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
30 | Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001 |
Test pattern generation for width compression in BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 114-118, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Irith Pomeranz, Sudhakar M. Reddy |
Built-in test generation for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 421-426, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
comparison units, built-in self-test, synchronous sequential circuits, at-speed test |
29 | Tomasz Garbolino, Gregor Papa |
Test Pattern Generator Design Optimization Based on Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: New Frontiers in Applied Artificial Intelligence, 21st International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2008, Wroclaw, Poland, June 18-20, 2008, Proceedings, pp. 580-589, 2008, Springer, 978-3-540-69045-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Costas Laoudias, Dimitris Nikolos |
A new test pattern generator for high defect coverage in a BIST environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 417-420, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
built-in self test, stuck-at fault, path delay fault |
29 | Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri |
Design of hierarchical cellular automata for on-chip test pattern generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12), pp. 1530-1539, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Chih-Ang Chen, Sandeep K. Gupta |
Efficient BIST TPG design and test set compaction via input reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 692-705, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Mohammad Tehranipoor, Reza M. Rad |
Test and recovery for fine-grained nanoscale architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 226, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Vishnupriya Shivakumar, Chinnaiyan Senthilpari, Zubaida Binti Yusoff |
A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 29366-29379, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem |
SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDT ![In: 10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015, pp. 124-128, 2015, IEEE, 978-1-4673-9994-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Dariusz Badura |
Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fehlertolerierende Rechensysteme ![In: Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, Automatisierungssysteme, Methoden, Anwendungen / Automation Systems, Methods, Applications; 4. Internationale GI/ITG/GMA-Fachtagung, Baden-Baden, Deutschland, 20.-22. September 1989, Proceedings, pp. 368-378, 1989, Springer, 3-540-51565-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
28 | Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz |
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 79-82, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu |
A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1883-1886, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Alejandro Czutro, Ilia Polian, Matthew Lewis 0004, Piet Engelke, Sudhakar M. Reddy, Bernd Becker 0001 |
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 227-232, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz |
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 729-734, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Spyros Tragoudas, Vijay Nagarandal |
On-chip embedding mechanisms for large sets of vectors for delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 488-497, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Rainer Dorsch, Hans-Joachim Wunderlich |
Accumulator based deterministic BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 412-421, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hardware pattern generator, BIST, embedded cores |
25 | Tian Chen, Huaguo Liang, Minsheng Zhang, Wei Wang 0310 |
A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICYCS ![In: Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008, Zhang Jia Jie, Hunan, China, November 18-21, 2008, pp. 2272-2277, 2008, IEEE Computer Society, 978-0-7695-3398-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan |
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 479-484, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia |
Pseudo-exhaustive built-in TPG for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9), pp. 1160-1171, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
24 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 376-383, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Dhiraj K. Pradhan, Chunsheng Liu |
EBIST: a novel test generator with built-in fault detection capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1457-1466, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer |
Delay-fault test generation and synthesis for testability under a standard scan design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8), pp. 1217-1231, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
24 | Mohammad Tehranipoor, Reza M. Rad |
Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 943-958, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya |
An Efficient Scan Tree Design for Compact Test Pattern Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1331-1339, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 689-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Alessandro Fin, Franco Fummi |
A VHDL Error Simulator for Functional Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 390-395, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Keiho Akiyama, Kewal K. Saluja |
A method of reducing aliasing in a built-in self-test environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4), pp. 548-553, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
23 | Nan-Cheng Lai, Sying-Jyan Wang |
Delay Test with Embedded Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 29(3), pp. 545-556, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
23 | Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue |
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, pp. 85-90, 2013, IEEE Computer Society, 978-0-7695-5080-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | A. Ahmad |
A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR) ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1102.0884, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
23 | Shaochong Lei, Zhen Wang, Zeye Liu 0002, Feng Liang |
A low cost test pattern generator for test-per-clock BIST scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 7(10), pp. 672-677, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz |
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 653-659, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Irith Pomeranz, Sudhakar M. Reddy |
On methods to match a test pattern generator to a circuit-under-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 432-444, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
23 | Dhiraj K. Pradhan, Mitrajit Chatterjee |
GLFSR - A New Test Pattern Generator for Built-In Self-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994, pp. 481-490, 1994, IEEE Computer Society, 0-7803-2103-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Irith Pomeranz, Sudhakar M. Reddy |
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 998-1007, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
23 | Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich |
Optimal Hardware Pattern Generation for Functional BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 292-297, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Rupsa Chakraborty, Dipanwita Roy Chowdhury |
coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 8th International Conference on Cellular Aotomata for Reseach and Industry, ACRI 2008, Yokohama, Japan, September 23-26, 2008. Proceedings, pp. 506-511, 2008, Springer, 978-3-540-79991-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator |
23 | Xiaoyu Ruan, Rajendra S. Katti |
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(4), pp. 545-556, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
system-on-chips, automatic test pattern generator, Automatic test equipment, test data compression, embedded core testing, run-length coding |
23 | Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto |
A Framework for the Functional Verification of SystemC Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(6), pp. 667-695, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SystemC, test pattern generator, Functional verification |
23 | Chih-Ang Chen, Sandeep K. Gupta 0001 |
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(3), pp. 257-269, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Built-in self-test, cellular automata, linear feedback shift register, test pattern generator, two-pattern testing, pseudo-exhaustive testing |
23 | Dimitrios Kagaris, Spyros Tragoudas |
A multiseed counter TPG with performance guarantee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 34-39, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation |
23 | Jacob Savir, Robert F. Berry |
AC strength of a pattern generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 119-125, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
AC test, level sensitive scan design, test pattern generator, scan path |
23 | Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 95-107, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
nonlinear CA, prohibited pattern set, TPG |
23 | Omar I. Khan, Michael L. Bushnell |
Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 67-76, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Hyoung B. Min, William A. Rogers |
A test methodology for finite state machines using partial scan design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 127-137, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
loop-free circuits, test generation, ATPG, fault, partial scan |
22 | Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis |
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 152-157, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1083-1099, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays |
21 | Christian Dufaza, Hassan Ihs |
A BIST-DFT technique for DC test of analog modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(1-2), pp. 117-133, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST |
21 | Jayawant Kakade, Dimitrios Kagaris |
Minimization of Linear Dependencies Through the Use of Phase Shifters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1877-1882, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Ehsan Atoofian, Zainalabedin Navabi |
A Test Approach for Look-Up Table Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(1), pp. 141-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
LUT testing, TPG with LE, BIST, memory testing, FPGA testing |
20 | Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
A Gated Clock Scheme for Low Power Testing of Logic Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(1), pp. 89-99, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test-per-scan, test-per-clock, low power design, low power test |
20 | Ehsan Atoofian, Zainalabedin Navabi |
A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 84-89, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas |
A new built-in TPG method for circuits with random patternresistant faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), pp. 859-866, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos |
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(3), pp. 315-332, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
test-per-clock schemes, accumulator-based test pattern generators, built-in self-test, linear feedback shift registers, reseeding |
19 | Dimitrios Kagaris, Spyros Tragoudas |
Von Neumann hybrid cellular automata for generating deterministic test sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 308-321, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test (BIST), cellular automata, test pattern generation |
19 | Xiaowei Li 0001, Paul Y. S. Cheung, Hideo Fujiwara |
LFSR-Based Deterministic TPG for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(5), pp. 419-426, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable LFSR, built-in self-test, path delay faults, two-pattern test |
19 | Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi |
Testability Alternatives Exploration through Functional Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 423-430, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
High-level Testability Analysis, Behavioral Test Generation, VHDL, ATPG |
19 | Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz |
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 178-183, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre |
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 314-321, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
AES core, BIST, secure systems |
19 | Martin Straka, Jiri Tobola, Zdenek Kotásek |
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 152-160, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki |
Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 444-449, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai |
Testing and Diagnosis Techniques for LUT-Based FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 414-419, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos |
A New Reseeding Technique for LFSR-Based Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 80-86, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Effective Built-In Self-Test for Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(3), pp. 105-111, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Booth multipliers, Built-In Self Test, design for testability, data paths |
18 | Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, Hao Yan 0002 |
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the Great Lakes Symposium on VLSI 2023, GLSVLSI 2023, Knoxville, TN, USA, June 5-7, 2023, pp. 299-304, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
18 | Soham Roy, Spencer K. Millican, Vishwani D. Agrawal |
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021, pp. 316-321, 2021, IEEE, 978-1-6654-4087-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
18 | Kuen-Wei Yeh, Jiun-Lang Huang |
DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC-Asia ![In: IEEE International Test Conference in Asia, ITC-Asia 2020, Taipei, Taiwan, September 23-25, 2020, pp. 124-129, 2020, IEEE, 978-1-7281-8944-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
18 | G. Naveen Balaji, S. Chenthur Pandian |
Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Clust. Comput. ![In: Clust. Comput. 22(6), pp. 15231-15244, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
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