Search results for "Test-Pattern-Generator"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
63	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
53	Udo Mahlstedt, Jürgen Alt, Ingo Hollenbeck	Deterministic test generation for non-classical faults on the gate level.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	deterministic test pattern generator, gate level fault models, function conversions, nonclassical faults, fault list generator, library-based fault modeling strategy, ISCAS benchmark circuits, scan-based circuits, CMOS cell library, algorithm, fault diagnosis, logic testing, design for testability, ATPG, combinational circuits, combinational circuits, fault simulator, logic CAD, stuck-at faults, CMOS logic circuits, bridging faults, deterministic algorithms, logic simulation, transition faults, automatic test software, test efficiency, CONTEST
52	María José López, Mar Martínez, Salvador Bracho	A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	deterministic generation, VLSI, built-in-self-test, integrated circuit
46	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
45	Bei Cao, Liyi Xiao, Yongsheng Wang	A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata.	DELTA	2008	DBLP DOI BibTeX RDF
43	Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri	An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS).	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
41	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
41	H. Daniel Schnurmann, Eric Lindbloom, Robert G. Carpenter	The Weighted Random Test-Pattern Generator.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Fault-detecting patterns, testing, heuristic algorithm, test-pattern generator, large-scale integration, testing algorithms, weighted random patterns
41	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	An effective BIST scheme for carry-save and carry-propagate array multipliers.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST scheme, carry-propagate array multipliers, carry-save array multipliers, complex VLSI devices, maximum length LFSR, count-based scheme, multiplier cells, VLSI, logic testing, controllability, built-in self test, integrated circuit testing, automatic testing, observability, fault coverage, test pattern generator, multiplying circuits, carry logic
40	Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham	Efficient multisine testing of analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
39	Avijit Dutta, Nur A. Touba	Synthesis of Efficient Linear Test Pattern Generators.	DFT	2006	DBLP DOI BibTeX RDF
39	Gregor Papa, Tomasz Garbolino, Franc Novak	Deterministic Test Pattern Generator Design.	EvoWorkshops	2008	DBLP DOI BibTeX RDF
39	Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir	A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.	IOLTS	2005	DBLP DOI BibTeX RDF
39	Hyung Ki Lee, Dong Sam Ha	SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.	DAC	1990	DBLP DOI BibTeX RDF
39	Nan-Cheng Li, Sying-Jyan Wang	A Reseeding Technique for LFSR-Based BIST Applications.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	Reseedling, LFST, BIST, Test Pattern Generator, Pseudo-Random Testing
38	Jing-Yang Jou	An effective BIST design for PLA.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST design, deterministic test pattern generator, cross point, AND array, fault detection capability, contact fault model, logic testing, built-in self test, integrated circuit testing, combinational circuits, automatic testing, programmable logic arrays, PLA, CMOS logic circuits, characteristic polynomial, stuck-at fault model, multiple input signature register
38	Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly	Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.	VLSI Design	2001	DBLP DOI BibTeX RDF
37	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
36	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
36	Spyros Tragoudas, Dimitrios Karayiannis	A fast nonenumerative automatic test pattern generator for pathdelay faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
35	Aiman H. El-Maleh, Yahya E. Osais	A retiming-based test pattern generator design for built-in self test of data path architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Dhiraj K. Pradhan, Mitrajit Chatterjee	GLFSR-a new test pattern generator for built-in-self-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
34	Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke	A new low power test pattern generator using a variable-length ring counter.	ISQED	2009	DBLP DOI BibTeX RDF
34	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
34	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
33	Gang Zeng, Hideo Ito	Concurrent core test for SOC using shared test set and scan chain disable.	DATE	2006	DBLP DOI BibTeX RDF
32	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	pseudo-random testing, deterministic BIST, logic BIST
32	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
31	Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa	Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	test-per-clock testing, test pattern compression, zero aliasing error, built-in self test, test response compaction
31	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
30	Zhe Zhao, Bahram Pouya, Nur A. Touba	BETSY: synthesizing circuits for a specified BIST environment.	ITC	1998	DBLP DOI BibTeX RDF
30	Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya	Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.	VLSI Design	1998	DBLP DOI BibTeX RDF	Built-in self-test, TPG, delay faults, robust testing, two-pattern tests
30	Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva 0001	Test pattern generation for width compression in BIST.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
30	Irith Pomeranz, Sudhakar M. Reddy	Built-in test generation for synchronous sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	comparison units, built-in self-test, synchronous sequential circuits, at-speed test
29	Tomasz Garbolino, Gregor Papa	Test Pattern Generator Design Optimization Based on Genetic Algorithm.	IEA/AIE	2008	DBLP DOI BibTeX RDF
29	Costas Laoudias, Dimitris Nikolos	A new test pattern generator for high defect coverage in a BIST environment.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	built-in self test, stuck-at fault, path delay fault
29	Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaudhuri	Design of hierarchical cellular automata for on-chip test pattern generator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
29	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
28	Mohammad Tehranipoor, Reza M. Rad	Test and recovery for fine-grained nanoscale architectures.	FPGA	2006	DBLP DOI BibTeX RDF
28	Vishnupriya Shivakumar, Chinnaiyan Senthilpari, Zubaida Binti Yusoff	A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture.	IEEE Access	2021	DBLP DOI BibTeX RDF
28	Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem	SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST.	IDT	2015	DBLP DOI BibTeX RDF
28	Dariusz Badura	Efficiency of Self-Test Path as a Test Pattern Generator and Test Response Compactor.	Fehlertolerierende Rechensysteme	1989	DBLP DOI BibTeX RDF
28	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.	DSD	2005	DBLP DOI BibTeX RDF
28	Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu	A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Alejandro Czutro, Ilia Polian, Matthew Lewis 0004, Piet Engelke, Sudhakar M. Reddy, Bernd Becker 0001	TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.	DSD	2008	DBLP DOI BibTeX RDF
27	Spyros Tragoudas, Vijay Nagarandal	On-chip embedding mechanisms for large sets of vectors for delay test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
26	Rainer Dorsch, Hans-Joachim Wunderlich	Accumulator based deterministic BIST.	ITC	1998	DBLP DOI BibTeX RDF	hardware pattern generator, BIST, embedded cores
25	Tian Chen, Huaguo Liang, Minsheng Zhang, Wei Wang 0310	A Scheme of Test Pattern Generation Based on Reseeding of Segment-Fixing Counter.	ICYCS	2008	DBLP DOI BibTeX RDF
25	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
25	Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia	Pseudo-exhaustive built-in TPG for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
24	Chen-Huan Chiang, Sandeep K. Gupta 0001	BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.	VTS	1997	DBLP DOI BibTeX RDF
24	Dhiraj K. Pradhan, Chunsheng Liu	EBIST: a novel test generator with built-in fault detection capability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
24	Mohammad Tehranipoor, Reza M. Rad	Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	An Efficient Scan Tree Design for Compact Test Pattern Set.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
24	Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS).	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
24	Alessandro Fin, Franco Fummi	A VHDL Error Simulator for Functional Test Generation.	DATE	2000	DBLP DOI BibTeX RDF
23	Keiho Akiyama, Kewal K. Saluja	A method of reducing aliasing in a built-in self-test environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
23	Nan-Cheng Lai, Sying-Jyan Wang	Delay Test with Embedded Test Pattern Generator.	J. Inf. Sci. Eng.	2013	DBLP BibTeX RDF
23	Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue	A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
23	A. Ahmad	A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)	CoRR	2011	DBLP BibTeX RDF
23	Shaochong Lei, Zhen Wang, Zeye Liu 0002, Feng Liang	A low cost test pattern generator for test-per-clock BIST scheme.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
23	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz	Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction.	DAC	1999	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	On methods to match a test pattern generator to a circuit-under-test.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
23	Dhiraj K. Pradhan, Mitrajit Chatterjee	GLFSR - A New Test Pattern Generator for Built-In Self-Test.	ITC	1994	DBLP DOI BibTeX RDF
23	Irith Pomeranz, Sudhakar M. Reddy	A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.	ITC	1993	DBLP DOI BibTeX RDF
23	Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich	Optimal Hardware Pattern Generation for Functional BIST.	DATE	2000	DBLP DOI BibTeX RDF
23	Rupsa Chakraborty, Dipanwita Roy Chowdhury	coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips.	ACRI	2008	DBLP DOI BibTeX RDF	Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator
23	Xiaoyu Ruan, Rajendra S. Katti	Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	system-on-chips, automatic test pattern generator, Automatic test equipment, test data compression, embedded core testing, run-length coding
23	Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto	A Framework for the Functional Verification of SystemC Models.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	SystemC, test pattern generator, Functional verification
23	Chih-Ang Chen, Sandeep K. Gupta 0001	BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Built-in self-test, cellular automata, linear feedback shift register, test pattern generator, two-pattern testing, pseudo-exhaustive testing
23	Dimitrios Kagaris, Spyros Tragoudas	A multiseed counter TPG with performance guarantee.	ICCD	1996	DBLP DOI BibTeX RDF	built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation
23	Jacob Savir, Robert F. Berry	AC strength of a pattern generator.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	AC test, level sensitive scan design, test pattern generator, scan path
23	Sukanta Das, Anirban Kundu, Biplab K. Sikdar, Parimal Pal Chaudhuri	Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	nonlinear CA, prohibited pattern set, TPG
23	Omar I. Khan, Michael L. Bushnell	Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing.	ITC	2004	DBLP DOI BibTeX RDF
23	Hyoung B. Min, William A. Rogers	A test methodology for finite state machines using partial scan design.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	loop-free circuits, test generation, ATPG, fault, partial scan
22	Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis	Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.	IOLTW	2002	DBLP DOI BibTeX RDF
21	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
21	Christian Dufaza, Hassan Ihs	A BIST-DFT technique for DC test of analog modules.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST
21	Jayawant Kakade, Dimitrios Kagaris	Minimization of Linear Dependencies Through the Use of Phase Shifters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
20	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
20	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
20	Ehsan Atoofian, Zainalabedin Navabi	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
20	Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas	A new built-in TPG method for circuits with random patternresistant faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
20	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test-per-clock schemes, accumulator-based test pattern generators, built-in self-test, linear feedback shift registers, reseeding
19	Dimitrios Kagaris, Spyros Tragoudas	Von Neumann hybrid cellular automata for generating deterministic test sequences.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	built-in self-test (BIST), cellular automata, test pattern generation
19	Xiaowei Li 0001, Paul Y. S. Cheung, Hideo Fujiwara	LFSR-Based Deterministic TPG for Two-Pattern Testing.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	configurable LFSR, built-in self-test, path delay faults, two-pattern test
19	Fabrizio Ferrandi, G. Fornara, Donatella Sciuto, G. Ferrara, Franco Fummi	Testability Alternatives Exploration through Functional Testing.	VTS	2000	DBLP DOI BibTeX RDF	High-level Testability Analysis, Behavioral Test Generation, VHDL, ATPG
19	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre	AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis.	DELTA	2008	DBLP DOI BibTeX RDF	AES core, BIST, secure systems
19	Martin Straka, Jiri Tobola, Zdenek Kotásek	Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.	DFT	2007	DBLP DOI BibTeX RDF
19	Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki	Efficient Constraint Extraction for Template-Based Processor Self-Test Generation.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
19	Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai	Testing and Diagnosis Techniques for LUT-Based FPGA's.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
18	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos	A New Reseeding Technique for LFSR-Based Test Pattern Generation.	IOLTW	2001	DBLP DOI BibTeX RDF
18	Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Effective Built-In Self-Test for Booth Multipliers.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF	Booth multipliers, Built-In Self Test, design for testability, data paths
18	Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, Hao Yan 0002	FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
18	Soham Roy, Spencer K. Millican, Vishwani D. Agrawal	Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator.	VLSID	2021	DBLP DOI BibTeX RDF
18	Kuen-Wei Yeh, Jiun-Lang Huang	DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator.	ITC-Asia	2020	DBLP DOI BibTeX RDF
18	G. Naveen Balaji, S. Chenthur Pandian	Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates.	Clust. Comput.	2019	DBLP DOI BibTeX RDF