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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 2136 publication records. Showing 2136 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
132 | Sumit Ghosh |
In Search of the Origin of VHDL's Delta Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 310-315, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs |
96 | Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden |
Improving Design and Verification Productivity with VHDL-200x. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 332-335, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
89 | Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey |
VHDL semantics and validating transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 936-955, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
81 | Ranga Vemuri, R. Kalyanaraman |
Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 201-214, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
80 | Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum |
Program slicing for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(1), pp. 125-137, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Model checking, Formal verification, VHDL, Program slicing, Hardware description languages |
72 | Sumit Ghosh |
P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(1), pp. 28-50, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics |
72 | Sheetanshu L. Pandey, Kothanda R. Subramanian, Philip A. Wilsey |
A Semantic Model of VHDL for Validating Rewriting Algebras. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 167-176, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
rewriting algebras validation, declarative style, process-folding, CAD tool optimization, VHDL, formal model, semantic model, hardware description languages, interval temporal logic, dynamic semantics |
72 | Nelson L. Passos, Edwin Hsing-Mean Sha |
Synthesis of Multi-Dimensional Applications in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 530-535, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Multidimensional Loops, Scheduling, VHDL, Circuit Optimization, Address generation |
71 | Wilco Van Hoogstraeten, Henk Corporaal |
ADVISE: Performance Evaluation of Parallel VHDL Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 30st Annual Simulation Symposium (SS '97), April 7-9, 1997, Atlanta, GA, USA, pp. 146-156, 1997, IEEE Computer Society, 0-8186-7934-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
VHDL compilation, VHDL simulation, partitioning, distributed simulation, Optimistic simulation, multiprocessor simulation |
67 | Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu |
Verification of VHDL Designs Using VAL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 48-53, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
65 | Abdulhadi Shoufan, Zheng Lu 0006, Guido Rößling |
A platform for visualizing digital circuit synthesis with VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 15th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2010, Bilkent, Ankara, Turkey, June 26-30, 2010, pp. 294-298, 2010, ACM, 978-1-60558-729-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
digital circuit synthesis, visualization, animation, VHDL |
59 | Alex Doboli, Ranga Vemuri |
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1504-1520, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
59 | Basant Rajan, R. K. Shyamasundar |
Modeling VHDL in Multiclock ESTEREL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 76-83, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
59 | Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie |
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9), pp. 1327-1340, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
59 | Shenggao Li, Brian Okoon, Mona Mostafa Hella, Mohammed Ismail 0001, Maya Rubeiz |
The Implementation of a VHDL-AMS to SPICE Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 22(2), pp. 113-121, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
52 | Daniel Köb, Bernhard Peischl, Franz Wotawa |
Debugging VHDL Designs Using Temporal Process Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Developments in Applied Artificial Intelligence, 16th International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, IEA/AIE 2003, Laughborough, UK, June 23-26, 2003, Proceedings, pp. 402-415, 2003, Springer, 3-540-40455-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, model-based diagnosis, software debugging |
52 | Dragos Lungeanu, C.-J. Richard Shi |
Parallel and Distributed VHDL Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 658-662, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
52 | Gábor Hosszú, Ferenc Kovács, László Varga 0003 |
Design procedure based on VHDL language transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 407-410, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
52 | Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa |
Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 151-156, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
52 | Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa |
Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10317-10620, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
52 | Petru Eles, Zebo Peng, Alexa Doboli |
VHDL system-level specification and partitioning in a hardware/software co-synthesis environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Third International Workshop on Hardware/Software Codesign, CODES 1994, Grenoble, France, September 22-24, 1994, pp. 49-55, 1994, IEEE Computer Society, 0-8186-6315-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
52 | Ramón D. Acosta, Mark Alexandre, Gary Imken, Bill Read |
The Role of VHDL in the MCC CAD System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 34-39, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
52 | David R. Coelho |
VHDL: A Call for Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 40-47, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
50 | Perry Alexander, Murali Rangarajan, Phillip Baraona |
A Brief Summary of VSPEC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Congress on Formal Methods ![In: FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, Volume II, pp. 1068-1086, 1999, Springer, 3-540-66588-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
VHDL, languages, systems level design, notations, Larch |
50 | Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos |
Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 142-147, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C-to-VHDL compiling, Impulse-C, Smart buffer, FPGA, High-performance computing |
50 | Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee |
Automatic Parallelization of Compiled Event Driven VHDL Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(4), pp. 380-394, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
scheduling, partitioning, VHDL, multithreading, automatic parallelization, event driven simulation, compiled simulation |
50 | Haifeng Zhou, Zhenghui Lin, Wei Cao |
Research on VHDL RTL Synthesis System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 99-103, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser |
50 | B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante |
New Techniques for Accelerating Fault Injection in VHDL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 61-66, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VHDL, Fault Injection |
50 | Stanislaw Deniziak, Krzysztof Sapiecha |
High Level Testbench Generation for VHDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 6th Symposium on Engineering of Computer-Based Systems (ECBS '99), 7-12 March 1999, Nashville, TN, USA. IEEE Computer Society, 1999, pp. 146-151, 1999, IEEE Computer Society, 0-7695-0028-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
simulation, VHDL, testbench |
50 | Michael Mrva |
Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 250-256, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
object-oriented, VHDL, hardware description language |
50 | Eduard Moser, Norbert Mittwollen |
VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 59-63, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Mixed-Domain Modelling, Mixed-Domain Simulation, Automotive Engineering, VHDL-AMS |
50 | Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez Fernández 0001 |
A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(4), pp. 585-616, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
timed logic, formal verification, refinement, VHDL, denotational semantics, digital circuits, program logic |
50 | Côme Rozon |
On the Use of VHDL as a Multi-Valued Logic Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 110-117, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications |
48 | Peter F. A. Middelhoek, Sreeranga P. Rajan |
From VHDL to efficient and first-time-right designs: a formal approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(2), pp. 205-250, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design |
48 | Mark Genoe, Paul Vanoostende, Geert van Wauwe |
On the use of VHDL-based behavioral synthesis for telecom ASIC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 96-103, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities |
45 | A. Sriram, Fadi J. Kurdahi |
Behavioral Modeling of an ATM Switch using SpecCharts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 19-22, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
44 | François Pêcheux, Christophe Lallement, Alain Vachoux |
VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 204-225, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Medard Rieder, Rico Steiner, Cathy Berthouzoz, Francois Corthay, Thomas Sterren |
Synthesized UML, a Practical Approach to Map UML to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RISE ![In: Rapid Integration of Software Engineering Techniques, Second International Workshop, RISE 2005, Heraklion, Crete, Greece, September 8-9, 2005, Revised Selected Papers, pp. 203-217, 2005, Springer, 3-540-34063-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Franz Wotawa |
Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 21(2), pp. 159-172, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
debugging hardware designs, modeling for diagnosis, model-based diagnosis |
44 | J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski |
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 77-80, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
44 | Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang |
A mixed-signal simulator for VHDL-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 287-292, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
44 | Alessandro Fin, Franco Fummi |
A VHDL Error Simulator for Functional Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 390-395, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
44 | Peter A. Walker, Sumit Ghosh |
On the nature and inadequacies of transport timing delay constructs in VHDL descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 894-915, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
44 | Frank Vahid, Sanjiv Narayan, Daniel D. Gajski |
SpecCharts: a VHDL front-end for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6), pp. 694-706, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Allen Dewey, Aart J. de Geus |
VHDL: Toward a Unified View of Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(2), pp. 8-17, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
44 | David R. Coelho |
A VHDL Standard Package for Logic Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(3), pp. 25-32, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
44 | Moon-Jung Chung, Sangchul Kim |
An Object-Oriented VHDL Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 431-436, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
44 | P. C. Ward, James R. Armstrong |
Behavioral Fault Simulation in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 587-593, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
44 | Moe Shahdad |
An Interface between VHDL and EDIF. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 472-478, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
43 | Ernst Christen, Kenneth Bakalar |
VHDL 1076.1 - analog and mixed signal extensions to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 556-561, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
43 | Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi |
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 575-589, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level |
43 | Paul Salama, Maher E. Rizkalla, Michael Eckbauer |
VHDL Implementation of the Fast Wavelet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(3), pp. 223-239, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Mallat's fast Wavelet Transform, VHDL implementation, VLSI, finite state machine, discrete wavelet transform |
43 | Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri |
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(2), pp. 238-271, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis |
43 | C. T. Carr, T. Martin McGinnity, L. J. McDaid |
Integration of UML and VHDL-AMS for analogue system modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 16(1), pp. 80-94, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Analogue, Automated mapping, UML, Circuits, VHDL-AMS |
43 | Régis Leveugle, K. Hadjiat |
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(5), pp. 559-575, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VHDL, fault injection, VLSI design, dependability analysis, digital circuits |
43 | William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza |
Early estimation of the size of VHDL projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 207-212, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VHDL analysis, embedded systems, cost estimation, system-level design, design metrics |
43 | Frédéric Mallet, Daniel Gaffé, Fernand Boéri |
Concurrent Control Systems: From Grafcet to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1230-1234, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
GRAFCET, programmable components, Modelling, FPGA, Specification, VHDL |
43 | William E. McUmber, Betty H. C. Cheng |
UML-Based Analysis of Embedded Systems Using a Mapping to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 4th IEEE International Symposium on High-Assurance Systems Engineering (HASE '99), 17-19 November 1999, Washington, D.C, USA, Proceedings, pp. 56-63, 1999, IEEE Computer Society, 0-7695-0418-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
formal specifications, mappings, VHDL, Object-oriented modeling |
43 | Nouma Izeboudjen, Ahcene Farah, S. Titri, H. Boumeridja |
Digital Implementation of Artificial Neural Networks: From VHDL Description to EPGA Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Engineering Applications of Bio-Inspired Artificial Neural Networks, International Work-Conference on Artificial and Natural Neural Networks, IWANN '99, Alicante, Spain, June 2-4, 1999, Proceedings, Volume II, pp. 139-148, 1999, Springer. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
parametric description, ANN, VHDL, FPGA implementation, top down design |
43 | Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba |
VHDL Teamwork, Organization Units and Workspace Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 297-302, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VHDL analysis, simulation, management, Teamwork, cooperative work, workspace, elaboration |
43 | Matthias Mutz |
Register Transfer Level VHDL Models without Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 153-158, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VHDL RT subset, register transfer level models |
43 | Edwin Naroska |
Parallel VHDL Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 159-163, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Conservative Parallel VHDL simulation, parallel discrete event simulation, PDES |
43 | Jason Coppens, Dhamin Al-Khalili, Côme Rozon |
VHDL Modelling and Analysis of Fault Secure Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 148-152, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Verification, VHDL, Defect Modelling, Fault Security |
43 | Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen |
The Design of an Asynchronous VHDL Synthesizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 44-51, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Synthesis, VHDL, Asynchronous |
43 | Michael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov |
Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 120-129, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
asynchronous circuits' design, simulation, VHDL, Signal Transition Graph (STG) |
43 | Venkatram Krishnaswamy, Prithviraj Banerjee |
Actor Based Parallel VHDL Simulation Using Time Warp. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Parallel and Distributed Simulation ![In: Proceedings of the Tenth Workshop on Parallel and Distributed Simulation, PADS '96, Philadelphia, PA, USA, May 22-24, 1996, pp. 135-142, 1996, IEEE Computer Society, 0-8186-7539-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VHDL, Time Warp, Parallel Discrete Event Simulation |
43 | Michael Münch, Manfred Glesner, Norbert Wehn |
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996., pp. 45-50, 1996, ACM / IEEE Computer Society, 0-8186-7563-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
control-flow dominated VHDL, time-constrainted scheduling, scheduling, ILP, code transformation, resource-constrained scheduling |
43 | Peter A. Walker, Sumit Ghosh |
On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 128-130, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
timing constructs, simulation of hardware descriptions, discrete event simulation, VHDL, Digital simulation, logic Simulation, Timing semantics |
43 | Ali Assi 0001, Bozena Kaminska |
Modeling of communication protocols in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 168-171, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards |
42 | Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, Maria M. Larrondo-Petrie, Carlos Delgado Kloos |
Reasoning about VHDL and VHDL-AMS using Denotational Semantics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 346-352, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
mixed-signal simulation, Language design, Language semantics, VHDL-AMS |
42 | Douglas J. Smith |
VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 771-776, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VHDL |
41 | Oliver Bringmann 0001, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann |
Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 114-119, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL |
37 | Allan H. Anderson, Gary A. Shaw |
Executable Requirements and Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 49-61, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
37 | Richard Maciel, Bruno C. Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo |
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 351-356, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Saeid Moslehpour, Chandrasekhar Puliroju, Christopher L. Spivey |
Simulating VHDL in PSpice Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSS (1) ![In: Advances in Computer and Information Sciences and Engineering, Proceedings of the 2007 International Conference on Systems, Computing Sciences and Software Engineering (SCSS), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2007), Bridgeport, CT, USA, December 3-12, 2007, pp. 461-466, 2007, Springer, 978-1-4020-8740-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | David M. Kunzman, Terry Wilmarth, Laxmikant V. Kalé |
Parallel VHDL simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 37th Winter Simulation Conference, Orlando, FL, USA, December 4-7, 2005, pp. 27, 2005, IEEE Computer Society, 0-7803-9519-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
37 | Tom Fitzpatric |
System Verilog for VHDL Users. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1334-1341, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Charles Hymans |
Design and Implementation of an Abstract Interpreter for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 263-269, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Charles Hymans |
Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 9th International Symposium, SAS 2002, Madrid, Spain, September 17-20, 2002, Proceedings, pp. 444-460, 2002, Springer, 3-540-44235-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Sara Blanc, Joaquin Gracia, Pedro J. Gil |
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 254-262, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Joaquin Gracia, Daniel Gil, Juan Carlos Baraza, Pedro J. Gil |
Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 16-18 December 2002, Tsukuba-City, Ibarski, Japan, pp. 316-320, 2002, IEEE Computer Society, 0-7695-1852-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Yanbing Li, Miriam Leeser |
HML, a novel hardware description language and its translation to VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(1), pp. 1-8, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno |
Fast Hardware-Software Co-simulation Using VHDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 309-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto |
Symbolic Functional Vector Generation for VHDL Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 442-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Cristina Barna, Wolfgang Rosenstiel |
Object-Oriented Reuse Methodology for VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 689-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Kwang-Il Park, Kyu Ho Park |
Event suppression by optimizing VHDL programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8), pp. 682-691, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Peter J. Ashenden, Philip A. Wilsey, Dale E. Martin |
SUAVE: Extending VHDL to Improve Data Modeling Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(2), pp. 34-44, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Tom J. Kazmierski |
A Formal Description of VHDL-AMS Analogue Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 916-920, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Peter J. Andersen, Philip A. Wilsey |
A Comparison of Alternative Extensions for Data Modeling in VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (3) ![In: Thirty-First Annual Hawaii International Conference on System Sciences, Kohala Coast, Hawaii, USA, January 6-9, 1998, pp. 207-215, 1998, IEEE Computer Society, 0-8186-8255-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Chie Dou |
Integration of SDL and VHDL for HW/SW Codesign of Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 188-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
37 | Thomas Egolf, Mark Pettigrew, James Debardelaben, Rahmi Hezar, Shahram Famorzadeh, Anil Kumar Kavipurapu, Moinul H. Khan, Lan-Rong Dung, Kasyapa Balemarthy, Neeraj Desai, Vijay K. Madisetti |
VHDL-based rapid system prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 14(2), pp. 125-156, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Costas Courcoubetis, Werner Damm, Bernhard Josko |
Verification of timing Properties of VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 225-236, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
37 | John C. Willis, Daniel P. Siewiorek |
Optimizing VHDL Compilation for Parallel Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(3), pp. 42-53, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
37 | Mani B. Srivastava, Robert W. Brodersen |
Using VHDL for High-Level, Mixed-Mode System Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 9(3), pp. 31-40, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
37 | Paul J. Menchini |
A Minimalist Approach to VHDL Logic Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(3), pp. 12-23, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
37 | Mart Altmäe |
MINT: a VHDL simulation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 102-106, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
37 | James Armstrong, Chang Cho, Sandeep Shah, Chakravarthy Kosaraju |
The VHDL Validation Suite. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 2-7, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
37 | Paul R. Jordan, Ronald D. Williams |
COMP: A VHDL Composition System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 750-753, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
37 | Joseph Lis, Daniel Gajski |
VHDL Synthesis Using Structured Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 606-609, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
37 | Jayaram Bhasker |
An algorithm for microcode compaction of VHDL behavioral descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 54-58, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
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