Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
132	Sumit Ghosh	In Search of the Origin of VHDL's Delta Delays.	ISQED	2002	DBLP DOI BibTeX RDF	Delta delay, simulation accuracy, BCL, Conlan, continuous systems, simulation, timing, discrete event simulation, VHDL, hardware, hardware description language, HDLs
96	Stephen Bailey, Erich Marschner, Jayaram Bhasker, Jim Lewis, Peter J. Ashenden	Improving Design and Verification Productivity with VHDL-200x.	DATE	2004	DBLP DOI BibTeX RDF
89	Sheetanshu L. Pandey, Kothanda Umamageswaran, Philip A. Wilsey	VHDL semantics and validating transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
81	Ranga Vemuri, R. Kalyanaraman	Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
80	Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum	Program slicing for VHDL.	Int. J. Softw. Tools Technol. Transf.	2002	DBLP DOI BibTeX RDF	Model checking, Formal verification, VHDL, Program slicing, Hardware description languages
72	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
72	Sheetanshu L. Pandey, Kothanda R. Subramanian, Philip A. Wilsey	A Semantic Model of VHDL for Validating Rewriting Algebras.	EUROMICRO	1996	DBLP DOI BibTeX RDF	rewriting algebras validation, declarative style, process-folding, CAD tool optimization, VHDL, formal model, semantic model, hardware description languages, interval temporal logic, dynamic semantics
72	Nelson L. Passos, Edwin Hsing-Mean Sha	Synthesis of Multi-Dimensional Applications in VHDL.	ICCD	1996	DBLP DOI BibTeX RDF	Multidimensional Loops, Scheduling, VHDL, Circuit Optimization, Address generation
71	Wilco Van Hoogstraeten, Henk Corporaal	ADVISE: Performance Evaluation of Parallel VHDL Simulation.	Annual Simulation Symposium	1997	DBLP DOI BibTeX RDF	VHDL compilation, VHDL simulation, partitioning, distributed simulation, Optimistic simulation, multiprocessor simulation
67	Larry M. Augustin, Benoit A. Gennart, Youm Huh, David C. Luckham, Alec G. Stanculescu	Verification of VHDL Designs Using VAL.	DAC	1988	DBLP BibTeX RDF
65	Abdulhadi Shoufan, Zheng Lu 0006, Guido Rößling	A platform for visualizing digital circuit synthesis with VHDL.	ITiCSE	2010	DBLP DOI BibTeX RDF	digital circuit synthesis, visualization, animation, VHDL
59	Alex Doboli, Ranga Vemuri	Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
59	Basant Rajan, R. K. Shyamasundar	Modeling VHDL in Multiclock ESTEREL.	VLSI Design	2000	DBLP DOI BibTeX RDF
59	Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie	Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
59	Shenggao Li, Brian Okoon, Mona Mostafa Hella, Mohammed Ismail 0001, Maya Rubeiz	The Implementation of a VHDL-AMS to SPICE Converter.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
52	Daniel Köb, Bernhard Peischl, Franz Wotawa	Debugging VHDL Designs Using Temporal Process Instances.	IEA/AIE	2003	DBLP DOI BibTeX RDF	debugging of hardware designs, model-based diagnosis, software debugging
52	Dragos Lungeanu, C.-J. Richard Shi	Parallel and Distributed VHDL Simulation.	DATE	2000	DBLP DOI BibTeX RDF
52	Gábor Hosszú, Ferenc Kovács, László Varga 0003	Design procedure based on VHDL language transformations.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
52	Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa	Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis.	VLSI Design	1999	DBLP DOI BibTeX RDF
52	Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa	Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis.	EUROMICRO	1998	DBLP DOI BibTeX RDF
52	Petru Eles, Zebo Peng, Alexa Doboli	VHDL system-level specification and partitioning in a hardware/software co-synthesis environment.	CODES	1994	DBLP DOI BibTeX RDF
52	Ramón D. Acosta, Mark Alexandre, Gary Imken, Bill Read	The Role of VHDL in the MCC CAD System.	DAC	1988	DBLP BibTeX RDF
52	David R. Coelho	VHDL: A Call for Standards.	DAC	1988	DBLP BibTeX RDF
50	Perry Alexander, Murali Rangarajan, Phillip Baraona	A Brief Summary of VSPEC.	World Congress on Formal Methods	1999	DBLP DOI BibTeX RDF	VHDL, languages, systems level design, notations, Larch
50	Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos	Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler.	DELTA	2008	DBLP DOI BibTeX RDF	C-to-VHDL compiling, Impulse-C, Smart buffer, FPGA, High-performance computing
50	Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee	Automatic Parallelization of Compiled Event Driven VHDL Simulation.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	scheduling, partitioning, VHDL, multithreading, automatic parallelization, event driven simulation, compiled simulation
50	Haifeng Zhou, Zhenghui Lin, Wei Cao	Research on VHDL RTL Synthesis System.	DELTA	2002	DBLP DOI BibTeX RDF	VHDL RTL synthesis, ambiguous grammar, language level optimization, inference, formal semantics, parser
50	B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	New Techniques for Accelerating Fault Injection in VHDL Descriptions.	IOLTW	2000	DBLP DOI BibTeX RDF	VHDL, Fault Injection
50	Stanislaw Deniziak, Krzysztof Sapiecha	High Level Testbench Generation for VHDL Models.	ECBS	1999	DBLP DOI BibTeX RDF	simulation, VHDL, testbench
50	Michael Mrva	Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL.	DATE	1998	DBLP DOI BibTeX RDF	object-oriented, VHDL, hardware description language
50	Eduard Moser, Norbert Mittwollen	VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering.	DATE	1998	DBLP DOI BibTeX RDF	Mixed-Domain Modelling, Mixed-Domain Simulation, Automotive Engineering, VHDL-AMS
50	Peter T. Breuer, Carlos Delgado Kloos, Andrés Marín López, Natividad Martínez Madrid, Luis Sánchez Fernández 0001	A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL.	ACM Trans. Program. Lang. Syst.	1997	DBLP DOI BibTeX RDF	timed logic, formal verification, refinement, VHDL, denotational semantics, digital circuits, program logic
50	Côme Rozon	On the Use of VHDL as a Multi-Valued Logic Simulator.	ISMVL	1996	DBLP DOI BibTeX RDF	multi-valued logic simulator, ternary circuits, simulation, VHDL, logic CAD, functionality, circuit analysis computing, hardware description languages, digital circuits, multivalued logic circuits, timing specifications
48	Peter F. A. Middelhoek, Sreeranga P. Rajan	From VHDL to efficient and first-time-right designs: a formal approach.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	CDFG, SFG, rapid system prototyping, VHDL, VHDL, design methodology, correctness by construction, transformational design
48	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
45	A. Sriram, Fadi J. Kurdahi	Behavioral Modeling of an ATM Switch using SpecCharts.	VLSI Design	1996	DBLP DOI BibTeX RDF
44	François Pêcheux, Christophe Lallement, Alain Vachoux	VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
44	Medard Rieder, Rico Steiner, Cathy Berthouzoz, Francois Corthay, Thomas Sterren	Synthesized UML, a Practical Approach to Map UML to VHDL.	RISE	2005	DBLP DOI BibTeX RDF
44	Franz Wotawa	Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results.	Appl. Intell.	2004	DBLP DOI BibTeX RDF	debugging hardware designs, modeling for diagnosis, model-based diagnosis
44	J. A. López, Ginés Doménech, R. Ruiz, Tom J. Kazmierski	Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
44	Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang	A mixed-signal simulator for VHDL-AMS.	ASP-DAC	2001	DBLP DOI BibTeX RDF
44	Alessandro Fin, Franco Fummi	A VHDL Error Simulator for Functional Test Generation.	DATE	2000	DBLP DOI BibTeX RDF
44	Peter A. Walker, Sumit Ghosh	On the nature and inadequacies of transport timing delay constructs in VHDL descriptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
44	Frank Vahid, Sanjiv Narayan, Daniel D. Gajski	SpecCharts: a VHDL front-end for embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
44	Allen Dewey, Aart J. de Geus	VHDL: Toward a Unified View of Design.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
44	David R. Coelho	A VHDL Standard Package for Logic Modeling.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
44	Moon-Jung Chung, Sangchul Kim	An Object-Oriented VHDL Design Environment.	DAC	1990	DBLP DOI BibTeX RDF
44	P. C. Ward, James R. Armstrong	Behavioral Fault Simulation in VHDL.	DAC	1990	DBLP DOI BibTeX RDF
44	Moe Shahdad	An Interface between VHDL and EDIF.	DAC	1987	DBLP DOI BibTeX RDF
43	Ernst Christen, Kenneth Bakalar	VHDL 1076.1 - analog and mixed signal extensions to VHDL.	EURO-DAC	1996	DBLP DOI BibTeX RDF
43	Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi	Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level
43	Paul Salama, Maher E. Rizkalla, Michael Eckbauer	VHDL Implementation of the Fast Wavelet Transform.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	Mallat's fast Wavelet Transform, VHDL implementation, VLSI, finite state machine, discrete wavelet transform
43	Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri	A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	genetic algorithms, branch-and-bound, performance estimation, VHDL-AMS, Analog synthesis
43	C. T. Carr, T. Martin McGinnity, L. J. McDaid	Integration of UML and VHDL-AMS for analogue system modelling.	Formal Aspects Comput.	2004	DBLP DOI BibTeX RDF	Analogue, Automated mapping, UML, Circuits, VHDL-AMS
43	Régis Leveugle, K. Hadjiat	Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	VHDL, fault injection, VLSI design, dependability analysis, digital circuits
43	William Fornaciari, Fabio Salice, Daniele Paolo Scarpazza	Early estimation of the size of VHDL projects.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	VHDL analysis, embedded systems, cost estimation, system-level design, design metrics
43	Frédéric Mallet, Daniel Gaffé, Fernand Boéri	Concurrent Control Systems: From Grafcet to VHDL.	EUROMICRO	2000	DBLP DOI BibTeX RDF	GRAFCET, programmable components, Modelling, FPGA, Specification, VHDL
43	William E. McUmber, Betty H. C. Cheng	UML-Based Analysis of Embedded Systems Using a Mapping to VHDL.	HASE	1999	DBLP DOI BibTeX RDF	formal specifications, mappings, VHDL, Object-oriented modeling
43	Nouma Izeboudjen, Ahcene Farah, S. Titri, H. Boumeridja	Digital Implementation of Artificial Neural Networks: From VHDL Description to EPGA Implementation.	IWANN (2)	1999	DBLP DOI BibTeX RDF	parametric description, ANN, VHDL, FPGA implementation, top down design
43	Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba	VHDL Teamwork, Organization Units and Workspace Management.	DATE	1998	DBLP DOI BibTeX RDF	VHDL analysis, simulation, management, Teamwork, cooperative work, workspace, elaboration
43	Matthias Mutz	Register Transfer Level VHDL Models without Clocks.	DATE	1998	DBLP DOI BibTeX RDF	VHDL RT subset, register transfer level models
43	Edwin Naroska	Parallel VHDL Simulation.	DATE	1998	DBLP DOI BibTeX RDF	Conservative Parallel VHDL simulation, parallel discrete event simulation, PDES
43	Jason Coppens, Dhamin Al-Khalili, Côme Rozon	VHDL Modelling and Analysis of Fault Secure Systems.	DATE	1998	DBLP DOI BibTeX RDF	Verification, VHDL, Defect Modelling, Fault Security
43	Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen	The Design of an Asynchronous VHDL Synthesizer.	DATE	1998	DBLP DOI BibTeX RDF	Synthesis, VHDL, Asynchronous
43	Michael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov	Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment.	ACSD	1998	DBLP DOI BibTeX RDF	asynchronous circuits' design, simulation, VHDL, Signal Transition Graph (STG)
43	Venkatram Krishnaswamy, Prithviraj Banerjee	Actor Based Parallel VHDL Simulation Using Time Warp.	Workshop on Parallel and Distributed Simulation	1996	DBLP DOI BibTeX RDF	VHDL, Time Warp, Parallel Discrete Event Simulation
43	Michael Münch, Manfred Glesner, Norbert Wehn	An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions.	ISSS	1996	DBLP DOI BibTeX RDF	control-flow dominated VHDL, time-constrainted scheduling, scheduling, ILP, code transformation, resource-constrained scheduling
43	Peter A. Walker, Sumit Ghosh	On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions.	ICCD	1996	DBLP DOI BibTeX RDF	timing constructs, simulation of hardware descriptions, discrete event simulation, VHDL, Digital simulation, logic Simulation, Timing semantics
43	Ali Assi 0001, Bozena Kaminska	Modeling of communication protocols in VHDL.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	ISO/CCITT class O, VLSI, VLSI, high level synthesis, VHDL, transport protocols, transport protocol, communication protocols, hardware description languages, hardware implementations, high level design, ISO standards
42	Peter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, Maria M. Larrondo-Petrie, Carlos Delgado Kloos	Reasoning about VHDL and VHDL-AMS using Denotational Semantics.	DATE	1999	DBLP DOI BibTeX RDF	mixed-signal simulation, Language design, Language semantics, VHDL-AMS
42	Douglas J. Smith	VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C.	DAC	1996	DBLP DOI BibTeX RDF	VHDL
41	Oliver Bringmann 0001, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann	Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL
37	Allan H. Anderson, Gary A. Shaw	Executable Requirements and Specifications.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
37	Richard Maciel, Bruno C. Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo	A Methodology and Toolset to Enable SystemC and VHDL Co-simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
37	Saeid Moslehpour, Chandrasekhar Puliroju, Christopher L. Spivey	Simulating VHDL in PSpice Software.	SCSS (1)	2007	DBLP DOI BibTeX RDF
37	David M. Kunzman, Terry Wilmarth, Laxmikant V. Kalé	Parallel VHDL simulation.	WSC	2005	DBLP BibTeX RDF
37	Tom Fitzpatric	System Verilog for VHDL Users.	DATE	2004	DBLP DOI BibTeX RDF
37	Charles Hymans	Design and Implementation of an Abstract Interpreter for VHDL.	CHARME	2003	DBLP DOI BibTeX RDF
37	Charles Hymans	Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation.	SAS	2002	DBLP DOI BibTeX RDF
37	Sara Blanc, Joaquin Gracia, Pedro J. Gil	A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques.	DFT	2002	DBLP DOI BibTeX RDF
37	Joaquin Gracia, Daniel Gil, Juan Carlos Baraza, Pedro J. Gil	Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture.	PRDC	2002	DBLP DOI BibTeX RDF
37	Yanbing Li, Miriam Leeser	HML, a novel hardware description language and its translation to VHDL.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
37	Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno	Fast Hardware-Software Co-simulation Using VHDL Models.	DATE	1999	DBLP DOI BibTeX RDF
37	Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto	Symbolic Functional Vector Generation for VHDL Specifications.	DATE	1999	DBLP DOI BibTeX RDF
37	Cristina Barna, Wolfgang Rosenstiel	Object-Oriented Reuse Methodology for VHDL.	DATE	1999	DBLP DOI BibTeX RDF
37	Kwang-Il Park, Kyu Ho Park	Event suppression by optimizing VHDL programs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
37	Peter J. Ashenden, Philip A. Wilsey, Dale E. Martin	SUAVE: Extending VHDL to Improve Data Modeling Support.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
37	Tom J. Kazmierski	A Formal Description of VHDL-AMS Analogue Systems.	DATE	1998	DBLP DOI BibTeX RDF
37	Peter J. Andersen, Philip A. Wilsey	A Comparison of Alternative Extensions for Data Modeling in VHDL.	HICSS (3)	1998	DBLP DOI BibTeX RDF
37	Chie Dou	Integration of SDL and VHDL for HW/SW Codesign of Communication Systems.	EUROMICRO	1997	DBLP DOI BibTeX RDF
37	Thomas Egolf, Mark Pettigrew, James Debardelaben, Rahmi Hezar, Shahram Famorzadeh, Anil Kumar Kavipurapu, Moinul H. Khan, Lan-Rong Dung, Kasyapa Balemarthy, Neeraj Desai, Vijay K. Madisetti	VHDL-based rapid system prototyping.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
37	Costas Courcoubetis, Werner Damm, Bernhard Josko	Verification of timing Properties of VHDL.	CAV	1993	DBLP DOI BibTeX RDF
37	John C. Willis, Daniel P. Siewiorek	Optimizing VHDL Compilation for Parallel Simulation.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
37	Mani B. Srivastava, Robert W. Brodersen	Using VHDL for High-Level, Mixed-Mode System Simulation.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
37	Paul J. Menchini	A Minimalist Approach to VHDL Logic Modeling.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
37	Mart Altmäe	MINT: a VHDL simulation system.	EURO-DAC	1990	DBLP DOI BibTeX RDF
37	James Armstrong, Chang Cho, Sandeep Shah, Chakravarthy Kosaraju	The VHDL Validation Suite.	DAC	1990	DBLP DOI BibTeX RDF
37	Paul R. Jordan, Ronald D. Williams	COMP: A VHDL Composition System.	DAC	1989	DBLP DOI BibTeX RDF
37	Joseph Lis, Daniel Gajski	VHDL Synthesis Using Structured Modeling.	DAC	1989	DBLP DOI BibTeX RDF
37	Jayaram Bhasker	An algorithm for microcode compaction of VHDL behavioral descriptions.	MICRO	1987	DBLP DOI BibTeX RDF