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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 148 occurrences of 90 keywords
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Results
Found 270 publication records. Showing 270 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
177 | Aswath Oruganti, Nagarajan Ranganathan |
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 766-769, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
143 | Yu Ching Chang, King Ho Tam, Lei He 0001 |
Power-optimal repeater insertion considering Vdd and Vth as design freedoms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 137-142, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, buffer insertion |
123 | Michael Liu, Wei-Shen Wang, Michael Orshansky |
Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 2-7, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
variability, yield, power minimization |
109 | Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari |
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 67-74, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing |
95 | Chandra S. Nagarajan, Lin Yuan, Gang Qu 0001, Barbara G. Stamps |
Leakage optimization using transistor-level dual threshold voltage cell library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 62-67, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
91 | Takayasu Sakurai |
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 417-424, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VDD, VTH, VLSI, Low-power, CMOS |
89 | Weixiang Shen, Yici Cai, Xianlong Hong |
Leakage power optimization for clock network using dual-Vth technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2769-2772, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
81 | Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge |
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 650-651, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
75 | S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur |
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 509-514, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
75 | Tadahiro Kuroda |
Optimization and control of VDD and VTH for low-power, high-speed CMOS design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 28-34, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
68 | Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001 |
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 900-905, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation |
68 | Tarun Sairam, Wei Zhao, Yu Cao 0001 |
Optimizing finfet technology for high-speed and low-power design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 73-77, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power, energy, variations, speed, threshold voltage, FinFET, noise margin |
68 | Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge |
Total leakage optimization strategies for multi-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 381-384, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, cache memory, gate leakage |
63 | Xiaoyong Tang, Hai Zhou 0001, Prithviraj Banerjee |
Leakage power optimization with dual-Vth library in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 202-207, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
dual-Vth, optimization, high-level synthesis, leakage power |
62 | Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu |
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 14-19, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
differential-pair circuit, radix-2 signed-digit adder, reliability |
62 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 783-787, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, power dissipation, multiple voltages |
62 | E. Seebacher, Gerhard Rappitsch, H. Höller |
Process Characterization for Low VTH and Low Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 70-79, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
62 | Kaushik Roy 0001, Liqiong Wei, Zhanping Chen |
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 366-370, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Min Ni, Seda Ogrenci Memik |
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 610-613, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dual-Vth, leakage power optimization, gate sizing, clock skew scheduling |
54 | Hamed F. Dadgour, Vivek De, Kaustav Banerjee |
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 270-277, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal |
Leakage power reduction using stress-enhanced layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 912-917, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance, mobility, layout, leakage, stress |
54 | Armin Wellig, Julien Zory |
Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 488-497, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma |
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 421-426, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer |
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 158-163, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dual threshold, sizing, dual supply voltage, simultaneous |
54 | Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa |
Automated selective multi-threshold design for ultra-low standby applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 202-206, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
standby leakage current, automated design, multi-threshold |
54 | Vjekoslav Svilan, Masataka Matsui, James B. Burr |
Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 268-272, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
48 | Frank Sill, Frank Grassert, Dirk Timmermann |
Low power gate-level design with mixed-Vth (MVT) techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 278-282, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
MVT, leakage currents, threshold voltage |
48 | Chris H. Kim, Kaushik Roy 0001 |
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 163-167, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
42 | Bohan Lu, Miao Cui, Wen Liu |
The Impact of AlGaN Barrier on Transient VTH Shifts and VTH Hysteresis in Depletion and Enhancement mode AlGaN/GaN MIS-HEMTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: International Conference on IC Design and Technology, ICICDT 2019, Suzhou, China, June 17-19, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-1853-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
41 | Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen 0024, Yu Cao 0001, Lawrence T. Clark |
In-situ characterization and extraction of SRAM variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 711-716, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SRAM test, data retention voltage, threshold voltage variation, write margin, extraction |
41 | Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw |
STEEL: a technique for stress-enhanced standard cell library design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 691-697, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Maziar Goudarzi, Tohru Ishihara, Hamid Noori |
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 224-239, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
process variation, cache memory, Leakage power, power reduction |
41 | Christian Piguet, Christian Schuster, Jean-Luc Nagel |
Static and Dynamic Power Reduction by Architecture Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 659-668, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Chanseok Hwang, Chang Woo Kang, Massoud Pedram |
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 741-746, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Yen-Te Ho, TingTing Hwang |
Low power design using dual threshold voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 205-208, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Imad A. Ferzli, Farid N. Najm |
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 856-859, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
statistical analysis, leakage current, power grid, voltage drop |
35 | Hui Shao, Chi-Ying Tsui |
Low energy level converter design for sub-Vth logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 107-108, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram |
Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 274-281, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Sherif A. Tawfik, Volkan Kursun |
Multi-Vth Level Conversion Circuits for Multi-VDD Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1397-1400, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Mongkol Ekpanyapong, Sung Kyu Lim |
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 142-148, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
supply and threshold voltage scaling, low power design, retiming |
35 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 718-719, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Sherif A. Tawfik, Volkan Kursun |
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 62-67, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD |
27 | Basab Datta, Wayne P. Burleson |
Temperature effects on energy optimization in sub-threshold circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 680-685, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Amir Khatib Zadeh, Catherine H. Gebotys |
Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 230-235, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Yun Ye, Frank Liu 0001, Min Chen 0024, Yu Cao 0001 |
Variability analysis under layout pattern-dependent rapid-thermal annealing process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 551-556, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dopant activation, layout pattern, rapid-thermal annealing, threshold voltage variation, physical design |
27 | Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa |
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 3:1-3:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, configuration, within-die variation, timing yield |
27 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
Failure analysis for ultra low power nano-CMOS SRAM under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 251-254, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura |
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 403-406, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
code allocation, low power design, on-chip memory |
27 | Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim |
Yield-driven near-threshold SRAM design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 660-666, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Rodrigo Jaramillo-Ramirez, Mohab Anis |
A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3724-3727, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Lih-Yih Chiou, Shien-Chun Luo |
An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1157-1160, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Frank Sill, Jiaxi You, Dirk Timmermann |
Design of mixed gates for leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 263-268, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mixed gates, leakage current, threshold voltage, gate leakage |
27 | Yuanlin Lu, Vishwani D. Agrawal |
Statistical Leakage and Timing Optimization for Submicron Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 439-444, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | B. Chung, J. B. Kuo |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 237-246, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi |
Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1394-1398, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen |
Engery-Efficient Double-Edge Triggered Flip-Flop Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1791-1794, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Visvesh S. Sathe 0001, Marios C. Papaefthymiou, Conrad H. Ziesler |
A GHz-class charge recovery logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 91-94, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
resonant systems, energy recovery, adiabatic |
27 | Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal |
On the Advantages of Serial Architectures for Low-Power Reliable Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 276-281, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger |
Sleepy Stack Reduction of Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 148-158, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee |
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 884-887, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
electrothermal couplings, temperature aware design, subthreshold leakage, energy delay product |
27 | Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong |
An MTCMOS design methodology and its application to mobile computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 110-115, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CPFF, low power, leakage current, CCS, MTCMOS |
27 | Hyunsik Im |
Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 13-18, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
?-power model, MOSFET modeling, Saturation current |
27 | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai |
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 228-230, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
gate capacitance, low supply voltage, low-power design |
27 | Mircea R. Stan |
Optimal Voltages and Sizing for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 428-433, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Yong-Hwa Wen, Tz-Wun Wang, Tzu-Hsien Yang, Sheng-Hsi Hung, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai |
A -10 to -20-V Inverting Buck-Boost Drive GaN Driver With Sub-1-μA Leakage Current Vth Tracking Technique for 20-MHz Depletion-Mode GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(2), pp. 497-507, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Bo Yi, Yi Xu, LiTian Zheng, Junji Cheng, Haimeng Huang, MouFu Kong, Hongqiang Yang |
Modeling and simulation of an insulated-gate HEMT using p-SnO2 gate for high VTH design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 139, pp. 105895, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Marcello Cioni, G. Giorgino, Alessandro Chini, Carmine Miccoli, Maria Eloisa Castagna, M. Moschetti, C. Tringali, Ferdinando Iucolano |
Evidence of Carbon Doping Effect on VTH Drift and Dynamic-RON of 100V p-GaN Gate AlGaN/GaN HEMTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yuye Kang, Kaizhen Han, Yue Chen, Xiao Gong |
Thickness-Engineered Extremely-thin Channel High Performance ITO TFTs with Raised S/D Architecture: Record-Low RSD, Highest Moblity (Sub-4 nm TCH Regime), and High VTH Tunability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Sonu Hooda, Chun-Kuei Chen, Manohar Lal, Shih-Hao Tsai, Evgeny Zamburg, Aaron Voon-Yew Thean |
Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Xianzhou Shao, Junshuai Chai, Min Liao, Jiahui Duan, Fengbin Tian, Xiaoyu Ke, Xiaoqing Sun, Hao Xu, Jinjuan Xiang, Xiaolei Wang, Wenwu Wang 0006 |
Comprehensive Study of Endurance Fatigue in the Scaled Si FeFET by in-situ Vth Measurement and Endurance Enhancement Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMW ![In: IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-7459-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Mohith Amara, Indranil Bhattacharjee, Gajendranath Chowdary |
A 19 pJ-K2 Temperature Sensor using Sub-VTH Ring Oscillator with 1.28°C/V Line Sensitivity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Pablo A. Petrashin, Walter J. Lancioni, Agustin Laprovitta, Fortunato Dualibe, Juan Luis Castagnola |
Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 24th IEEE Latin American Test Symposium, LATS 2023, Veracruz, Mexico, March 21-24, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2597-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Shun'ichiro Ohmi, Masakazu Tanuma, Joong-Won Shin |
Precise VTH Control of MFSFET with 5 nm-thick FeND-HfO2 Realized by Kr-Plasma Sputtering for Pt Gate Electrode Deposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2023, Santa Barbara, CA, USA, June 25-28, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-2310-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | P. C. Chang, P. J. Liao, D. W. Heh, C. Lee, D. H. Hou, Elia Ambrosi, C. H. Wu, H. Y. Lee, J. H. Lee, Xinyu Bao |
Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 4, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Fabrizio Masin, Carlo De Santi, Arno Stockman, J. Lettens, F. Geenen, Gaudenzio Meneghesso, Enrico Zanoni, Peter Moens, Matteo Meneghini |
Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs at Room and Cryogenic-Temperature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 5, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Marcello Cioni, Patrick Fiorenza, Fabrizio Roccaforte, Mario Saggio, S. Cascino, Angelo Alberto Messina, Vincenzo Vinciguerra, Michele Calabretta, Alessandro Chini |
Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 5, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Camille Leurquin, William Vandendaele, Aby-Gaël Viey, Romain Gwoziecki, René Escoffier, R. Salot, G. Despesse, Ferdinando Iucolano, Roberto Modica, A. Constant |
Novel High Voltage Bias Temperature Instabilities (HV-BTI) setup to monitor RON/VTH drift on GaN-on-Si E-mode MOSc-HEMTs under drain voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 10, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi |
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 306-307, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Kailiang Huang, Xinlv Duan, Junxiao Feng, Ying Sun, Congyan Lu, Chuanke Chen, Guangfan Jiao, Xinpeng Lin, Jinhai Shao, Shihui Yin, Jiazhen Sheng, Zhaogui Wang, Wenqiang Zhang, Xichen Chuai, Jiebin Niu, Wenwu Wang 0006, Ying Wu, Weiliang Jing, Zhengbo Wang, Jeffrey Xu, Guanhua Yang, Di Geng, Ling Li, Ming Liu |
Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 296-297, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Muhammad Abrar Akram, Sohmyung Ha |
A 433.92-MHz CMOS Rectifier with Dynamic VTH-reduction for Wireless Biomedical Implants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BioCAS ![In: IEEE Biomedical Circuits and Systems Conference, BioCAS 2022, Taipei, Taiwan, October 13-15, 2022, pp. 16-20, 2022, IEEE, 978-1-6654-6917-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Liron Lisha, Ori Bass, Joseph Shor |
A 5800 μm² Process Monitor Circuit for Measurement of in-Die Variation of Vth in 65nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(3), pp. 863-867, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Marcello Cioni, Alessandro Bertacchini, Alessandro Mucci, Giovanni Verzellesi, Paolo Pavan, Alessandro Chini |
Investigation on VTH and RON Slow/Fast Drifts in SiC MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2021, Monterey, CA, USA, March 21-25, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-6893-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Anuradha Chathuranga Ranasinghe, Sabih H. Gerez |
Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021, pp. 57-65, 2021, IEEE, 978-1-6654-3219-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Mengyuan Hua, Junting Chen, Chengcai Wang, Lingling Li, Ling Liu, Zheyang Zheng, Kevin J. Chen |
E-mode p-FET-bridge HEMT: Toward high VTH, low reverse-conduction loss and enhanced stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Munir Ahmad Al-Absi, Sami R. Al-Batati |
Hybrid Internal Vth Cancellation Rectifiers for RF Energy Harvesting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 51976-51980, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Bumjin Park, Youngwoo Ji, Jae-Yoon Sim |
A 490-pW SAR Temperature Sensor With a Leakage-Based Bandgap-Vth Reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(9), pp. 1549-1553, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Ren Usami, Takao Komiyama, Yasunori Chonan, Hiroyuki Yamaguchi, Koji Kotani |
Photovoltaic-assisted self-Vth-cancellation CMOS rectifier for synergistic RF energy harvesting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 17(13), pp. 20200186, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Nayoung Choi, Jaeha Kim |
Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, pp. 52:1-52:8, 2020, IEEE. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Shuang Li, Zhichao Du, Yu Wang 0097, Fei Liu, Qi Wang 0041, Zongliang Huo |
Adaptive Pulse Program Scheme to Improve the Vth Distribution for 3D NAND Flash. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Anuradha Chathuranga Ranasinghe, Sabih H. Gerez |
Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Syed Huzaif Ali, Enes Ugur, Bilal Akin |
Analysis of Vth Variations in IGBTs Under Thermal Stress for Improved Condition Monitoring in Automotive Power Conversion Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Veh. Technol. ![In: IEEE Trans. Veh. Technol. 68(1), pp. 193-202, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Kunliang Wang, Gang Du, Zhiyuan Lun, Wangyong Chen, Xiaoyan Liu |
Modeling of program Vth distribution for 3-D TLC NAND flash memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 62(4), pp. 42401:1-42401:10, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Besar Asllani, Alberto Castellazzi, Oriol Avino-Salvado, Asad Fayyaz, Hervé Morel, Dominique Planson |
VTH-Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2019, Monterey, CA, USA, March 31 - April 4, 2019, pp. 1-6, 2019, IEEE, 978-1-5386-9504-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim |
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, pp. 308-310, 2019, IEEE, 978-1-5386-8531-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi |
Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2-D and 3-D-TLC NAND Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(10), pp. 2917-2926, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Besar Asllani, Asad Fayyaz, Alberto Castellazzi, Hervé Morel, Dominique Planson |
VTH subthreshold hysteresis technology and temperature dependence in commercial 4H-SiC MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 604-609, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen |
Reliability-Aware Multi-Vth Domain Digital Design Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2018, Budapest, Hungary, April 25-27, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-5754-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Miroslav Potocný, Viera Stopjaková, Martin Kovác |
Self Vth-Compensating CMOS On-Chip Rectifier for Inductively Powered Implantable Medical Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2018, Budapest, Hungary, April 25-27, 2018, pp. 158-161, 2018, IEEE, 978-1-5386-5754-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Ren Usami, Takao Komiyama, Yasunori Chonan, Hiroyuki Yamaguchi, Koji Kotani |
Photovoltaic-Assisted Self-Vth-Cancellation CMOS RF Rectifier for Wide Power Range Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 115-118, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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21 | Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue |
Accurate Nanopower Supply-Insensitive CMOS Unit Vth Extractor and αVth Extractor with Continuous Variety. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(5), pp. 1145-1155, 2017. The full citation details ...](Pics/full.jpeg) |
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