Search results for "VTH"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
177	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
143	Yu Ching Chang, King Ho Tam, Lei He 0001	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
123	Michael Liu, Wei-Shen Wang, Michael Orshansky	Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation.	ISLPED	2004	DBLP DOI BibTeX RDF	variability, yield, power minimization
109	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
95	Chandra S. Nagarajan, Lin Yuan, Gang Qu 0001, Barbara G. Stamps	Leakage optimization using transistor-level dual threshold voltage cell library.	ISQED	2009	DBLP DOI BibTeX RDF
91	Takayasu Sakurai	Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control.	ISQED	2000	DBLP DOI BibTeX RDF	VDD, VTH, VLSI, Low-power, CMOS
89	Weixiang Shen, Yici Cai, Xianlong Hong	Leakage power optimization for clock network using dual-Vth technology.	ISCAS	2008	DBLP DOI BibTeX RDF
81	Robert Bai, Nam Sung Kim, Taeho Kgil, Dennis Sylvester, Trevor N. Mudge	Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage.	DATE	2005	DBLP DOI BibTeX RDF
75	S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur	Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block.	VLSI Design	2008	DBLP DOI BibTeX RDF
75	Tadahiro Kuroda	Optimization and control of VDD and VTH for low-power, high-speed CMOS design.	ICCAD	2002	DBLP DOI BibTeX RDF
68	Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001	Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.	DAC	2008	DBLP DOI BibTeX RDF	atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation
68	Tarun Sairam, Wei Zhao, Yu Cao 0001	Optimizing finfet technology for high-speed and low-power design.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	power, energy, variations, speed, threshold voltage, FinFET, noise margin
68	Robert Bai, Nam Sung Kim, Dennis Sylvester, Trevor N. Mudge	Total leakage optimization strategies for multi-level caches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, cache memory, gate leakage
63	Xiaoyong Tang, Hai Zhou 0001, Prithviraj Banerjee	Leakage power optimization with dual-Vth library in high-level synthesis.	DAC	2005	DBLP DOI BibTeX RDF	dual-Vth, optimization, high-level synthesis, leakage power
62	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
62	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.	DAC	2004	DBLP DOI BibTeX RDF	optimization, power dissipation, multiple voltages
62	E. Seebacher, Gerhard Rappitsch, H. Höller	Process Characterization for Low VTH and Low Power Design.	PATMOS	2003	DBLP DOI BibTeX RDF
62	Kaushik Roy 0001, Liqiong Wei, Zhanping Chen	Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
55	Min Ni, Seda Ogrenci Memik	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dual-Vth, leakage power optimization, gate sizing, clock skew scheduling
54	Hamed F. Dadgour, Vivek De, Kaustav Banerjee	Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design.	ICCAD	2008	DBLP DOI BibTeX RDF
54	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Leakage power reduction using stress-enhanced layouts.	DAC	2008	DBLP DOI BibTeX RDF	performance, mobility, layout, leakage, stress
54	Armin Wellig, Julien Zory	Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology.	PATMOS	2005	DBLP DOI BibTeX RDF
54	Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma	A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology.	ISQED	2005	DBLP DOI BibTeX RDF
54	David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization.	ISLPED	2003	DBLP DOI BibTeX RDF	dual threshold, sizing, dual supply voltage, simultaneous
54	Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa	Automated selective multi-threshold design for ultra-low standby applications.	ISLPED	2002	DBLP DOI BibTeX RDF	standby leakage current, automated design, multi-threshold
54	Vjekoslav Svilan, Masataka Matsui, James B. Burr	Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS.	ISLPED	2000	DBLP DOI BibTeX RDF
48	Frank Sill, Frank Grassert, Dirk Timmermann	Low power gate-level design with mixed-Vth (MVT) techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
48	Chris H. Kim, Kaushik Roy 0001	Dynamic VTH Scaling Scheme for Active Leakage Power Reduction.	DATE	2002	DBLP DOI BibTeX RDF
42	Bohan Lu, Miao Cui, Wen Liu	The Impact of AlGaN Barrier on Transient VTH Shifts and VTH Hysteresis in Depletion and Enhancement mode AlGaN/GaN MIS-HEMTs.	ICICDT	2019	DBLP DOI BibTeX RDF
41	Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen 0024, Yu Cao 0001, Lawrence T. Clark	In-situ characterization and extraction of SRAM variability.	DAC	2010	DBLP DOI BibTeX RDF	SRAM test, data retention voltage, threshold voltage variation, write margin, extraction
41	Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw	STEEL: a technique for stress-enhanced standard cell library design.	ICCAD	2008	DBLP DOI BibTeX RDF
41	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
41	Christian Piguet, Christian Schuster, Jean-Luc Nagel	Static and Dynamic Power Reduction by Architecture Selection.	PATMOS	2006	DBLP DOI BibTeX RDF
41	Chanseok Hwang, Chang Woo Kang, Massoud Pedram	Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.	ISQED	2006	DBLP DOI BibTeX RDF
41	Yen-Te Ho, TingTing Hwang	Low power design using dual threshold voltage.	ASP-DAC	2004	DBLP DOI BibTeX RDF
41	Imad A. Ferzli, Farid N. Najm	Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.	DAC	2003	DBLP DOI BibTeX RDF	statistical analysis, leakage current, power grid, voltage drop
35	Hui Shao, Chi-Ying Tsui	Low energy level converter design for sub-Vth logics.	ASP-DAC	2009	DBLP DOI BibTeX RDF
35	Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram	Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.	DSD	2008	DBLP DOI BibTeX RDF
35	Sherif A. Tawfik, Volkan Kursun	Multi-Vth Level Conversion Circuits for Multi-VDD Systems.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Mongkol Ekpanyapong, Sung Kyu Lim	Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.	ISPD	2006	DBLP DOI BibTeX RDF	supply and threshold voltage scaling, low power design, retiming
35	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.	DATE	2004	DBLP DOI BibTeX RDF
28	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
27	Basab Datta, Wayne P. Burleson	Temperature effects on energy optimization in sub-threshold circuit design.	ISQED	2009	DBLP DOI BibTeX RDF
27	Amir Khatib Zadeh, Catherine H. Gebotys	Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC).	ISQED	2009	DBLP DOI BibTeX RDF
27	Yun Ye, Frank Liu 0001, Min Chen 0024, Yu Cao 0001	Variability analysis under layout pattern-dependent rapid-thermal annealing process.	DAC	2009	DBLP DOI BibTeX RDF	dopant activation, layout pattern, rapid-thermal annealing, threshold voltage variation, physical design
27	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa	Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
27	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Failure analysis for ultra low power nano-CMOS SRAM under process variations.	SoCC	2008	DBLP DOI BibTeX RDF
27	Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura	Simultaneous optimization of memory configuration and code allocation for low power embedded systems.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	code allocation, low power design, on-chip memory
27	Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim	Yield-driven near-threshold SRAM design.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Rodrigo Jaramillo-Ramirez, Mohab Anis	A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Lih-Yih Chiou, Shien-Chun Luo	An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Frank Sill, Jiaxi You, Dirk Timmermann	Design of mixed gates for leakage reduction.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	mixed gates, leakage current, threshold voltage, gate leakage
27	Yuanlin Lu, Vishwani D. Agrawal	Statistical Leakage and Timing Optimization for Submicron Process Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
27	B. Chung, J. B. Kuo	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
27	M. Emadi, Amir Jafargholi, M. H. Sargazi Moghadam, Mohammad Mahdi Nayebi	Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen	Engery-Efficient Double-Edge Triggered Flip-Flop Design.	APCCAS	2006	DBLP DOI BibTeX RDF
27	Visvesh S. Sathe 0001, Marios C. Papaefthymiou, Conrad H. Ziesler	A GHz-class charge recovery logic.	ISLPED	2005	DBLP DOI BibTeX RDF	resonant systems, energy recovery, adiabatic
27	Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal	On the Advantages of Serial Architectures for Low-Power Reliable Computations.	ASAP	2005	DBLP DOI BibTeX RDF
27	Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger	Sleepy Stack Reduction of Leakage Power.	PATMOS	2004	DBLP DOI BibTeX RDF
27	Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee	Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era.	DAC	2004	DBLP DOI BibTeX RDF	electrothermal couplings, temperature aware design, subthreshold leakage, energy delay product
27	Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong	An MTCMOS design methodology and its application to mobile computing.	ISLPED	2003	DBLP DOI BibTeX RDF	CPFF, low power, leakage current, CCS, MTCMOS
27	Hyunsik Im	Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model).	ISLPED	2002	DBLP DOI BibTeX RDF	?-power model, MOSFET modeling, Saturation current
27	Koichi Nose, Soo-Ik Chae, Takayasu Sakurai	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	gate capacitance, low supply voltage, low-power design
27	Mircea R. Stan	Optimal Voltages and Sizing for Low Power.	VLSI Design	1999	DBLP DOI BibTeX RDF
21	Yong-Hwa Wen, Tz-Wun Wang, Tzu-Hsien Yang, Sheng-Hsi Hung, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai	A -10 to -20-V Inverting Buck-Boost Drive GaN Driver With Sub-1-μA Leakage Current Vth Tracking Technique for 20-MHz Depletion-Mode GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
21	Bo Yi, Yi Xu, LiTian Zheng, Junji Cheng, Haimeng Huang, MouFu Kong, Hongqiang Yang	Modeling and simulation of an insulated-gate HEMT using p-SnO2 gate for high VTH design.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
21	Marcello Cioni, G. Giorgino, Alessandro Chini, Carmine Miccoli, Maria Eloisa Castagna, M. Moschetti, C. Tringali, Ferdinando Iucolano	Evidence of Carbon Doping Effect on VTH Drift and Dynamic-RON of 100V p-GaN Gate AlGaN/GaN HEMTs.	IRPS	2023	DBLP DOI BibTeX RDF
21	Yuye Kang, Kaizhen Han, Yue Chen, Xiao Gong	Thickness-Engineered Extremely-thin Channel High Performance ITO TFTs with Raised S/D Architecture: Record-Low RSD, Highest Moblity (Sub-4 nm TCH Regime), and High VTH Tunability.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
21	Sonu Hooda, Chun-Kuei Chen, Manohar Lal, Shih-Hao Tsai, Evgeny Zamburg, Aaron Voon-Yew Thean	Overcoming Negative nFET VTH by Defect-Compensated Low-Thermal Budget ITO-IGZO Hetero-Oxide Channel to Achieve Record Mobility and Enhancement-mode Operation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
21	Xianzhou Shao, Junshuai Chai, Min Liao, Jiahui Duan, Fengbin Tian, Xiaoyu Ke, Xiaoqing Sun, Hao Xu, Jinjuan Xiang, Xiaolei Wang, Wenwu Wang 0006	Comprehensive Study of Endurance Fatigue in the Scaled Si FeFET by in-situ Vth Measurement and Endurance Enhancement Strategy.	IMW	2023	DBLP DOI BibTeX RDF
21	Mohith Amara, Indranil Bhattacharjee, Gajendranath Chowdary	A 19 pJ-K2 Temperature Sensor using Sub-VTH Ring Oscillator with 1.28°C/V Line Sensitivity.	ISCAS	2023	DBLP DOI BibTeX RDF
21	Pablo A. Petrashin, Walter J. Lancioni, Agustin Laprovitta, Fortunato Dualibe, Juan Luis Castagnola	Effect of Vth shifting in CMOS Transistors under radiation conditions when applying OBT: A case study.	LATS	2023	DBLP DOI BibTeX RDF
21	Shun'ichiro Ohmi, Masakazu Tanuma, Joong-Won Shin	Precise VTH Control of MFSFET with 5 nm-thick FeND-HfO2 Realized by Kr-Plasma Sputtering for Pt Gate Electrode Deposition.	DRC	2023	DBLP DOI BibTeX RDF
21	P. C. Chang, P. J. Liao, D. W. Heh, C. Lee, D. H. Hou, Elia Ambrosi, C. H. Wu, H. Y. Lee, J. H. Lee, Xinyu Bao	Investigation of First Fire Effect on VTH Stability and Endurance in GeCTe Selector.	IRPS	2022	DBLP DOI BibTeX RDF
21	Fabrizio Masin, Carlo De Santi, Arno Stockman, J. Lettens, F. Geenen, Gaudenzio Meneghesso, Enrico Zanoni, Peter Moens, Matteo Meneghini	Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs at Room and Cryogenic-Temperature.	IRPS	2022	DBLP DOI BibTeX RDF
21	Marcello Cioni, Patrick Fiorenza, Fabrizio Roccaforte, Mario Saggio, S. Cascino, Angelo Alberto Messina, Vincenzo Vinciguerra, Michele Calabretta, Alessandro Chini	Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs.	IRPS	2022	DBLP DOI BibTeX RDF
21	Camille Leurquin, William Vandendaele, Aby-Gaël Viey, Romain Gwoziecki, René Escoffier, R. Salot, G. Despesse, Ferdinando Iucolano, Roberto Modica, A. Constant	Novel High Voltage Bias Temperature Instabilities (HV-BTI) setup to monitor RON/VTH drift on GaN-on-Si E-mode MOSc-HEMTs under drain voltage.	IRPS	2022	DBLP DOI BibTeX RDF
21	Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi	High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Kailiang Huang, Xinlv Duan, Junxiao Feng, Ying Sun, Congyan Lu, Chuanke Chen, Guangfan Jiao, Xinpeng Lin, Jinhai Shao, Shihui Yin, Jiazhen Sheng, Zhaogui Wang, Wenqiang Zhang, Xichen Chuai, Jiebin Niu, Wenwu Wang 0006, Ying Wu, Weiliang Jing, Zhengbo Wang, Jeffrey Xu, Guanhua Yang, Di Geng, Ling Li, Ming Liu	Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Muhammad Abrar Akram, Sohmyung Ha	A 433.92-MHz CMOS Rectifier with Dynamic VTH-reduction for Wireless Biomedical Implants.	BioCAS	2022	DBLP DOI BibTeX RDF
21	Liron Lisha, Ori Bass, Joseph Shor	A 5800 μm² Process Monitor Circuit for Measurement of in-Die Variation of Vth in 65nm.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
21	Marcello Cioni, Alessandro Bertacchini, Alessandro Mucci, Giovanni Verzellesi, Paolo Pavan, Alessandro Chini	Investigation on VTH and RON Slow/Fast Drifts in SiC MOSFETs.	IRPS	2021	DBLP DOI BibTeX RDF
21	Anuradha Chathuranga Ranasinghe, Sabih H. Gerez	Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration.	ICCD	2021	DBLP DOI BibTeX RDF
21	Mengyuan Hua, Junting Chen, Chengcai Wang, Lingling Li, Ling Liu, Zheyang Zheng, Kevin J. Chen	E-mode p-FET-bridge HEMT: Toward high VTH, low reverse-conduction loss and enhanced stability.	ASICON	2021	DBLP DOI BibTeX RDF
21	Munir Ahmad Al-Absi, Sami R. Al-Batati	Hybrid Internal Vth Cancellation Rectifiers for RF Energy Harvesting.	IEEE Access	2020	DBLP DOI BibTeX RDF
21	Bumjin Park, Youngwoo Ji, Jae-Yoon Sim	A 490-pW SAR Temperature Sensor With a Leakage-Based Bandgap-Vth Reference.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
21	Ren Usami, Takao Komiyama, Yasunori Chonan, Hiroyuki Yamaguchi, Koji Kotani	Photovoltaic-assisted self-Vth-cancellation CMOS rectifier for synergistic RF energy harvesting.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
21	Nayoung Choi, Jaeha Kim	Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth Variations.	ICCAD	2020	DBLP DOI BibTeX RDF
21	Shuang Li, Zhichao Du, Yu Wang 0097, Fei Liu, Qi Wang 0041, Zongliang Huo	Adaptive Pulse Program Scheme to Improve the Vth Distribution for 3D NAND Flash.	ISCAS	2020	DBLP DOI BibTeX RDF
21	Anuradha Chathuranga Ranasinghe, Sabih H. Gerez	Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing.	ISCAS	2020	DBLP DOI BibTeX RDF
21	Syed Huzaif Ali, Enes Ugur, Bilal Akin	Analysis of Vth Variations in IGBTs Under Thermal Stress for Improved Condition Monitoring in Automotive Power Conversion Systems.	IEEE Trans. Veh. Technol.	2019	DBLP DOI BibTeX RDF
21	Kunliang Wang, Gang Du, Zhiyuan Lun, Wangyong Chen, Xiaoyan Liu	Modeling of program Vth distribution for 3-D TLC NAND flash memory.	Sci. China Inf. Sci.	2019	DBLP DOI BibTeX RDF
21	Besar Asllani, Alberto Castellazzi, Oriol Avino-Salvado, Asad Fayyaz, Hervé Morel, Dominique Planson	VTH-Hysteresis and Interface States Characterisation in SiC Power MOSFETs with Planar and Trench Gate.	IRPS	2019	DBLP DOI BibTeX RDF
21	Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim	A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect.	ISSCC	2019	DBLP DOI BibTeX RDF
21	Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi	Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2-D and 3-D-TLC NAND Flash Memories.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
21	Besar Asllani, Asad Fayyaz, Alberto Castellazzi, Hervé Morel, Dominique Planson	VTH subthreshold hysteresis technology and temperature dependence in commercial 4H-SiC MOSFETs.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
21	Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen	Reliability-Aware Multi-Vth Domain Digital Design Assessment.	DDECS	2018	DBLP DOI BibTeX RDF
21	Miroslav Potocný, Viera Stopjaková, Martin Kovác	Self Vth-Compensating CMOS On-Chip Rectifier for Inductively Powered Implantable Medical Devices.	DDECS	2018	DBLP DOI BibTeX RDF
21	Ren Usami, Takao Komiyama, Yasunori Chonan, Hiroyuki Yamaguchi, Koji Kotani	Photovoltaic-Assisted Self-Vth-Cancellation CMOS RF Rectifier for Wide Power Range Operation.	A-SSCC	2018	DBLP DOI BibTeX RDF
21	Jing Wang, Li Ding, Qiang Li, Hirofumi Shinohara, Yasuaki Inoue	Accurate Nanopower Supply-Insensitive CMOS Unit Vth Extractor and αVth Extractor with Continuous Variety.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF