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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1030 occurrences of 542 keywords
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Results
Found 1492 publication records. Showing 1492 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
134 | Yoav Ossia, Ori Ben-Yitzhak, Marc Segal |
Mostly concurrent compaction for mark-sweep GC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 4th International Symposium on Memory Management, ISMM 2004, Vancouver, BC, Canada, October 24-25, 2004, pp. 25-36, 2004, ACM, 1-58113-945-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
concurrent compaction, incremental compaction, Java, garbage collection, JVM, compaction |
115 | Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. Shaheen |
Improving utilization of reconfigurable resources using two-dimensional compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 42(2), pp. 235-250, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Pre-emptive tasks, Online placement, Compaction, Partial reconfiguration, Resources utilization |
101 | Ahmed A. El Farag, Hatem M. El-Boghdadi, Samir I. Shaheen |
Improving utilization of reconfigurable resources using two dimensional compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 135-140, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
101 | Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy |
Static test sequence compaction based on segment reordering and accelerated vector restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 954-961, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
94 | Diab Abuaiadh, Yoav Ossia, Erez Petrank, Uri Silbershtein |
An efficient parallel heap compaction algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA ![In: Proceedings of the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2004, October 24-28, 2004, Vancouver, BC, Canada, pp. 224-236, 2004, ACM, 1-58113-831-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
parallel compaction, java, garbage collection, JVM, compaction, parallel garbage collection |
93 | Krishnendu Chakrabarty |
Zero-aliasing space compaction using linear compactors with bounded overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5), pp. 452-457, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
89 | Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara |
Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 192-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Time expansion model, acyclic sequential circuit, reverse transformation fault simulation, template, Test sequence compaction |
85 | Slawomir Pilarski, Kevin James Wiebe |
Counter-based compaction: An analysis for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(1), pp. 33-43, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
compaction by counter, edge counting, one's counting, transition counting, built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, test response compaction |
80 | Michael S. Hsiao, Srimat T. Chakradhar |
Test Set Compaction Using Relaxed Subsequence Removal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 319-327, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
static test set compaction, support sets, recurrence subsequence, ATPG |
80 | Michael S. Hsiao, Srimat T. Chakradhar |
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 329-338, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
static test set compaction, vector-reordering, fault coverage curve, partitioning, ATPG |
77 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 54-59, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects |
75 | Narayan Vikas |
Computational Complexity Classification of Partition under Compaction and Retraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, 10th Annual International Conference, COCOON 2004, Jeju Island, Korea, August 17-20, 2004, Proceedings, pp. 380-391, 2004, Springer, 3-540-22856-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
75 | Irith Pomeranz, Sudhakar M. Reddy |
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 61-66, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
75 | Zhenyu Li, Victor Milenkovic |
A Compaction Algorithm for Non-Convex Polygons and Its Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCG ![In: Proceedings of the Ninth Annual Symposium on Computational GeometrySan Diego, CA, USA, May 19-21, 1993, pp. 153-162, 1993, ACM, 0-89791-582-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
72 | Nian-Feng Tzeng, Hsing-Lung Chen |
Fast Compaction in Hypercubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 9(1), pp. 50-56, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hypercubes, fragmentation, Compaction, disjoint paths, task migration, subcubes |
72 | Michael S. Hsiao, Srimat T. Chakradhar |
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 577-582, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
test set compaction, state relaxation, recurrence subsequence removal, sequential circuit |
68 | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
Compaction-based test generation using state and fault information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 159-164, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
compaction-based test generation, newly-traversed state information, newly-detected fault information, vector compaction iterations, vector sequence bias, biased vectors, compacted test set extension, intelligent vector selection, state analysis, fault diagnosis, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, iterative methods, vectors, fault coverage, circuit analysis computing, fault analysis, benchmark circuits, computing resources, vector generation |
68 | Markus Seuring, Krishnendu Chakrabarty |
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 213-220, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
non-modeled faults, one-step compaction, two-step compaction, error detection, transparency, Aliasing |
67 | Sverre Wichlund, Frank Berntsen, Einar J. Aas |
Scan Test Response Compaction Combined with Diagnosis Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 235-246, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE |
67 | Bjorn De Sutter, Bruno De Bus, Koenraad De Bosschere, Saumya K. Debray |
Combining Global Code and Data Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 29-38, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
67 | Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy |
On Improving Static Test Compaction for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 111-116, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
67 | Gunnar W. Klau, Petra Mutzel |
Optimal Compaction of Orthogonal Grid Drawings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCO ![In: Integer Programming and Combinatorial Optimization, 7th International IPCO Conference, Graz, Austria, June 9-11, 1999, Proceedings, pp. 304-319, 1999, Springer, 3-540-66019-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Irith Pomeranz, Sudhakar M. Reddy |
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 250-255, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Krishnendu Chakrabarty, John P. Hayes |
Test response compaction using multiplexed parity trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11), pp. 1399-1408, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
67 | David G. Boyer |
Symbolic Layout Compaction Review. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 383-389, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
63 | Aiman H. El-Maleh, Yahya E. Osais |
Test vector decomposition-based static compaction algorithms for combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 430-459, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Static compaction, class-based clustering, independent fault clustering, test vector decomposition, taxonomy, combinational circuits |
63 | Wen-Ke Chen, Bengu Li, Rajiv Gupta 0001 |
Code Compaction of Matching Single-Entry Multiple-Exit Regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 10th International Symposium, SAS 2003, San Diego, CA, USA, June 11-13, 2003, Proceedings, pp. 401-417, 2003, Springer, 3-540-40325-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
single-entry-multiple-exit regions, control flow signature, Code compaction, predicated execution |
63 | Paulo F. Flores, Horácio C. Neto, João P. Marques Silva |
On Applying Set Covering Models to Test Set Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 8-11, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Test Set Compaction, Unate Covering Problem, Test Pattern Generation, Set Covering |
63 | Anand Raghunathan, Srimat T. Chakradhar |
Acceleration techniques for dynamic vector compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 310-317, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Dynamic equivalent and untestable fault analysis, Target fault switching, Support sets, Test compaction, Acceleration Techniques |
59 | Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba |
Static Compaction Techniques to Control Scan Vector Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 35-42, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Static Compaction, Test Vector Compaction, Heat Minimization, Low Power, Built-In Self-Test, Design-for-Testability, Integrated Circuits, switching activity, Scan Chains, Peak power, Embedded Cores, Digital Testing |
58 | Irith Pomeranz, Sudhakar M. Reddy |
Vector-restoration-based static compaction using random initial omission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11), pp. 1587-1592, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
58 | Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz |
Reverse-order-restoration-based static test compaction for synchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), pp. 293-304, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
58 | Ori Ben-Yitzhak, Irit Goft, Elliot K. Kolodner, Kean Kuiper, Victor Leikehman |
An algorithm for parallel incremental compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSP/ISMM ![In: Proceedings of The Workshop on Memory Systems Performance (MSP 2002), June 16, 2002 and The International Symposium on Memory Management (ISMM 2002), June 20-21, 2002, Berlin, Germany, pp. 207-212, 2002, ACM, 1-58113-539-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
58 | Kwame Osei Boateng, Hideaki Konishi, Tsuneo Nakata |
A Method of Static Compaction of Test Stimuli. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 137-144, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
58 | Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos |
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 350-355, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
58 | Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy |
Resource-Constrained Compaction of Sequential Circuit Test Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 398-405, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
58 | Michael S. Hsiao, Srimat T. Chakradhar |
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 452-457, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
58 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(1), pp. 112-122, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
58 | Srimat T. Chakradhar, Anand Raghunathan |
Bottleneck removal algorithm for dynamic compaction in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1157-1172, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
58 | Kurt Mehlhorn, Wolfgang Rülling |
Compaction on the torus [VLSI layout]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4), pp. 389-397, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
58 | Mark Harris |
Extending microcode compaction for real architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987, Colorado Springs, Colorado, USA, December 1-4, 1987, pp. 40-53, 1987, ACM/IEEE, 0-89791-250-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
58 | Y. Eric Cho |
A subjective review of compaction (tutorial session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 396-404, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
55 | Huaxing Tang, Chen Wang 0014, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz |
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 59-64, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja |
DX-compactor: distributed X-compaction for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 505-510, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dx-compactor, hierarchical compactor, x-compactor, SoC, compaction |
54 | Michal Wegiel, Chandra Krintz |
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 91-102, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
parallel, concurrent, virtual memory, compaction |
54 | Haim Kermany, Erez Petrank |
The Compressor: concurrent, incremental, and parallel compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada, June 11-14, 2006, pp. 354-363, 2006, ACM, 1-59593-320-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
garbage collection, memory management, compaction, runtime systems, concurrent garbage collection |
54 | Yinhe Han 0001, Xiaowei Li 0001, Huawei Li 0001, Anshuman Chandra |
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 201-209, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test resource partitioning (TRP), error cancellation, System-on-a-Chip (SoC), diagnose, response compaction |
54 | Irith Pomeranz, Sudhakar M. Reddy |
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(12), pp. 1569-1581, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Scan circuits, test application time, static test compaction |
54 | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
State and Fault Information for Compaction-Based Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(1), pp. 63-72, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
sequential circuits, ATPG, test compaction |
54 | Sandeep Bhatia, Prab Varma |
Test Compaction in a Parallel Access Scan Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 300-305, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Test Vector Compaction, Design for Testability, Scan |
54 | Wen-Ben Jone, Anita Gleason |
Analysis of Hamming count compaction scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(4), pp. 373-384, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
index vector, spectral coefficients, Built-in self test, compaction, syndrome |
52 | Jin Ding, David Moloney, Xiaojun Wang 0001 |
Aliasing-Free Space and Time Compactions with Limited Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 355-360, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
51 | Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita |
Test sequence compaction for sequential circuits with reset states. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 165-170, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction |
51 | Irith Pomeranz, Sudhakar M. Reddy |
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 216-221, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
dynamic test compaction, synchronous sequential circuits, static test compaction |
51 | Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak |
An improved output compaction technique for built-in self-test in VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 403-407, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
output compaction technique, space compression technique, compaction tree generation, detectable error probability, Boolean difference method, syndrome counter, VLSI, logic testing, probability, built-in self test, built-in self-test, Boolean functions, integrated circuit testing, design for testability, BIST, combinational circuits, combinational circuits, automatic testing, DFT, fault coverage, integrated logic circuits, digital circuits, VLSI circuits, digital integrated circuits |
49 | Bo Cui 0002, DengHua Zhong, Ping Zhang 0006, Lei Liu |
The Application of Computer Graphic Technology on Monitoring Roller Compaction Quality of Rock-fill Dam. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGIV ![In: Sixth International Conference on Computer Graphics, Imaging and Visualization: New Advances and Trends, CGIV 2009, 11-14 August 2009, Tianjin, China, pp. 520-524, 2009, IEEE Computer Society, 978-0-7695-3789-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
49 | Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic |
Synonymous address compaction for energy reduction in data TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 357-362, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low-power TLB, spatial and temporal locality, multi-porting |
49 | Puqing Chen, Kejing He, Zhaoyao Zhou, Yuanyuan Li |
The Research on MPC-WS, a Web Service for the Simulation of Metal Powder Compaction Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing - GCC 2005, 4th International Conference, Beijing, China, November 30 - December 3, 2005, Proceedings, pp. 232-237, 2005, Springer, 3-540-30510-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Irith Pomeranz, Sudhakar M. Reddy |
Vector replacement to improve static-test compaction forsynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2), pp. 336-342, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
49 | Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo |
Static test compaction for synchronous sequential circuits based on vector restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7), pp. 1040-1049, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | Ioan Tabus, Corneliu Popeea, Jaakko Astola |
Optimizing the compaction gain in a class of IIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 528-531, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | Youssef Saab |
An improved linear placement algorithm using node compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8), pp. 952-958, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Roberto Bevacqua, Luca Guerrazzi, Fabrizio Ferrandi, Franco Fummi |
Implicit Test Sequences Compaction for Decreasing Test Application Cos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 384-382, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
49 | Jau-Shien Chang, Chen-Shang Lin |
Test set compaction for combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11), pp. 1370-1378, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
49 | Prabhakar Radge |
The Parallel Simplicity of Compaction and Chaining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 17th International Colloquium, ICALP90, Warwick University, England, UK, July 16-20, 1990, Proceedings, pp. 744-751, 1990, Springer, 3-540-52826-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
49 | Shao-Jun Wei, Jacques Leroy, Raymond Crappe |
An efficient two-dimensional compaction algorithm for VLSI symbolic layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 196-200, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
49 | Bogong Su, Jian Wang 0046, Jinshi Xia |
Global microcode compaction under timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 116-118, 1988, ACM/IEEE, 0-8186-1919-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
49 | M. Al-Suwaiyel, Ellis Horowitz |
Algorithms for Trie Compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Database Syst. ![In: ACM Trans. Database Syst. 9(2), pp. 243-263, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
|
49 | Zinaida V. Apanovich, Alexander G. Marchuk |
Top-Down Approach to Technology Migration for Full-Custom Mask Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 48-52, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Technology migration, decomposition, compaction, rerouting |
46 | Markus Billeter, Ola Olsson, Ulf Assarsson |
Efficient stream compaction on wide SIMD many-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
High Performance Graphics ![In: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on High Performance Graphics 2009, New Orleans, Louisiana, USA, August 1-3, 2009, pp. 159-166, 2009, Eurographics Association, 978-1-60558-603-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
stream compaction, GPGPU, CUDA, parallel sorting, prefix sum |
46 | Yinhe Han 0001, Huawei Li 0001, Xiaowei Li 0001, Anshuman Chandra |
Response compaction for system-on-a-chip based on advanced convolutional codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 49(2), pp. 262-272, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
X bits masking, aliasing, convolutional code, SOC test, response compaction |
46 | Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta 0001, Melvin A. Breuer |
STAX: statistical crosstalk target set compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 172-177, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
compaction degree, fault-producing target, pruning power, safe target, statistical static timing analyzer, ATPG |
46 | Dominique Chanet, Bjorn De Sutter, Bruno De Bus, Ludo Van Put, Koen De Bosschere |
System-wide compaction and specialization of the linux kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005, pp. 95-104, 2005, ACM, 1-59593-018-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
operating system, compaction, specialization, system calls, linux kernel |
46 | Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
Path delay test compaction with process variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 845-850, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process variation, delay testing, path delay fault, test compaction |
46 | Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel |
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(12), pp. 1646-1651, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Space compaction, testing, stuck-at faults, system-on-a-chip |
46 | Irith Pomeranz, Sudhakar M. Reddy |
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(7), pp. 866-872, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
synchronous sequential circuits, Static test compaction |
46 | Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy |
A Method of Static Test Compaction Based on Don't Care Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 392-395, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Coloring Problem, Don't Care Identification, ATPG, Static Test Compaction |
46 | Saumya K. Debray, William S. Evans, Robert Muth, Bjorn De Sutter |
Compiler techniques for code compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 22(2), pp. 378-415, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
code compression, code size reduction, code compaction |
46 | Irith Pomeranz, Sudhakar M. Reddy |
Test-Point Insertion to Enhance Test Compaction for Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 375-381, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Scan design, test-point insertion, static test compaction |
46 | Toshiyuki Maeda, Kozo Kinoshita |
Memory reduction of IDDQ test compaction for internal and external bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 350-355, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction |
46 | Irith Pomeranz, Sudhakar M. Reddy |
On Test Compaction Objectives for Combinational and Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 279-284, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements |
46 | Irith Pomeranz, Sudhakar M. Reddy |
On the Compaction of Test Sets Produced by Genetic Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 4-9, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
test generation, test compaction, genetic optimization, n-detection test sets |
46 | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
On the effects of test compaction on defect coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 430-437, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
surrogate faults, fault diagnosis, test generation, integrated circuit testing, fault modeling, test sets, test compaction, defect coverage |
46 | Irith Pomeranz, Sudhakar M. Reddy |
Static compaction for two-pattern test sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 222-228, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults |
46 | Paolo Ienne |
Horizontal Microcode Compaction for Programmable Systolic Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 85-, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Horizontal Microcode, Microcode Compaction, Programmable Systolic Arrays, Neural Networks |
46 | Toshio Nakatani, Kemal Ebcioglu |
Making Compaction-Based Parallelization Affordable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(9), pp. 1014-1029, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc |
45 | Irith Pomeranz, Sudhakar M. Reddy |
Reducing test application time for full scan circuits by the addition of transfer sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 317-322, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
transfer sequences, primary input vectors, scan-in operation, scan-out operation, static compaction procedure, compaction levels, fault diagnosis, logic testing, design for testability, fault detection, automatic testing, boundary scan testing, test set, test application time, full scan circuits |
43 | Qianying Tang, Jianwen Zhu |
Two-Dimensional Layout Migration by Soft Constraint Satisfaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 35-39, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Faith E. Fich, Miroslaw Kowaluk, Krzysztof Lorys, Miroslaw Kutylowski, Prabhakar Ragde |
Retrieval of scattered information by EREW, CREW and CRCW PRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SWAT ![In: Algorithm Theory - SWAT '92, Third Scandinavian Workshop on Algorithm Theory, Helsinki, Finland, July 8-10, 1992, Proceedings, pp. 30-41, 1992, Springer, 3-540-55706-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
43 | David Marple |
A Hierarchy Preserving Hierarchical Compactor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 375-381, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
43 | Jingsheng Cong, D. F. Wong 0001 |
How to Obtain More Compactable Channel Routing Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 663-666, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
41 | Po-Han Wu, Tsung-Tang Chen, Wei-Lin Li, Jiann-Chyi Rau |
An efficient test-data compaction for low power VLSI testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 237-241, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 776-781, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Chunsheng Liu, Yu Huang 0005 |
Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 461-468, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Andre Tkacenko, P. P. Vaidyanathan |
On the spectral factor ambiguity of FIR energy compaction filter Banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 54(1), pp. 380-385, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Irith Pomeranz, Sudhakar M. Reddy |
Test compaction for transition faults under transparent-scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1264-1269, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Jing Wang 0006, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker |
Static Compaction of Delay Tests Considering Power Supply Noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 235-240, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Ozgur Sinanoglu, Alex Orailoglu |
Compaction Schemes with Minimum Test Application Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 199-204, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Youcef Bourai, C.-J. Richard Shi |
Layout Compaction for Yield Optimization via Critical Area Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 122-125, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Rei Oguro, Kazuhiko Ozeki, Kazuyuki Takagi, Yujie Zhang |
An Efficient Algorithm for Japanese Sentence Compaction Based on Phrase Importance and Inter-Phrase Dependency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TSD ![In: Text, Speech and Dialogue - Third International Workshop, TSD 2000, Brno, Czech Republic, September 13-16, 2000, Proceedings, pp. 103-108, 2000, Springer, 3-540-41042-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
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