Search results for "latches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
98	Chen-Hsuan Lin, Chun-Yao Wang	Dependent latch identification in the reachable state space.	ASP-DAC	2009	DBLP DOI BibTeX RDF
66	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
66	Maryam Shojaei Baghini, Madhav P. Desai	Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	CMOS latches, Technology Scaling, Metastability
65	Sandeep Bhatia, Niraj K. Jha	Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
65	V. Seth, Min Zhao 0001, Jiang Hu	Exploiting level sensitive latches in wire pipelining.	ICCAD	2004	DBLP DOI BibTeX RDF
55	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
55	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
54	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-latch aware placement for timing-integrity optimization.	DAC	2010	DBLP DOI BibTeX RDF	pulsed latch, placement, physical design
54	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Reducing reorder buffer complexity through selective operand caching.	ISLPED	2003	DBLP DOI BibTeX RDF	low-complexity datapath, short-lived values, low-power design, reorder buffer
54	Sorin Cotofana, Stamatis Vassiliadis	delta-Bit serial binary addition with linear threshold networks.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
54	Yibo Chen, Yuan Xie 0001	Tolerating process variations in high-level synthesis using transparent latches.	ASP-DAC	2009	DBLP DOI BibTeX RDF
54	Victor V. Zyuban	Optimization of scannable latches for low energy.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
54	Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung	Low-power high-level synthesis using latches.	ASP-DAC	2001	DBLP DOI BibTeX RDF
44	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
44	David A. Kearney, Neil W. Bergmann	Performance evaluation of asynchronous logic pipelines with data dependent processing delays.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous logic pipelines, data dependent processing delays, logic stages, data dependent delay, two valued random variable, performance evaluation, performance evaluation, asynchronous circuits, pipeline processing, latches
44	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
43	Chuan Lin 0002, Hai Zhou 0001	Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
43	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A micropower low-voltage multiplier with reduced spurious switching.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
43	Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi	ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
43	Li-Hsun Chen, Oscal T.-C. Chen	A low-complexity and high-speed Booth-algorithm FIR architecture.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
43	Rajeev K. Ranjan 0001, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton	Using Combinational Verification for Sequential Circuits.	DATE	1999	DBLP DOI BibTeX RDF
43	Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac	Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
43	Mahmoud Lotfi Anhar, Mohammad Ali Jabraeil Jamali	The Optimum Location of Delay Latches Between Dynamic Pipeline Stages.	APPT	2007	DBLP DOI BibTeX RDF	Minimum, MAL, Pipeline, Latency, Collision, Table, Reservation, Latch, Average
43	Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein	Self-Resetting Latches for Asynchronous Micro-Pipelines.	DAC	2007	DBLP DOI BibTeX RDF
43	Eslam Yahya, Marc Renaudin	QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
43	Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura 0002, Shigeto Inui, Takeshi Yoshimura	Timing optimization by replacing flip-flops to latches.	ASP-DAC	2004	DBLP DOI BibTeX RDF
43	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail	Modeling unbuffered latches for timing analysis.	ICCAD	2004	DBLP DOI BibTeX RDF
43	Soha Hassoun	Optimal use of 2-phase transparent latches in buffered maze routing.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
43	Antonio Zenteno, Víctor H. Champac	Resistive Opens in a Class of CMOS Latches: Analysis and DFT.	VTS	2001	DBLP DOI BibTeX RDF
43	Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy	Built In Self Test for Ring Addressed FIFOs with Transparent Latches.	MTDT	1999	DBLP DOI BibTeX RDF	Built In Self Test, Memory testing, Embedded memories
43	Jin-Fuw Lee, Donald T. Tang, Chak-Kuen Wong	A timing analysis algorithm for circuits with level-sensitive latches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
43	Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge	Critical paths in circuits with level-sensitive latches.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
43	Timothy M. Burks, Karem A. Sakallah	Optimization of critical paths in circuits with level-sensitive latches.	ICCAD	1994	DBLP DOI BibTeX RDF
43	Jin-Fuw Lee, Donald T. Tang, C. K. Wong	A timing analysis algorithm for circuits with level-sensitive latches.	ICCAD	1994	DBLP DOI BibTeX RDF
33	Malay K. Ganai, Aarti Gupta	Efficient BMC for Multi-Clock Systems with Clocked Specifications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
33	Il-soo Lee, Tony Ambler	Two efficient methods to reduce power and testing time.	ISLPED	2005	DBLP DOI BibTeX RDF	reordering scan latches, scan architecture, power, testing time
33	I. Thoidis, Dimitrios Soudris, Ioannis Karafyllidis, Adonios Thanailakis, Thanos Stouraitis	Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	voltage-mode latches, voltage-mode master-slave, true-single phase clocked-logic, Multiple-Valued Logic
33	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
33	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
33	José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
33	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Functional clock schedule optimization.	VLSI Design	1995	DBLP DOI BibTeX RDF	clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
33	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
33	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
33	Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
33	Michael Nicolaidis, Renaud Perez, Dan Alexandrescu	Low-Cost Highly-Robust Hardened Cells Using Blocking Feedback Transistors.	VTS	2008	DBLP DOI BibTeX RDF	radiation hardened cells, soft errors, SEUs
33	Sanjit A. Seshia, Wenchao Li 0001, Subhasish Mitra	Verification-guided soft error resilience.	DATE	2007	DBLP DOI BibTeX RDF
33	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
33	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.	DFT	2006	DBLP DOI BibTeX RDF
33	Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke	Word level predicate abstraction and refinement for verifying RTL verilog.	DAC	2005	DBLP DOI BibTeX RDF	SAT, predicate abstraction, verilog
33	Soonhak Kwon	A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
33	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
33	Gurhan Kucuk, Dmitry Ponomarev 0001, Kanad Ghose	Low-complexity reorder buffer architecture.	ICS	2002	DBLP DOI BibTeX RDF	low-complexity datapath, low-power design, reorder buffer
33	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
33	Nicola Nicolici, Bashir M. Al-Hashimi	Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.	DATE	2000	DBLP DOI BibTeX RDF
33	Naresh Maheshwari, Sachin S. Sapatnekar	Optimizing large multiphase level-clocked circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
33	Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah	Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
33	Hervé J. Touati, Robert K. Brayton	Computing the initial states of retimed circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
33	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Verification of Interacting Sequential Circuits.	DAC	1990	DBLP DOI BibTeX RDF
32	Sherif A. Tawfik, Volkan Kursun	Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
32	Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen	Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.	ASP-DAC	2006	DBLP DOI BibTeX RDF
32	Srivathsan Krishnamohan, Nihar R. Mahapatra	Analysis and design of soft-error hardened latches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple-upset, single-event, soft errors, single-event upset, latch, radiation hardening
32	Payam Heydari, Ravindran Mohanavelu	Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
32	Payam Heydari, Ravindran Mohanavelu	Design of ultra high-speed CMOS CML buffers and latches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
32	Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta 0001	A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.	PATMOS	2002	DBLP DOI BibTeX RDF
32	Prashant Saxena, Peichen Pan, C. L. Liu 0001	The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.	VLSI Design	1999	DBLP DOI BibTeX RDF
32	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	A unified approach in the analysis of latches and flip-flops for low-power systems.	ISLPED	1998	DBLP DOI BibTeX RDF	master-slave latch, optimization, timing, flip-flop, power measurement
32	Samy Makar, Edward J. McCluskey	ATPG for scan chain latches and flip-flops.	VTS	1997	DBLP DOI BibTeX RDF	bistable element, scan chain circuit, combinational defect detection, algorithm, ATPG, automatic test pattern generation, automatic testing, stuck-at fault, flip-flop, latch, checking experiment
32	Michel R. Dagenais, Nicholas C. Rumin	On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton	Sequential optimization in the absence of global reset.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Sequential logic synthesis, no-reset latches, safe replaceability
22	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF	dual edge, low power, flip-flops, clocking, triggered, latches
22	Peter Kornerup	A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	systolic linear-array multiplier, right-shift algorithms, multiplier cell, digit-product terms, least significant digit first, active elements, module-multiplier, Montgomery module-reduction, RSA encryption, modular division, cryptography, logic design, systolic arrays, systolic array, digital arithmetic, multiplying circuits, latches, modular inverses, Hensel codes, digit-serial multiplier
22	Jacob Savir, William H. McAnney	Random Pattern Testability of Delay Faults.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	combinational logic networks, logic testing, delay faults, combinatorial circuits, latches, random pattern testability, system clocks
22	Stephen H. Unger, Chung-Jen Tan	Clocking Schemes for High-Speed Digital Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
22	Theja Tulabandhula, Yujendra Mitikiri	A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS.	VLSI Design	2009	DBLP DOI BibTeX RDF
22	Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte	Energy-aware opcode design.	ICCD	2008	DBLP DOI BibTeX RDF
22	Vikas Chandra, Robert C. Aitken	Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.	DFT	2008	DBLP DOI BibTeX RDF
22	Shuangyu Ruan, Kazuteru Namba, Hideo Ito	Soft Error Hardened FF Capable of Detecting Wide Error Pulse.	DFT	2008	DBLP DOI BibTeX RDF
22	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Latch Susceptibility to Transient Faults and New Hardening Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design
22	Eric L. Hill, Mikko H. Lipasti	Transparent mode flip-flops for collapsible pipelines.	ICCD	2007	DBLP DOI BibTeX RDF
22	Himanshu Thapliyal, A. Prasad Vinod 0001	Design of Reversible Sequential Elements With Feasibility of Transistor Implementation.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.	DFT	2007	DBLP DOI BibTeX RDF
22	Man Chung Hon	Spec-based flip-flop and latch repeater planning.	ASP-DAC	2006	DBLP DOI BibTeX RDF
22	Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty	Untestable Multi-Cycle Path Delay Faults in Industrial Designs.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
22	Li-Hsun Chen, Oscal T.-C. Chen	A hardware-efficient FIR architecture with input-data and tap folding.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
22	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Complexity-Effective Reorder Buffer Designs for Superscalar Processors.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
22	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction
22	Frank te Beest, Ad M. G. Peeters, Kees van Berkel 0001, Hans G. Kerkhoff	Synchronous Full-Scan for Asynchronous Handshake Circuits.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	L1L2*, DFT, asynchronous circuits, scan design, LSSD
22	Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev 0001, Kanad Ghose	Energy Efficient Register Renaming.	PATMOS	2003	DBLP DOI BibTeX RDF
22	Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong	A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
22	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
22	Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster	Synchronous Interlocked Pipelines.	ASYNC	2002	DBLP DOI BibTeX RDF	progressive stalls, synchronous, Pipeline, asynchronous, clock gating, elastic, interlocked
22	Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee	Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	AOP, finite field, Bit-parallel systolic multiplier, ESP
22	Nobuo Funabiki, Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	A Global Routing Technique for Wave-Steering Design Methodology.	DSD	2001	DBLP DOI BibTeX RDF
22	Peter-Michael Seidel, Guy Even	On the Design of Fast IEEE Floating-Point Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
22	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
22	Oscal T.-C. Chen, Wei-Lung Liu	An FIR processor with programmable dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
22	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists.	CAV	1999	DBLP DOI BibTeX RDF
22	Bernhard Korte	How Long Does a Bit Live in a Computer? (abstract).	ESA	1999	DBLP DOI BibTeX RDF
22	Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli	A methodology for correct-by-construction latency insensitive design.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Christoph Albrecht, Bernhard Korte, Jürgen Schietke, Jens Vygen	Cycle time and slack optimization for VLSI-chips.	ICCAD	1999	DBLP DOI BibTeX RDF