Search results for "programmable-logic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Programmable Logic Arrays with Universal Literals.	ISMVL	1997	DBLP DOI BibTeX RDF	universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays
62	Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton	Architectures and algorithms for synthesizable embedded programmable logic cores.	FPGA	2003	DBLP DOI BibTeX RDF	programmable logic cores, FPGA, standard cells, system-on-chip design
55	André DeHon, Michael J. Wilson	Nanowire-based sublithographic programmable logic arrays.	FPGA	2004	DBLP DOI BibTeX RDF	sublithographic architecture, programmable logic arrays, nanowires
54	David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi	Testing of programmable logic devices (PLD) with faulty resources.	DFT	1997	DBLP DOI BibTeX RDF	faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices
52	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect
50	Peter Hallschmid, Steven J. E. Wilton	Detailed routing architectures for embedded programmable logic IP cores.	FPGA	2001	DBLP DOI BibTeX RDF	FPGA, programmable logic, detailed routing, SoC design, embedded cores
50	Bill Carter	The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract].	FPL	2001	DBLP DOI BibTeX RDF
46	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
45	Charles Hsu	Future Prospective of Programmable Logic Non-volatile Device.	MTDT	2006	DBLP DOI BibTeX RDF
44	John Y. Oliver, Venkatesh Akella	Improving DSP Performance with a Small Amount of Field Programmable Logic.	FPL	2003	DBLP DOI BibTeX RDF
43	Andy Yan, Steven J. E. Wilton	Product-Term-Based Synthesizable Embedded Programmable Logic Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
42	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
41	Lizy Kurian John	VaWiRAM: a variable width random access memory module.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
41	Santonu Sarkar, Anupam Basu, Arun K. Majumdar	Representation and Synthesis of Interface of a Circuit for its Reuse.	VLSI Design	1996	DBLP DOI BibTeX RDF	VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
40	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
40	Branka Medved Rogina, Karolj Skala, Bozidar Vojnovic	Metastability Characteristics Testing for Programmable Logic Design.	FPL	1996	DBLP DOI BibTeX RDF
40	Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx	The Implementation of a Field Programmable Logic Based Co-Processor for the Acceleration of Discrete Event Simulators.	FPL	1996	DBLP DOI BibTeX RDF
40	C. P. Cowen, S. Monaghan	Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic- based Custom Computing Machine.	FPL	1994	DBLP DOI BibTeX RDF
40	Nigel Toon	Reconfigurable Hardware from Programmable Logic Devices.	FPL	1994	DBLP DOI BibTeX RDF
40	Nigel Toon	Continuous Interconnect Provides Solution to Density/Performance Trade-Off in Programmable Logic.	FPL	1994	DBLP DOI BibTeX RDF
39	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
37	Charles E. Stroud, James R. Bailey, Johan R. Emmert	A New Method for Testing Re-Programmable PLAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	electrically erasable programmable logic array testing, manufacturing test development, bridging faults
37	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
37	Giby Samson, Lawrence T. Clark	Circuit architecture for low-power race-free programmable logic arrays.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	circuit timing, low power, programmable logic arrays
35	Peter Zipf, Manfred Glesner, Christine Bauer 0002, Hans Wojtkowiak	Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.	FPL	2002	DBLP DOI BibTeX RDF
35	Javier Ramírez 0001, Antonio García 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz	Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic
35	Michael D. Hutton	Interconnect prediction for programmable logic devices.	SLIP	2001	DBLP DOI BibTeX RDF	interconnect prodiction, wireability, architecture, programmable logic device
35	Seungkweon Jeong, Young Shin Kim, Wook Hyun Kwon	Scheduling algorithm for programmable logic controllers with remote I/Os.	RTCSA	1997	DBLP DOI BibTeX RDF	remote I/O, remote input output, sequence programs, application processor, bounded response time, scheduling algorithm, network processor, computer simulation, multitasking, data transmission, programmable logic controllers, PLC, programmable controllers
35	D. M. Marcynuk, D. Michael Miller	The OR-k method for on-line checking of programmable logic arrays.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	fault secure design, on-line checking, concurrency, programmable logic array
35	Bradley R. Quinton, Steven J. E. Wilton	Embedded Programmable Logic Core Enhancements for System Bus Interfaces.	FPL	2007	DBLP DOI BibTeX RDF
34	Gordon J. Brebner	Multithreading for Logic-Centric Systems.	FPL	2002	DBLP DOI BibTeX RDF
33	Yahiko Kambayashi	Logic Design of Programmable Logic Arrays.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	two-level circuit, Incompletely specified logic function, reduction of the number of inputs, logic design, programmable logic array, multiple-output function
33	Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic	Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices.	FPL	2002	DBLP DOI BibTeX RDF
33	Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell	Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic.	FPL	2001	DBLP DOI BibTeX RDF
33	Gordon J. Brebner	Field-Programmable Logic: Catalyst for New Computing Paradigms.	FPL	1998	DBLP DOI BibTeX RDF
32	Christian Siemers, Volker Winterstein	Modelling Programmable Logic Devices and Reconfigurable, Microprocessor-Related Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
31	Gordon J. Brebner	Programmable Logic Has More Computational Power than Fixed Logic.	FPL	2004	DBLP DOI BibTeX RDF
31	Philip James-Roxby, Gordon J. Brebner	Multithreading in a Hyper-programmable Platform for Networked Systems.	FPL	2004	DBLP DOI BibTeX RDF
31	Henry Selvaraj, Mariusz Rawski, Tadeusz Luba	FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition.	ITCC	2002	DBLP DOI BibTeX RDF	programmable read only memory, Boolean functions, implementation, digital circuits, sequential machines, logic minimization
31	Tom Kean	It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures.	FPL	2000	DBLP DOI BibTeX RDF
31	Kiyoshi Oguri, Norbert Imlig, Hideyuki Ito, Kouichi Nagami, Ryusuke Konishi, Tsunemichi Shiozawa	General-Purpose Computer Architecture Based on Fully Programmable Logic.	ICES	1998	DBLP DOI BibTeX RDF
31	A. Abo Shosha, P. Reinhart, F. Rongen	Reconfigurable PCI-Bus Interface (RPCI).	FPL	1998	DBLP DOI BibTeX RDF
30	Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu	A graph representation for programmable logic arrays to facilitate testing and logic design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
29	Yu Hu 0002, Satyaki Das, Steven Trimberger, Lei He 0001	Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
28	Paul Metzgen	A high performance 32-bit ALU for programmable logic.	FPGA	2004	DBLP DOI BibTeX RDF	ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors
28	Dieter Spath, Ulf Osmers	Virtual Reality - An Approach to Improve the Generation of Fault-Free Software for Programmable Logic Controllers (PLC).	ICECCS	1996	DBLP DOI BibTeX RDF	fault free software, instruction list, ladder diagram, virtual reality, programmable logic controllers, programmable controllers, low-level languages
28	Parthasarathy P. Tirumalai, Jon T. Butler	Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	minimisation algorithms, multiple-valued programmable logic arrays, sum-of products, MIN operation, random-symmetric functions, constrained implicant sets, charge-coupled device circuits, performance, CMOS, heuristic algorithms, many-valued logics, minimisation, CMOS integrated circuits, backtracking, logic arrays, tree search, multiple-valued functions, charge-coupled device
28	James Jacob, Nripendra N. Biswas	Further Comments on "Detection of Faults in Programmable Logic Arrays".	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	fault detection, fault location, programmable logic arrays, logic arrays
28	Saied Bozorgui-Nesbat, Edward J. McCluskey	Lower Overhead Design for Testability of Programmable Logic Arrays.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	test generation for PLA's, PLA testing, Design for testability, programmable logic arrays (PLA)
28	Hao-Yung Lo, Yoshinao Aoki	Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	ROM's, Arithmetic units error correction, binary antilogarithm generation, binary logarithm generation, differential group programmable logic arrays (DGPLA's), PLA's
28	Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara	An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	stuck-type faults, Cross-point faults, easily testable design, programmable logic arrays, multiple faults
28	Hideo Fujiwara, Kozo Kinoshita	A Design of Programmable Logic Arrays with Universal Tests.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Easily testable design, programmable logic arrays (PLA's), fault detection, fault location, logic circuits, universal test sets
28	Wilfried Daehn, Joachim Mucha	A Hardware Approach to Self-Testing of Large Programmable Logic Arrays.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	programmable logic array (PLA), Built-in test, pattern generation, nonlinear feedback shift registers
28	Tsutomu Sasao	Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Complexity of logic circuits, programmable logic array, multiple-valued logic, functional decomposition, symmetric function
28	Vinod K. Agarwal	Multiple Fault Detection in Programmable Logic Arrays.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	single fault coverage, Contact faults, PLA fault detection, PLA modeling, programmable logic arrays, masking, multiple fault detection
28	Suhas S. Patil, Terry A. Welch	A Programmable Logic Approach for VLSI.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	very large-scale integrated (VLSI) technology, digital integrated circuit design, programmable logic circuits, Asynchronous circuits, logic arrays, digital systems design
28	Thaddeus Kobylarz, Atef Al-Najjar	An Examination of the Cost Function for Programmable Logic Arrays.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	programmable logic arrays (PLA's), cyclic tables, minimal covers, multiple output combinational circuits, minimization, Cost functions
28	Roy A. Wood	A High Density Programmable Logic Array Chip.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	Array folding techniques, array logic, array optimization, folded array configuration, programmable logic array (PLA)
28	Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev	Interconnect enhancements for a high-speed PLD architecture.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, architecture, interconnect, programmable logic
28	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
28	Steve Trimberger	Redefining the FPGA for the Next Generation.	FPL	2007	DBLP DOI BibTeX RDF
28	Hamish Fallside, Michael John Sebastian Smith	Internet Connected FPL.	FPL	2000	DBLP DOI BibTeX RDF
28	Samary Baranov	CAD System for ASM and FSM Synthesis.	FPL	1998	DBLP DOI BibTeX RDF
26	Tan Nguyen, Zachary Blair, Stephen Neuendorffer, John Wawrzynek	SPADES: A Productive Design Flow for Versal Programmable Logic.	FPL	2023	DBLP DOI BibTeX RDF
26	Laurent Fesquet, Marc Renaudin	A Programmable Logic Architecture for Prototyping Clockless Circuits.	FPL	2005	DBLP DOI BibTeX RDF
26	Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides	Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.	FPL	2005	DBLP DOI BibTeX RDF
26	Norbert Pramstaller, Johannes Wolkerstorfer	A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.	FPL	2004	DBLP DOI BibTeX RDF
26	Albert Simpson, Jill K. Hunter, Moira Wylie, Yi Hu, David Mann	Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing.	FPL	2001	DBLP DOI BibTeX RDF
26	E. Cantó, Juan Manuel Moreno, Joan Cabestany, Julio Faura, Josep Maria Insenser	A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic.	FPL	1999	DBLP DOI BibTeX RDF
26	Reiner W. Hartenstein, Manfred Glesner (eds.)	Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings	FPL	1996	DBLP DOI BibTeX RDF
26	Markus Weinhardt	Portable Pipeline Synthesis for FCCMs.	FPL	1996	DBLP DOI BibTeX RDF
26	Alessandro Balboni, Loris Valenti	ASIC Design and FPGA Design: A Unified Design Methodology Applied to Different Technologies.	FPL	1996	DBLP DOI BibTeX RDF
26	Albrecht Ditzinger, Ralph Remme	Key Issues for User Acceptance of FPGA Design Tools.	FPL	1996	DBLP DOI BibTeX RDF
26	Holger Eggers, Patrick Lysaght, Hugh Dick, Gordon Charles McGregor	Fast Reconfigurable Crossbar Switching in FPGAs.	FPL	1996	DBLP DOI BibTeX RDF
26	Uwe Meyer-Bäse	Coherent Demodulation with FPGAs.	FPL	1996	DBLP DOI BibTeX RDF
26	Kalle Tammemäe, Mattias O'Nils, Ahmed Hemani	Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems.	FPL	1996	DBLP DOI BibTeX RDF
26	John R. Haddy, David J. Skellern	An Asynchronous Transfer Mode (ATM) Stream Demultiplexer and Switch.	FPL	1996	DBLP DOI BibTeX RDF
26	Sébastien Pillement, Lionel Torres, Michel Robert, Gaston Cambon	Concurrent Design of Hardware/Software Dedicated Systems.	FPL	1996	DBLP DOI BibTeX RDF
26	Milan Vasilko, Djamel Ait-Boudaoud	Optically Reconfigurable FPGAs: Is this a Future Trend?	FPL	1996	DBLP DOI BibTeX RDF
26	Milan Vasilko, Djamel Ait-Boudaoud	Architectural Synthesis Techniques for Dynamically Reconfigurable Logic.	FPL	1996	DBLP DOI BibTeX RDF
26	Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano	ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.	FPL	1996	DBLP DOI BibTeX RDF
26	Chris Dick, Fred Harris 0001	FIR Filtering with FPGAs Using Quadrature Sigma-Delta Modulation Encoding.	FPL	1996	DBLP DOI BibTeX RDF
26	Nigel Lester, Jonathan Saul	Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form.	FPL	1996	DBLP DOI BibTeX RDF
26	Michael Gschwind, Christian Mautner	Migration from Schematic-Based Designs to a VHDL Synthesis Environment.	FPL	1996	DBLP DOI BibTeX RDF
26	Carl Ebeling, Darren C. Cronquist, Paul Franklin	RaPiD - Reconfigurable Pipelined Datapath.	FPL	1996	DBLP DOI BibTeX RDF
26	Stefan H.-M. Ludwig	The Design of a Coprocessor Board Using Xilinx's XC6200 FPGA - An Experience Report.	FPL	1996	DBLP DOI BibTeX RDF
26	Steve Casselman	Reconfigurable Logic Based Fibre Channel Network Card With Sub 2 Micro-Second Raw Latency.	FPL	1996	DBLP DOI BibTeX RDF
26	Toshiaki Miyazaki, Akihiro Tsutsui, Kenji Ishii, Naohisa Ohta	FACT: Co-evaluation Environment for FPGA Architecture and CAD System.	FPL	1996	DBLP DOI BibTeX RDF
26	David W. Trainor, Roger F. Woods	Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays.	FPL	1996	DBLP DOI BibTeX RDF
26	Kevin Rowley, Colin Lyden	Implementing Sigma Delta Modulator Prototype Designs on an FPGA.	FPL	1996	DBLP DOI BibTeX RDF
26	Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano	An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware.	FPL	1996	DBLP DOI BibTeX RDF
26	Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada	Solving Satisfiability Problems on FPGAs.	FPL	1996	DBLP DOI BibTeX RDF
26	Tom Kean, Bernie New, Robert Slous	A Fast Constant Coefficient Multiplier for the XC6200.	FPL	1996	DBLP DOI BibTeX RDF
26	Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002	Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view.	FPL	1996	DBLP DOI BibTeX RDF
26	Uwe Meyer-Bäse	Convolutional Error Decoding with FPGAs.	FPL	1996	DBLP DOI BibTeX RDF
26	Gulsun Yasar, Julie Devins, Yelena Tsyrkina, Gregg Stadtlander, Eric Millham	Growable FPGA Macro Generator.	FPL	1996	DBLP DOI BibTeX RDF
26	Zoran A. Salcic, R. Bruce Maunder	CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs.	FPL	1996	DBLP DOI BibTeX RDF
26	César Sanz, Laura de Zulueta, Juan M. Meneses	FPGA Implementation of the Block-Matching Algorithm for Motion Estimation in Image Coding.	FPL	1996	DBLP DOI BibTeX RDF
26	Michael Braun 0002, Jörg Friedrich, Thomas Grün, Josef Lembert	Parallel CRC Computation in FPGAs.	FPL	1996	DBLP DOI BibTeX RDF
26	Jean-Paul Heron, Roger F. Woods	Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA.	FPL	1996	DBLP DOI BibTeX RDF