Search results for "sleep-transistor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
152	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Optimal sleep transistor synthesis under timing and area constraints.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
150	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware sleep transistor design for reliable power-gating.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	reliability, sizing, sleep-transistor, nbti
125	Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang	A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	DSTN, low power, MTCMOS, sleep transistor
122	Kaijian Shi, David Howard	Challenges in sleep transistor design and implementation in low-power designs.	DAC	2006	DBLP DOI BibTeX RDF	methodology, low-power design, power gating, sleep transistor
113	Ehsan Pakbaznia, Massoud Pedram	Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.	DATE	2008	DBLP DOI BibTeX RDF
113	Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Le Kang, Xianlong Hong	A novel performance driven power gating based on distributed sleep transistor network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
102	Jie Gu 0003, Hanyong Eom, Chris H. Kim	Sleep transistor sizing and control for resonant supply noise damping.	ISLPED	2007	DBLP DOI BibTeX RDF	resonant supply noise, sleep transistor, damping
99	Changbo Long, Lei He 0001	Distributed sleep transistor network for power reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
99	Changbo Long, Lei He 0001	Distributed sleep transistor network for power reduction.	DAC	2003	DBLP DOI BibTeX RDF
98	Vishal Khandelwal, Ankur Srivastava 0001	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
98	Vishal Khandelwal, Ankur Srivastava 0001	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
94	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	layout, leakage power, insertion, standard-cell, sleep transistor
86	Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu	Functionality directed clustering for low power MTCMOS design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
82	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Post-layout leakage power minimization based on distributed sleep transistor insertion.	ISLPED	2004	DBLP DOI BibTeX RDF	sub-threshold current, leakage power, sleep transistor
78	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
71	De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang	Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.	DAC	2007	DBLP DOI BibTeX RDF
67	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
67	Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu	Can SG-FET Replace FET in Sleep Mode Circuits?	NanoNet	2009	DBLP DOI BibTeX RDF	SG-FET, power gating, sleep transistor
66	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
65	Yu Wang 0002, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang 0004	Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.	ISQED	2006	DBLP DOI BibTeX RDF
63	Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.	DATE	2007	DBLP DOI BibTeX RDF
58	Changbo Long, Jinjun Xiong, Lei He 0001	On optimal physical synthesis of sleep transistors.	ISPD	2004	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
57	Anand Ramalingam, Bin Zhang 0011, Anirudh Devgan, David Z. Pan	Sleep transistor sizing using timing criticality and temporal currents.	ASP-DAC	2005	DBLP DOI BibTeX RDF
52	De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh	Timing driven power gating.	DAC	2006	DBLP DOI BibTeX RDF	leakage current, power gating, IR drop
52	Ramaprasath Vilangudipitchai, Poras T. Balsara	Power Switch Network Design for MTCMOS.	VLSI Design	2005	DBLP DOI BibTeX RDF
51	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang	Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.	ICNC (1)	2006	DBLP DOI BibTeX RDF
50	Kaijian Shi, Zhian Lin, Yi-Min Jiang	A Power Network Synthesis Method for Industrial Power Gating Designs.	ISQED	2007	DBLP DOI BibTeX RDF
50	Enrico Macii	Leakage power optimization in standard-cell designs.	SBCCI	2004	DBLP DOI BibTeX RDF
50	James T. Kao, Anantha P. Chandrakasan, Dimitri A. Antoniadis	Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology.	DAC	1997	DBLP DOI BibTeX RDF
49	Yu Wang 0002, Ku He, Rong Luo, Hui Wang 0004, Huazhong Yang	Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
46	Yongho Lee, Deog-Kyoon Jeong, Taewhan Kim	Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
44	Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi	An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition.	ISQED	2009	DBLP DOI BibTeX RDF
44	Zhiyu Liu, Volkan Kursun	Leakage current starved domino logic.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, domino logic, subthreshold leakage current, dual threshold voltage
43	Yu Wang 0002, Hui Wang 0004, Huazhong Yang	Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.	APCCAS	2006	DBLP DOI BibTeX RDF
42	Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh	Precomputation-based Guarding for Dynamic and Leakage Power Reduction.	ICCD	2003	DBLP DOI BibTeX RDF
42	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
38	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
35	Afshin Nourivand, Chunyan Wang 0004, M. Omair Ahmad	An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
31	S. Saqib Khursheed, Sheng Yang 0003, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn	Improved DFT for Testing Power Switches.	ETS	2011	DBLP DOI BibTeX RDF	power switch, leakage power management, test time overhead, DFT, design for test, Sleep transistor
31	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Timing-driven row-based power gating.	ISLPED	2007	DBLP DOI BibTeX RDF	row-based, clustering, leakage power, power-gating, standard cell, sleep transistor
31	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.	ISLPED	2005	DBLP DOI BibTeX RDF	activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
31	Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari	MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
30	Chandramouli Gopalakrishnan, Srinivas Katkoori	KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths.	ICCD	2003	DBLP DOI BibTeX RDF
28	Chandramouli Gopalakrishnan, Srinivas Katkoori	Resource Allocation and Binding Approach for Low Leakage Power.	VLSI Design	2003	DBLP DOI BibTeX RDF
26	Tamer Cakici, Keejong Kim, Kaushik Roy 0001	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
22	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	A Scalable Algorithmic Framework for Row-Based Power-Gating.	DATE	2008	DBLP DOI BibTeX RDF
22	Andrea Calimera, Luca Benini, Enrico Macii	Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.	DATE	2008	DBLP DOI BibTeX RDF
22	Xin Zhao, Yici Cai, Qiang Zhou 0001, Xianlong Hong	A novel low-power physical design methodology for MTCMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi	A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.	ICCD	2005	DBLP DOI BibTeX RDF
21	Abhishek Bhattacharjee, Sambhu Nath Pradhan	NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
21	Gerson D. Andrade, Ricardo A. L. Reis, Eduardo A. C. da Costa, Alexandra L. Zimpeck	Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.	APCCAS	2021	DBLP DOI BibTeX RDF
21	Sherif M. Sharroush	Optimum Sizing of the Sleep Transistor in MTCMOS Technology.	NILES	2020	DBLP DOI BibTeX RDF
21	Jitendra Kumar Mishra, Harshit Srivastava, Prasanna Kumar Misra, Manish Goswami	A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology.	iSES	2018	DBLP DOI BibTeX RDF
21	Rohit Lorenzo, Saurabh Chaudhury	Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
21	Huimei Cheng, Ji Li 0006, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang	Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
21	Daniele Rossi 0001, Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi	NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.	ETS	2015	DBLP DOI BibTeX RDF
21	Kai-Chiang Wu, Ing-Chao Lin, Yao-Te Wang, Shuen-Shiang Yang	BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
21	Qing Xie 0001, Yanzhi Wang, Shuang Chen 0001, Massoud Pedram	Variation-aware joint optimization of the supply voltage and sleep transistor size for the 7nm FinFET technology.	ICCD	2014	DBLP DOI BibTeX RDF
21	Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar	Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit.	CoRR	2013	DBLP BibTeX RDF
21	Kaijian Shi	Sleep transistor design in 28nm CMOS technology.	SoCC	2013	DBLP DOI BibTeX RDF
21	Pradeep Singla, Kamya Dhingra, Naveen Kr. Malik	DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design	CoRR	2012	DBLP BibTeX RDF
21	Sven Rosinger, Wolfgang Nebel	Sleep-Transistor Based Power-Gating Tradeoff Analyses.	PATMOS	2012	DBLP DOI BibTeX RDF
21	Suyoung Bang, David T. Blaauw, Dennis Sylvester, Massimo Alioto	Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems.	CICC	2012	DBLP DOI BibTeX RDF
21	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
21	Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami	Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
21	Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino	Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.	PATMOS	2011	DBLP DOI BibTeX RDF
21	De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang	Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
21	Yongho Lee, Taewhan Kim	Technique for controlling power-mode transition noise in distributed sleep transistor network.	ASP-DAC	2010	DBLP DOI BibTeX RDF
21	Yu Sun, Liyi Xiao, Cong Shi	DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current.	ISCAS	2010	DBLP DOI BibTeX RDF
21	David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat	Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
21	Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi	Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.	ISQED	2010	DBLP DOI BibTeX RDF
21	Sven Rosinger, Domenik Helms, Wolfgang Nebel	RTL power modeling and estimation of sleep transistor based power gating.	J. Embed. Comput.	2009	DBLP DOI BibTeX RDF
21	Jie Gu 0003, Hanyong Eom, John Keane 0001, Chris H. Kim	Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
21	De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang	Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
21	Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan	Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs.	J. Comput.	2008	DBLP DOI BibTeX RDF
21	Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum	ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.	ICCD	2008	DBLP DOI BibTeX RDF
21	Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang 0001, Vivek De	A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
21	Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann, Adrian Mihai Ionescu	Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications.	Nano-Net	2007	DBLP DOI BibTeX RDF
21	Sven Rosinger, Domenik Helms, Wolfgang Nebel	RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating.	PATMOS	2007	DBLP DOI BibTeX RDF
21	Kevin Zhang 0001, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr	SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
21	Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel	Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.	ESSCIRC	2005	DBLP DOI BibTeX RDF
21	Amit Agarwal 0001, Kaushik Roy 0001, Ram K. Krishnamurthy	A leakage-tolerant low-leakage register file with conditional sleep transistor.	SoCC	2004	DBLP DOI BibTeX RDF
21	James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De	Dynamic sleep transistor and body bias for active leakage power control of microprocessors.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
14	Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur	In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits.	ISLPED	2010	DBLP DOI BibTeX RDF	DVTS loop, in-situ power monitor, power optimum point, variable body bias, variable supply voltage, low power, ground bounce
14	Lerong Cheng, Fei Li 0003, Yan Lin 0001, Phoebe Wong, Lei He 0001	Device and Architecture Cooptimization for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang	An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy 0001	Analysis of super cut-off transistors for ultralow power digital logic circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	carbon nanotube FETs, tunneling transistors
14	Vijay K. Jain, Glenn H. Chapman	Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC.	DFT	2006	DBLP DOI BibTeX RDF	3D Heterogeneous sensor, redundancy and reconfiguration, energy economization, heterogeneous SOC, J-platform, defect tolerance
14	Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif	Benefits and Costs of Power-Gating Technique.	ICCD	2005	DBLP DOI BibTeX RDF
14	Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	Reducing leakage energy in FPGAs using region-constrained placement.	FPGA	2004	DBLP DOI BibTeX RDF	region-constrained placement, FPGA, leakage power
14	Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy	High-level area and power-up current estimation considering rich cell library.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy	High Level Area and Current Estimation.	PATMOS	2003	DBLP DOI BibTeX RDF
14	Avi Efrati, Moshe Kleyner	Timing analysis challenges for high speed CPUs at 90nm and below.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF