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Publication years (Num. hits)
2003-2006 (18) 2007-2008 (16) 2009-2010 (20) 2011-2013 (19) 2014-2017 (15) 2018-2022 (16) 2023 (2)
Publication types (Num. hits)
article(20) incollection(1) inproceedings(85)
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Found 106 publication records. Showing 106 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
122Kelly D. Larson Translation of an existing VMM-based SystemVerilog testbench to OVM. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF OVM, VMM, testbenches, SystemVerilog
96Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. Search on Bibsonomy ISMVL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
89Tom Fitzpatric System Verilog for VHDL Users. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
78Donatella Sciuto, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji SystemC and SystemVerilog: Where do They Fit? Where are They Going? Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
68Clifford E. Cummings SystemVerilog implicit port enhancements accelerate system design & verification. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF *, .name, Verilog EMACS mode, implicit ports, Verilog, instantiation, SystemVerilog
60Doron Bustan, John Havlicek Some Complexity Results for SystemVerilog Assertions. Search on Bibsonomy CAV The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Alexander Krupp, Wolfgang Müller 0003 Classification trees for random tests and functional coverage. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil Synthesis of synchronous assertions with guarded atomic actions. Search on Bibsonomy MEMOCODE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
44Brian Bailey Was it worth the wait? Yes! Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF verification, formal verification, design reuse, testbench, SystemVerilog
42Albert Chiang, Wei-Hua Han, Bhanu Kapoor Validating physical access layer of WiMAX using SystemVerilog. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
42Hai H. Wang, Shengchao Qin, Jun Sun 0001, Jin Song Dong Realizing Live Sequence Charts in SystemVerilog. Search on Bibsonomy TASE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Yingpan Wu, Lixin Yu, Wei Zhuang, Jianyong Wang A Coverage-Driven Constraint Random-Based Functional Verification Method of Pipeline Unit. Search on Bibsonomy ACIS-ICIS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
36Steve Haynal, Timothy Kam, Michael Kishinevsky, Emily Shriver, Xinning Wang A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. Search on Bibsonomy MEMOCODE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36A. Bernstein, M. Burton, Frank Ghenassia How to bridge the abstraction gap in system level modeling and design. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Kausik Datta, Partha Pratim Das Assertion Based Verification Using HDVL. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Rishiyur S. Nikhil Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design). Search on Bibsonomy GPCE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
26Michael Siegel, Adriana Maggiore, Christian Pichler Untwist your brain: efficient debugging and diagnosis of complex assertions. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF SystemVerilog assertions, debugging, assertions, fault localization, functional verification, root cause analysis
26Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch Building a standard ESL design and verification methodology: is it just a dream? Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF modeling rapid hardware prototyping, design, verification, methodology, systemC, RTL, ESL, C/C++, systemVerilog
26Annette Bunker, Ganesh Gopalakrishnan, Sally A. McKee Formal hardware specification languages for protocol compliance verification. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Heterogeneous Hardware Logic, Hierarchical Annotated Action Diagrams, Lava, Objective VHDL, OpenVera, SpecC, Specification and Description Language, The Unified Modeling Language, Java, Statecharts, SystemC, Message Sequence Charts, Esterel, Live Sequence Charts, timing diagrams, hardware monitors, SystemVerilog, e, Property Specification Language
26James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois ESys.Net: a new solution for embedded systems modeling and simulation. Search on Bibsonomy LCTES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF CIL, ESys.Net, attribute programming, component-based programming, simulation, Java, modeling, embedded systems, C++, framework, system on chip, VHDL, SystemC, hardware/software codesign, C#, Net, Verilog, HDLs, SystemVerilog
24Bilal Majeed, Conor Ryan, Jack McEllin, Ayman Youssef, Douglas Mota Dias, Aidan Murphy, Samuel Carvalho Evolving Behavioural Level Sequence Detectors in SystemVerilog Using Grammatical Evolution. Search on Bibsonomy ICAART (3) The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Wei-Ting Yeh, Chung-Lun Chang, Shang-Chih Yin, Chien-Hung Tsai Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs. Search on Bibsonomy GCCE The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Michael Kwaku Tetteh, Douglas Mota Dias, Conor Ryan Grammatical Evolution of Complex Digital Circuits in SystemVerilog. Search on Bibsonomy SN Comput. Sci. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
24Christos Sapsanis, Martin Villemur, Andreas G. Andreou Real Number Modeling of a SAR ADC behavior using SystemVerilog. Search on Bibsonomy SMACD The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
24Nikolaos Georgoulopoulos, Alkiviades A. Hatzopoulos Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog. Search on Bibsonomy J. Electron. Test. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
24Michael Kwaku Tetteh, Douglas Mota Dias, Conor Ryan Evolution of Complex Combinational Logic Circuits Using Grammatical Evolution with SystemVerilog. Search on Bibsonomy EuroGP The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
24Yuichi Kamina, Keisuke Iwai, Takashi Matsubara 0002, Takakazu Kurokawa A Translator from FDL to SystemVerilog for FPGA Implementation of Fuzzy Inference. Search on Bibsonomy CANDAR (Workshops) The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif, Wasi Haider Butt A model-driven framework for design and verification of embedded systems through SystemVerilog. Search on Bibsonomy Des. Autom. Embed. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos UVM-based Verification of a Digital PLL Using SystemVerilog. Search on Bibsonomy PATMOS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Constantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos Design of a SystemVerilog-Based Sigma-Delta ADC Real Number Model. Search on Bibsonomy DSD The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Mina Louis, Mohamed Dessouky, Ashraf Salem PLL Real Number Modeling in SystemVerilog. Search on Bibsonomy SMACD The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Juan-José Crespo, German Maglione Mathey, José L. Sánchez 0002, Francisco J. Alfaro-Cortes, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001 Methodology for Decoupled Simulation of SystemVerilog HDL Designs. Search on Bibsonomy HPCS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos Design of a Digital PLL Real Number Model Using SystemVerilog. Search on Bibsonomy MOCAST The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Nikolaos Georgoulopoulos, Athanasios Mekras, Alkiviadis A. Hatzopoulos Design of a SystemVerilog-Based VCO Real Number Model. Search on Bibsonomy MOCAST The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Nikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog. Search on Bibsonomy PATMOS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu 0001, Wendelin Serwe Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Michael Bedford Taylor Basejump STL: systemverilog needs a standard template library for hardware design. Search on Bibsonomy DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos Efficiency evaluation of a SystemVerilog-based real number model. Search on Bibsonomy MOCAST The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog. Search on Bibsonomy Des. Autom. Embed. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Ka Lok Man, Chi-Un Lei, Hemangee K. Kapoor, Tomas Krilavicius, Jieming Ma, Nan Zhang PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. Search on Bibsonomy Comput. Informatics The full citation details ... 2016 DBLP  BibTeX  RDF
24Oriol Arcas-Abella, Nehir Sönmez Bluespec SystemVerilog. Search on Bibsonomy FPGAs for Software Programmers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Aamir M. Khan, Muhammad Rashid Generation of SystemVerilog Observers from SysML and MARTE/CCSL. Search on Bibsonomy ISORC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Muhammad Rashid, Muhammad Waseem Anwar, Farooque Azam Expressing embedded systems verification aspects at higher abstraction level - SystemVerilog in Object Constraint Language (SVOCL). Search on Bibsonomy SysCon The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Ji-Eun Jang, Jaeha Kim PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky SystemVerilog assertion debugging: A visualization and pattern matching model. Search on Bibsonomy PACRIM The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Jeremy Ridgeway Performance of a SystemVerilog Sudoku Solver with VCS. Search on Bibsonomy MTV The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Sara Marconi, Elia Conti, Jorgen Christiansen, Pisana Placidi Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications. Search on Bibsonomy ISSE The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Sara Marconi, Elia Conti, Pisana Placidi, Andrea Scorzoni, Jorgen Christiansen, Tomasz Hemperek A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications. Search on Bibsonomy ApplePies The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Yunzhong Zhu, Tao Li, Jingpeng Guo, Haiyang Zhou, Fangfa Fu A novel low-cost interface design for SystemC and SystemVerilog Co-simulation. Search on Bibsonomy ASICON The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Ning Zhou, Xinyan Gao, Jinzhao Wu, Jianchao Wei, Dakui Li Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions. Search on Bibsonomy J. Appl. Math. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Abhishek Jain 0003, Piyush Kumar Gupta, Hima Gupta, Sachish Dhar Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator. Search on Bibsonomy CoRR The full citation details ... 2014 DBLP  BibTeX  RDF
24Jaeha Kim, Si-Jung Yang, Ji-Eun Jang PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. Search on Bibsonomy CICC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Xinyan Gao, Ning Zhou, Jinzhao Wu, Dakui Li Wu's Characteristic Set Method for SystemVerilog Assertions Verification. Search on Bibsonomy J. Appl. Math. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Dave Rich The unique challenges of debugging design and verification code jointly in SystemVerilog. Search on Bibsonomy FDL The full citation details ... 2013 DBLP  BibTeX  RDF
24Jonathan Bromley If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language. Search on Bibsonomy FDL The full citation details ... 2013 DBLP  BibTeX  RDF
24Kaiming Ho SystemVerilog: The new standard. Search on Bibsonomy FDL The full citation details ... 2013 DBLP  BibTeX  RDF
24Ji-Eun Jang, Si-Jung Yang, Jaeha Kim Event-driven simulation of Volterra series models in SystemVerilog. Search on Bibsonomy CICC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. Search on Bibsonomy DAC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Doron Bustan, Dmitry Korchemny, Erik Seligman, Jin Yang 0006 SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou A formal method to improve SystemVerilog functional coverage. Search on Bibsonomy HLDVT The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Sangook Moon Systemverilog-based approach of a design of multiplication server farms. Search on Bibsonomy ICUFN The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Sergio H. M. Durand, Vanderlei Bonato A tool to support Bluespec SystemVerilog coding based on UML diagrams. Search on Bibsonomy IECON The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. Search on Bibsonomy CICC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Jomu George Mani Paret, Otmane Aït Mohamed Modeling discrete event system with distributions using SystemVerilog. Search on Bibsonomy ISCAS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Dominic Richards, David R. Lester A monadic approach to automated reasoning for Bluespec SystemVerilog. Search on Bibsonomy Innov. Syst. Softw. Eng. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Brian Keng, Sean Safarpour, Andreas G. Veneris Automated debugging of SystemVerilog assertions. Search on Bibsonomy DATE The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Hans Eveking, Tobias Dornes, Martin Schweikert Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. Search on Bibsonomy HLDVT The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Ryuichi Takahashi, Yoshiyasu Takefuji SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project. Search on Bibsonomy MSE The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Jae-Jin Lee, Young-Jin Oh, Gi-Yong Song Design and verification of an application-specific PLD using VHDL and SystemVerilog. Search on Bibsonomy ASICON The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. Search on Bibsonomy DIFTS@FMCAD The full citation details ... 2011 DBLP  BibTeX  RDF
24Arash Saifhashemi, Peter A. Beerel SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. Search on Bibsonomy CPA The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Myoung-Keun You, Gi-Yong Song SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Bahram Hakhamaneshi, Behnam S. Arad A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog. Search on Bibsonomy CATA The full citation details ... 2010 DBLP  BibTeX  RDF
24Alexander Bol, Wolfgang Müller 0003, Alexander Krupp Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen. Search on Bibsonomy MBMV The full citation details ... 2010 DBLP  BibTeX  RDF
24David Rich A Solution to the Lack of Multiple Inheritance in SystemVerilog. Search on Bibsonomy FDL The full citation details ... 2010 DBLP  BibTeX  RDF
24Dominic Richards, David R. Lester A Prototype Embedding of Bluespec SystemVerilog in the PVS Theorem Prover. Search on Bibsonomy NASA Formal Methods The full citation details ... 2010 DBLP  BibTeX  RDF
24Chengjie Zang, Shinji Kimura Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Ivan Kastelan, Zoran Krajacevic Synthesizable SystemVerilog Assertions as a Methodology for SoC. Search on Bibsonomy ECBS-EERC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Robert C. Page, Sakar Jain Verification of the CoreNet Fabric with SystemVerilog. Search on Bibsonomy MTV The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. Search on Bibsonomy ISMVL The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Ka Lok Man PAFSV: A process algebraic framework for SystemVerilog. Search on Bibsonomy IMCSIT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Ronald W. Mehler SystemVerilog Maximum Performance Maneuvers. Search on Bibsonomy MSV The full citation details ... 2008 DBLP  BibTeX  RDF
24Tingjun Wen, Tadeusz Kwasniewski Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. Search on Bibsonomy BMAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Peter Jensen, Wolfgang Ecker, Thomas Kruse, Martin Zambaldi SystemVerilog: Interface Based Design. Search on Bibsonomy FDL The full citation details ... 2004 DBLP  BibTeX  RDF
24Martin Zambaldi, Wolfgang Ecker, Thomas Kruse, Wolfgang Müller 0003 The Formal Simulation Semantics of SystemVerilog. Search on Bibsonomy FDL The full citation details ... 2004 DBLP  BibTeX  RDF
24Phil Moorby Design for Verification with SystemVerilog. Search on Bibsonomy VLSI Design The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
24David I. Rich The Evolution of SystemVerilog. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2003 DBLP  BibTeX  RDF
18Daniel Gajski, Todd M. Austin, Steve Svoboda What input-language is the best choice for high level synthesis (HLS)? Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
18Perry Alexander Rosetta: Standardization at the System Level. Search on Bibsonomy Computer The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
18Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough Instrumenting AMS assertion verification on commercial platforms. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
18Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003 Intel® atomTM processor core made FPGA-synthesizable. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF intel atom, synthesizable core, fpga, emulator
18Christian Dax, Felix Klaedtke, Martin Lange On Regular Temporal Logics with Past, . Search on Bibsonomy ICALP (2) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
18Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti Inline Assertions - Embedding Formal Properties in a Test Bench. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
18Alon Gluska, Lior Libis Shortening the verification cycle with synthesizable abstract models. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF verification, logic design, abstract modeling
18Kermin Fleming, Chun-Chieh Lin, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks H.264 Decoder: A Case Study in Multiple Design Points. Search on Bibsonomy MEMOCODE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Nathaniel J. August A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF pre-silicon, validation, mixed-signal
18Dennis Brophy IEEE Market-Oriented Standards Process and the EDA Industry. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi Heterogeneous Behavioral Hierarchy Extensions for SystemC. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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