Search results for "test-sets"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
59	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets without test generation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	test generation, stuck-at faults, Bridging faults, n-detection test sets
43	M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
43	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
41	Hideyuki Ichihara, Tomoo Inoue	Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding.	DELTA	2002	DBLP DOI BibTeX RDF	statistical code, test generation, ATE, test compression, test compaction
41	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	Compact test sets for high defect coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
41	Irith Pomeranz, Sudhakar M. Reddy	On the Compaction of Test Sets Produced by Genetic Optimization.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test generation, test compaction, genetic optimization, n-detection test sets
41	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Scan circuits, test application time, static test compaction
38	Hyung Ki Lee, Dong Sam Ha, Kwanghyun Kim	Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits.	DAC	1989	DBLP DOI BibTeX RDF
38	Gwénaël Richomme, Francis Wlazinski	Finite Test-Sets for Overlap-Free Morphisms.	MFCS	2002	DBLP DOI BibTeX RDF	overlap-free words, test-sets, Combinatorics on words, morphisms
38	M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor	Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume.	ITC	2002	DBLP DOI BibTeX RDF	compact test sets, ATPG, fault coverage, stuck-at faults, test length, Test point insertion, gate-delay faults
36	Robert M. Hierons	Comparing test sets and criteria in the presence of test hypotheses and fault domains.	ACM Trans. Softw. Eng. Methodol.	2002	DBLP DOI BibTeX RDF
35	Irith Pomeranz, Sudhakar M. Reddy	On n-detection test sets and variable n-detection test sets fortransition faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
35	Irith Pomeranz, Sudhakar M. Reddy	On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.	VTS	1999	DBLP DOI BibTeX RDF
35	Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy	Resource-Constrained Compaction of Sequential Circuit Test Sets.	VLSI Design	2000	DBLP DOI BibTeX RDF
34	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I2L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
34	Uwe Sparmann, Holger Müller, Sudhakar M. Reddy	Minimal Delay Test Sets for Unate Gate Networks.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
34	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Systematic Scan Reconfiguration.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains
33	Soo Young Lee, Kewal K. Saluja	Test application time reduction for sequential circuits with scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
33	Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman	z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
31	James D. McCaffrey	Generation of Pairwise Test Sets Using a Genetic Algorithm.	COMPSAC (1)	2009	DBLP DOI BibTeX RDF
31	Stelios Neophytou, Maria K. Michael	On the Relaxation of n-detect Test Sets.	VTS	2008	DBLP DOI BibTeX RDF	N-detect, test set relaxation
31	Irith Pomeranz, Sudhakar M. Reddy	Test sequences to achieve high defect coverage for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
31	Dan Zhao 0001, Shambhu J. Upadhyaya, Martin Margala	Minimizing concurrent test time in SoC's by balancing resource usage.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	resource balancing, system-on-a-chip test scheduling, test sets selection
31	Phyllis G. Frankl, Stewart N. Weiss	An Experimental Comparison of the Effectiveness of Branch Testing and Data Flow Testing.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	error exposing ability, all-edges test data adequacy criteria, software testing experiments, executable edges, definition-use associations, all-uses adequate test sets, program testing, errors, regression analysis, data flow testing, branch testing
31	Warren H. Debany Jr., Carlos R. P. Hartmann	Bounds on the sizes of irredundant test sets and sequences for combinational logic networks.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Digital logic testing, irredundant tests, test complexity, test counting
31	Zhanglei Wang, Krishnendu Chakrabarty	Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
31	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On the effects of test compaction on defect coverage.	VTS	1996	DBLP DOI BibTeX RDF	surrogate faults, fault diagnosis, test generation, integrated circuit testing, fault modeling, test sets, test compaction, defect coverage
30	Irith Pomeranz	N-detection under transparent-scan.	DAC	2005	DBLP DOI BibTeX RDF	test generation, scan design, n-detection test sets
30	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Thermal-aware testing, Test scheduling, SoC testing
30	Dieter Hofbauer, Maria Huber	Test Sets for the Universal and Existential Closure of Regular Tree Languages.	RTA	1999	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Sudhakar M. Reddy	A Measure of Quality for n-Detection Test Sets.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	n-detection tests, test set ordering, unmodeled faults
29	Paul Ammann, Paul E. Black	A Specification-Based Coverage Metric to Evaluate Test Sets.	HASE	1999	DBLP DOI BibTeX RDF	Model Checking, Formal Specification, Coverage, Test Sets, SCR, Test Metric, SMV
29	Irith Pomeranz, Sudhakar M. Reddy	On test data compression and n-detection test sets.	DAC	2003	DBLP DOI BibTeX RDF	test generation, test data compression, n-detection test sets
29	Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra	ELF-Murphy Data on Defects and Test Sets.	VTS	2004	DBLP DOI BibTeX RDF
29	Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy	Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Sudhakar M. Reddy	Partitioned n-detection test generation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault partitioning, test generation, stuck-at faults, bridging faults, n-detection test sets
29	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	DFT	2006	DBLP DOI BibTeX RDF
28	Li Chen, Sujit Dey	Software-based self-testing methodology for processor cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
28	Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng	Embedded hardware and software self-testing methodologies for processor cores.	DAC	2000	DBLP DOI BibTeX RDF
28	Sarah Salahuddin	Analysing the Impact of Change on Test Sets Using X-Machines.	ICSM	2007	DBLP DOI BibTeX RDF
27	Indradeep Ghosh, Srivaths Ravi 0001	On automatic generation of RTL validation test benches using circuit testing techniques.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	OCCOM, RTL ATPG, RTL testing, path coverage, small validation, toggle coverage, test, testing, generation, ATPG, fault coverage, code coverage, test sets, design validation, coverage metrics, universal test sets, testbench, branch coverage
27	Anshuman Chandra, Krishnendu Chakrabarty	Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	decompression architecture, precomputed test sets, test set encoding, system-on-a-chip test, variable-to-variable-length codes, Automatic test equipment (ATE), embedded core testing
26	Irith Pomeranz, Sudhakar M. Reddy	Forming N-detection test sets from one-detection test sets without test generation.	ITC	2005	DBLP DOI BibTeX RDF
26	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Sudhakar M. Reddy	Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.	ISQED	2003	DBLP DOI BibTeX RDF
26	Irith Pomeranz, Sudhakar M. Reddy	On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.	ICCD	2000	DBLP DOI BibTeX RDF
26	W. Eric Wong, Joseph Robert Horgan, Aditya P. Mathur, Alberto Pasquini	Test Set Size Minimization and Fault Detection Effectiveness: A Case Study in a Space Application.	COMPSAC	1997	DBLP DOI BibTeX RDF	Block coverage, test set minimization, null hypothesis, fault detection effectiveness
26	Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy	MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.	VLSI Design	1995	DBLP DOI BibTeX RDF	MUSTC-testing, multi-stage-combinational test, control paths, signal types, module level pre-computed test sets, scheduling, logic testing, integrated circuit testing, combinational circuits, automatic testing, automatic test, register-transfer level, test scheduling, data-paths
25	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Multiple Full-Scan Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
25	Chih-Ang Chen, Sandeep K. Gupta	Efficient BIST TPG design and test set compaction via input reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
25	Jeanne Tongbong, Salvador Mir, Jean-Louis Carbonéro	Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model.	DATE	2007	DBLP DOI BibTeX RDF
25	Julien Pouget, Erik Larsson, Zebo Peng	Multiple-Constraint Driven System-on-Chip Test Time Optimization.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	wrapper and TAM design, test scheduling, SOC testing, power constraint, multiple constraints
25	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Hierarchical test generation and design for testability methods for ASPPs and ASIPs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
24	Larry J. Morell, Branson W. Murrill	Using Perturbation Analysis to Measure Variation in the Information Content of Test Sets.	ISSTA	1996	DBLP DOI BibTeX RDF
24	Juhani Karhumäki, Wojciech Rytter, Stefan Jarominek	Efficient Constructions of Test Sets for Regular and Context-Free Languages.	MFCS	1991	DBLP DOI BibTeX RDF
24	Joseph L. A. Hughes	Multiple fault detection using single fault test sets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Worst-Case and Average-Case Analysis of n-Detection Test Sets.	DATE	2005	DBLP DOI BibTeX RDF
24	Dimitrios Kagaris, Spyros Tragoudas	Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Static compaction for two-pattern test sets.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
24	Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz	The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	minimum test sets, monotone combinational circuits, minimum complete test set, monotone PLAs, computational complexity, complexity, logic testing, NP-complete, logic arrays, combinatorial circuits, literals
24	Irith Pomeranz, Sudhakar M. Reddy	On Generating Test Sets that Remain Valid in the Presence of Undetected Faults.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
23	Kyoung Youn Cho, Edward J. McCluskey	Test Set Reordering Using the Gate Exhaustive Test Metric.	VTS	2007	DBLP DOI BibTeX RDF
23	Zhiyuan He 0002, Zebo Peng, Petru Eles	Power constrained and defect-probability driven SoC test scheduling with test set partitioning.	DATE	2006	DBLP DOI BibTeX RDF
23	Gang Zeng, Hideo Ito	Concurrent core test for SOC using shared test set and scan chain disable.	DATE	2006	DBLP DOI BibTeX RDF
23	Anand Raghunathan, Srimat T. Chakradhar	Acceleration techniques for dynamic vector compaction.	ICCAD	1995	DBLP DOI BibTeX RDF	Dynamic equivalent and untestable fault analysis, Target fault switching, Support sets, Test compaction, Acceleration Techniques
23	Uwe Sparmann, Holger Müller, Sudhakar M. Reddy	Universal delay test sets for logic networks.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
23	Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko	On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
23	Silvia Regina Vergilio, José Carlos Maldonado, Mário Jino	Constraint Based Selection of Test Sets to Satisfy Structural Software Testing Criteria.	SCCC	1997	DBLP DOI BibTeX RDF	constraint based selection, structural software testing criteria, Constraint Based Criteria, distinct fundamentals, test data generation strategies, test data set adequacy, program testing
22	Man Fai Lau, Yuen-Tak Yu	On Comparing Testing Criteria for Logical Decisions.	Ada-Europe	2009	DBLP DOI BibTeX RDF	condition coverage, condition/decision coverage, control flow criteria, decision coverage, modified condition/ decision coverage (MC/DC), software testing, Boolean expression
22	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams	Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.	ITC	2002	DBLP DOI BibTeX RDF
22	Irith Pomeranz, Sudhakar M. Reddy	Test enrichment for path delay faults using multiple sets of target faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
22	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
22	Gang Zeng, Hideo Ito	Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree.	ICCD	2005	DBLP DOI BibTeX RDF
22	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	A framework for testing core-based systems-on-a-chip.	ICCAD	1999	DBLP DOI BibTeX RDF
21	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
21	Raymond Hemmecke	On the positive sum property and the computation of Graver test sets.	Math. Program.	2003	DBLP DOI BibTeX RDF
21	R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah	Analyzing the Effectiveness of Multiple-Detect Test Sets.	ITC	2003	DBLP DOI BibTeX RDF
21	Klaus Schmid, Roland Fettig	Towards an Efficient Construction of Test Sets for Deciding Ground Reducability.	RTA	1995	DBLP DOI BibTeX RDF
21	Peter C. Maxwell, Hans-Joachim Wunderlich	The effectiveness of different test sets for PLAs.	EURO-DAC	1990	DBLP DOI BibTeX RDF
21	Luc Bougé, N. Choquet, Laurent Fribourg, Marie-Claude Gaudel	Application of Prolog to Test Sets Generation from Algebraic Specifications.	TAPSOFT, Vol.2	1985	DBLP DOI BibTeX RDF
21	Supaporn Kansomkeat, Jeff Offutt, Aynur Abdurazik, Andrea Baldini	A Comparative Evaluation of Tests Generated from Different UML Diagrams.	SNPD	2008	DBLP DOI BibTeX RDF	Software Testing, Model-based Testing, UML Diagram
21	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.	DFT	2005	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	Generation of broadside transition fault test sets that detect four-way bridging faults.	DATE	2006	DBLP DOI BibTeX RDF
21	Fevzi Belli, Christof J. Budnik	Towards Minimization of Test Sets for Human-Computer Systems.	IEA/AIE	2005	DBLP DOI BibTeX RDF
21	Grégoire Hamon, Leonardo Mendonça de Moura, John M. Rushby	Generating Efficient Test Sets with a Model Checker.	SEFM	2004	DBLP DOI BibTeX RDF
21	Irith Pomeranz, Sudhakar M. Reddy	On n-detection test sequences for synchronous sequential circuits343.	VTS	1997	DBLP DOI BibTeX RDF	n-detection test sequences, stuck-at fault detection, test generation procedures, logic testing, fault simulation, synchronous sequential circuits, defect coverages
21	Heng Li, Jin-Song Liu, Zhao Xu, Jiao Jin, Lin Fang, Lei Gao, Yu-Dong Li, Zi-Xing Xing, Shao-Gen Gao, Tao Liu, Hai-Hong Li, Yan Li, Li-Jun Fang, Hui-Min Xie, Wei-Mou Zheng, Bailin Hao	Test Data Sets and Evaluation of Gene Prediction Programs on the Rice Genome.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	rice genome, accuracy measures, dynamic programming, hidden Markov models, test sets, gene prediction
21	Stewart N. Weiss, Elaine J. Weyuker	An Extended Domain-Bases Model of Software Reliability.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	extended domain-based model, tolerance function, probability function, operational input distribution, probability, software reliability, software reliability, program verification, program testing, correctness, programming theory, test sets
21	Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir	Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach.	DATE	2005	DBLP DOI BibTeX RDF
21	Yuen-Tak Yu, Man Fai Lau, Tsong Yueh Chen	Using the Incremental Approach to Generate Test Sets: A Case Study.	QSIC	2003	DBLP DOI BibTeX RDF	Empirical study, test case generation, specification-based testing, partition testing, fault-based testing
21	Shivakumar Swaminathan, Krishnendu Chakrabarty	On Using Twisted-Ring Counters for Test Set Embedding in BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	non-intrusive testing, scalable BIST, test-per-clock, reseeding, deterministic BIST
21	Seiji Kajihara, Kewal K. Saluja	On Test Pattern Compaction Using Random Pattern Fault Simulation.	VLSI Design	1998	DBLP DOI BibTeX RDF	test generation, combinational circuit, fault simulation, stuck-at fault, test compaction
21	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.	VLSI Design	2003	DBLP DOI BibTeX RDF
21	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
21	Roy S. Freedman	Testability of Software Components.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	domain testability, domain-testable program, input-output inconsistencies, small test sets, test outputs, domain-testable specification, nondomain-testable specification, formal specification, controllability, software components, program testing, observability, program specifications
20	Shih-Ping Lin 0001, Chung-Len Lee 0001, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu	A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
20	Ahmad A. Al-Yamani, Edward J. McCluskey	Test chip experimental results on high-level structural test.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test experiment, Structural test, VLSI test, complex gates
20	Stuart McCracken, Zeljko Zilic	Design for Testability of FPGA Blocks.	ISQED	2004	DBLP DOI BibTeX RDF
20	Irith Pomeranz, Sudhakar M. Reddy	Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF