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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 72 publication records. Showing 72 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | Hari Ananthan, Kaushik Roy 0001 |
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 413-418, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage distribution, multiple-gate, tri-gate, process variations, finFET, double-gate |
31 | Himanshu Kaul, Mark A. Anders 0001, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy 0001 |
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(4), pp. 1048-1058, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
31 | Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De |
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8682-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
31 | Chia-Hong Jan, F. Al-amoody, H.-Y. Chang, T. Chang, Y.-W. Chen, N. Dias, Walid M. Hafez, Doug B. Ingerly, M. Jang, Eric Karl, S. K.-Y. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C.-G. Lee, J. Lee, T. Leo, P.-C. Liu, N. Nidhi, R. Olac-vaw, C. Petersburg, K. Phoa, Chetan Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, Aravinth Subramaniam, C. Tsai, Peter Vandervoorn, L. Yang, A. Zainuddin, Peng Bai |
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015, pp. 12-, 2015, IEEE, 978-4-86348-502-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
31 | Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders 0001, Gregory K. Chen, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014, pp. 1-2, 2014, IEEE, 978-1-4799-3327-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
31 | Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold |
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: Proceedings of the 2012 European Solid-State Device Research Conference, ESSDERC 2012, Bordeaux, France, September 17-21, 2012, pp. 73-76, 2012, IEEE, 978-1-4673-1707-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
31 | Dick James |
Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k, metal-gate CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, pp. 1-4, 2012, IEEE, 978-1-4673-1555-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | K. Joshi, D. Nminibapiel, M. Ghoneim, D. Ali, R. Ramamurthy, L. Pantisano, Inanc Meric, Stephen Ramey |
A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Swagat Nanda, Rudra Sankar Dhar |
Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 98, pp. 107687, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | D. Nminibapiel, K. Joshi, R. Ramamurthy, L. Pantisano, Inanc Meric, Stephen Ramey |
Method to evaluate off-state breakdown in scaled Tri-gate technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2022, Dallas, TX, USA, March 27-31, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-7950-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta |
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022, pp. 292-296, 2022, IEEE, 978-1-6654-8505-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | M. Prasad, U. B. Mahadevaswamy |
Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 118(1), pp. 619-630, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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22 | Sourav De, Md. Aftab Baig, Bo-Han Qiu, Darsen D. Lu, Po-Jung Sung, Fu. K. Hsueh, Yao-Jen Lee, Chun-Jung Su |
Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: 2020 Device Research Conference, DRC 2020, Columbus, OH, USA, June 21-24, 2020, pp. 1-2, 2020, IEEE, 978-1-7281-7047-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan 0002, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De |
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(1), pp. 144-157, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram K. Krishnamurthy, Vivek De |
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(4), pp. 1074-1085, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Gerhard Schrom, Sarath Makala, Ravi Sankar Vunnam, Raghuraman Narayanan, Fabrice Paillet |
A Low-Latency 16-Phase Pulse Width Modulator with Phase Angle Control for 140MHz Fully Integrated Voltage Regulators on 22nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019, Dallas, TX, USA, August 4-7, 2019, pp. 513-516, 2019, IEEE, 978-1-7281-2788-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar 0001, Rinkle Jain, Sheldon Weng, Stephen T. Kim, George E. Matthew, Nachiket V. Desai, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De |
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(1), pp. 8-19, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Harish Kumar Krishnamurthy, Sheldon Weng, George E. Matthew, Nachiket V. Desai, Ruchir Saraswat, Krishnan Ravichandran, James W. Tschanz, Vivek De |
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(4), pp. 1038-1048, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Yali Su, Junhua Lai, Feng Liang |
The impact of heat loss paths on the electrothermal models of self-heating effects in nanoscale tri-gate SOI MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(24), pp. 20180905, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Yoko Yoshimura, Kensuke Ota, Masumi Saitoh |
Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 5, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Kam Krisnnamurthy |
34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018, pp. 90-93, 2018, IEEE, 978-1-5386-5404-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018, pp. 98-101, 2018, IEEE, 978-1-5386-5404-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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22 | Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao 0002, Santosh Ghosh, Rafael Misoczki, Ankit Gupta 0011, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De |
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 46-48, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan 0002, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De |
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018, pp. 38-40, 2018, IEEE, 978-1-5090-4940-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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22 | Mark A. Anders 0001, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 39-40, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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22 | Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, pp. 175-176, 2018, IEEE, 978-1-5386-4214-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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22 | Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, pp. 263-266, 2018, IEEE, 978-1-5386-6413-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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22 | Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De |
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 52(4), pp. 961-971, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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22 | Azzedin D. Es-Sakhi, Masud H. Chowdhury |
Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 62, pp. 30-37, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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22 | Ramnarayanan Muthukaruppan, Tarun Mahajan, Harish Kumar Krishnamurthy, Sumedha Mangal, Am Dhanashekar, Rupak Ghayal, Vivek De |
A digitally controlled linear regulator for per-core wide-range DVFS of atom™ cores in 14nm tri-gate CMOS featuring non-linear control, adaptive gain and code roaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, September 11-14, 2017, pp. 275-278, 2017, IEEE, 978-1-5090-5025-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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22 | Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar 0001, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De |
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017, pp. 336-337, 2017, IEEE, 978-1-5090-3758-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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22 | Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De |
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(1), pp. 117-129, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang 0001 |
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(4), pp. 1003-1008, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd |
A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 51(2), pp. 378-390, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Chika Tanaka, Masumi Saitoh, Kensuke Ota, Takayuki Ishikawa, Toshinori Numata |
BSIM4 parameter extraction for tri-gate Si nanowire transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 47, pp. 1-6, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Mohamed Alsharef, Ralf Granzner, Frank Schwierz, Erdin Ture, Rüdiger Quay, Oliver Ambacher |
Performance of tri-gate AlGaN/GaN HEMTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, September 12-15, 2016, pp. 176-179, 2016, IEEE, 978-1-5090-2969-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Himanshu Kaul, Mark A. Anders 0001, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001 |
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, San Francisco, CA, USA, January 31 - February 4, 2016, pp. 260-261, 2016, IEEE, 978-1-4673-9466-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Amit Agarwal 0001, Steven Hsu, Mark A. Anders 0001, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy 0001 |
A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy 0001, Vivek De |
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De |
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy 0001 |
250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Circuits ![In: 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016, pp. 1-2, 2016, IEEE, 978-1-5090-0635-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders 0001, Gregory K. Chen, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De |
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016, pp. 253-256, 2016, IEEE, 978-1-5090-3699-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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22 | Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, Dror Zilberman |
Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(3), pp. 799-807, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang 0001 |
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 150-157, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Gregory K. Chen, Mark A. Anders 0001, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal 0001, Ram Krishnamurthy 0001, Vivek De, Shekhar Borkar |
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 59-67, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, Krishnan Ravichandran, James W. Tschanz, Vivek De |
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(8), pp. 1809-1819, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Steven R. Novak, C. Parker, D. Becher, M. Liu, Marty Agostinelli, M. Chahal, P. Packan, P. Nayak, Stephen Ramey, S. Natarajan |
Transistor aging and reliability in 14nm tri-gate technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 2, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Norbert Seifert, Shah M. Jahinuzzaman, Jyothi Velamala, Nikunj Patel |
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 2, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Pavan Kumar 0001, Vaibhav A. Vaidya, Harish Krishnamurthy, Stephen T. Kim, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De |
A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8682-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De |
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Rajeev K. Dokania, Alexandra M. Kern, Mike He, Adam C. Faust, Richard Tseng, Skyler Weaver, Kai Yu 0016, Christiaan Bil, Tao Liang, Frank O'Mahony |
10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang 0001 |
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015, pp. 174-, 2015, IEEE, 978-4-86348-502-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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22 | Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De |
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 49(4), pp. 917-927, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Jae Hoon Lee, Jong Tae Park 0003 |
Crystallographic-orientation-dependent GIDL current in Tri-gate MOSFETs under hot carrier stress. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(9-10), pp. 2315-2318, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Sudhir Satpathy, Sanu Mathew, Jiangtao Li 0001, Patrick Koeberl, Mark A. Anders 0001, Himanshu Kaul, Gregory K. Chen, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014, pp. 239-242, 2014, IEEE, 978-1-4799-5694-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, James W. Tschanz, Krishnan Ravichandran, Vivek De |
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, San Jose, CA, USA, September 15-17, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang 0001 |
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 230-231, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Gregory K. Chen, Mark A. Anders 0001, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal 0001, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De |
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 276-277, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Mesut Meterelliyoz, Fuad H. Al-amoody, Umut Arslan, Fatih Hamzaoglu, Luke Hood, Manoj B. Lal, Jeffrey L. Miller, Anand Ramasundar, Dan Soltman, Ifar Wan, Yih Wang, Kevin Zhang 0001 |
2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014, pp. 1-2, 2014, IEEE, 978-1-4799-3327-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Harish Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar 0001, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De |
A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014, pp. 1-2, 2014, IEEE, 978-1-4799-3327-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Andrew Marshall |
T4A: System-on-chip design using Tri-gate technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014, pp. xliii, 2014, IEEE, 978-1-4799-3378-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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22 | Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane 0001, Uddalak Bhattacharya, Kevin Zhang 0001, Kaizad Mistry, Mark Bohr |
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(1), pp. 150-158, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Steven Hsu, Amit Agarwal 0001, Mark A. Anders 0001, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy |
A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 48(1), pp. 118-127, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
22 | Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Gérard Ghibaudo, Hiroshi Iwai, Gilles Reimbold |
Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: Proceedings of the European Solid-State Device Research Conference, ESSDERC 2013, Bucharest, Romania, September 16-20, 2013, pp. 300-303, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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22 | Amit Agarwal 0001, Steven Hsu, Sanu Mathew, Mark A. Anders 0001, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy 0001 |
A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012, pp. 177-180, 2012, IEEE, 978-1-4673-2212-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Chris Auth |
22-nm fully-depleted tri-gate CMOS transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012, pp. 1-6, 2012, IEEE, 978-1-4673-1555-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Y. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath |
A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 70-72, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang 0001, Kaizad Mistry, Mark Bohr |
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012, pp. 230-232, 2012, IEEE, 978-1-4673-0376-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Zoran Jaksic, Ramon Canal |
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012, pp. 309-314, 2012, IEEE Computer Society, 978-1-4673-3051-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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22 | Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu |
Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 270-274, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
22 | Junha Lee, Hanwool Jeong, Younghwi Yang, Jisu Kim, Seong-Ook Jung |
Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2012, Jeju Island, South Korea, November 4-7, 2012, pp. 479-482, 2012, IEEE, 978-1-4673-2989-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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