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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 159 occurrences of 109 keywords
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Results
Found 457 publication records. Showing 457 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
47 | Gregory Lucas, Chen Dong 0003, Deming Chen |
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 177-180, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis |
47 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 148-151, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis |
42 | Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001 |
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1253-1263, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie 0001, Narayanan Vijaykrishnan |
Variation-aware task allocation and scheduling for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 598-603, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Tarek A. El-Moselhy, Luca Daniel |
Stochastic dominant singular vectors method for variation-aware extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 667-672, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
intrusive algorithms, stochastic PDEs, stochastic dominant singular vectors, variation-aware extraction, stochastic simulation, integral equations, surface roughness, parasitic extraction |
39 | Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001 |
Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 195-200, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
significance driven computation, variation aware, voltage over-scaling, low power, motion estimation |
38 | Chen Dong 0003, Scott Chilstedt, Deming Chen |
FPCNA: a field programmable carbon nanotube array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 161-170, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics |
38 | Kanakagiri Raghavendra, Madhu Mutyam |
Process Variation Aware Issue Queue Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1438-1443, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Madhu Mutyam, Narayanan Vijaykrishnan |
Working with process variation aware caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1152-1157, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Lerong Cheng, Jinjun Xiong, Lei He 0001, Mike Hutton |
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001 |
Efficient decoupling capacitance budgeting considering operation and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 803-810, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Tarek Moselhy, Luca Daniel |
Stochastic integral equation solver for efficient variation-aware interconnect extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 415-420, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Neumann expansion, polynomial chaos expansion, stochastic field solvers, variation-aware extraction, surface roughness |
32 | Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy 0001 |
A process variation aware low power synthesis methodology for fixed-point FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 147-152, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fixed-point FIR filters, variation aware, low-power, synthesis |
30 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 426-430, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay |
30 | HaNeul Chon, Taewhan Kim |
Timing variation-aware task scheduling and binding for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 137-142, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Gregory Lucas, Scott Cromar, Deming Chen |
FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 61-66, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 433-438, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun |
Power-efficient variation-aware photonic on-chip network management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 31-36, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
networks on chip, optical interconnects, nanophotonics |
26 | Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah |
Variation-aware performance verification using at-speed structural test and statistical timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 405-412, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002 |
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 222-231, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3D die stacking, NUCA, process variation, DRAM |
26 | Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera |
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 107-112, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VGTA: Variation Aware Gate Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 351-356, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Rasit Onur Topaloglu, Alex Orailoglu |
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 851-856, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Lin Huang 0002, Qiang Xu 0001 |
Performance yield-driven task allocation and scheduling for MPSoCs under process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 326-331, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance yield, process variation, task scheduling |
23 | Feng Wang 0004, Guangyu Sun 0003, Yuan Xie 0001 |
A Variation Aware High Level Synthesis Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1063-1068, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Kumar Yelamarthi, Chien-In Henry Chen |
Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 143-147, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders |
23 | Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas |
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 43-46, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus coding, delay, process variation |
23 | Venkataraman Mahalingam, N. Ranganathan |
Variation Aware Timing Based Placement Using Fuzzy Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 327-332, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Suresh Srinivasan, Narayanan Vijaykrishnan |
Variation Aware Placement for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 422-423, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Ke Meng, Russ Joseph |
Process variation aware cache leakage management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 262-267, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gated-VDD, selective cache ways, low power, process variation, leakage, cache management |
23 | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III |
A novel approach for variation aware power minimization during gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 174-179, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Jae-Seok Yang, Andrew R. Neureuther |
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 352-356, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
worst corner, noise, crosstalk, variation, signal integrity |
22 | Masashi Imai, Takashi Nanya |
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 68-77, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang |
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 39-44, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd |
21 | Patrick McGuinness |
Variations, margins, and statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 60-67, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design margins, process variations, yield, SSTA |
21 | Feng Wang 0004, Yuan Xie 0001 |
Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-5, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi |
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 251-260, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs |
20 | Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik |
Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(11), pp. 1515-1521, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi |
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(4), pp. 630-642, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 519-522, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi |
History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012, pp. 498-505, 2012, IEEE, 978-1-4673-1034-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Maziar Goudarzi, Tohru Ishihara, Hamid Noori |
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 224-239, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
process variation, cache memory, Leakage power, power reduction |
20 | Amit Agarwal 0001, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy 0001 |
Process variation in embedded memories: failure analysis and variation aware architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(9), pp. 1804-1814, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam |
Variation-aware multimetric optimization during gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 54:1-54:30, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise |
19 | Feng Wang 0004, Yuan Xie 0001, Andrés Takach |
Variation-aware resource sharing and binding in behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 79-84, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Satish Sivaswamy, Kia Bazargan |
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 4:1-4:35, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
skew assignment, routing, Statistical timing analysis |
19 | Siddharth Garg, Diana Marculescu |
System-level throughput analysis for process variation aware multiple voltage-frequency island designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 59:1-59:25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
manufacturing process variations, maximum cycle mean, voltage-frequency islands, performance analysis, system-level design, Globally asynchronous locally synchronous |
19 | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
Variation Aware Spline Center and Range Modeling for Analog Circuit Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 162-167, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Center and Range, Process Variation, Analog, Spline |
19 | Satish Sivaswamy, Kia Bazargan |
Variation-aware routing for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 71-79, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
statistical timing analysis, FPGA routing |
19 | Ning Lu, Judy H. McCullen |
Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 743-748, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | LuÃs Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira |
Variation-Aware, Library Compatible Delay Modeling Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 122-127, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Peng Yu, Sean X. Shi, David Z. Pan |
Process variation aware OPC with variational lithography modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 785-790, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
lithography modeling, process variation, OPC |
18 | Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu |
Transistor sizing of custom high-performance digital circuits with parametric yield considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 781-786, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
custom circuits, optimization |
18 | Xin Fu, Tao Li 0006, José A. B. Fortes |
NBTI tolerant microarchitecture design in the presence of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 399-410, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001 |
Variability-driven module selection with joint design time optimization and post-silicon tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 2-9, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Temperature and Process Variations Aware Power Gating of Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 515-520, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Power Reduction of Functional Units Considering Temperature and Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 533-539, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Sayed Taha Muhammad, Mohamed Saad 0001, Ali A. El-Moursy, Magdy A. El-Moursy, Hesham F. A. Hamed |
CFPA: Congestion aware, fault tolerant and process variation aware adaptive routing algorithm for asynchronous Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Parallel Distributed Comput. ![In: J. Parallel Distributed Comput. 128, pp. 151-166, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
15 | Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy 0001 |
Coping with Variations through System-Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 581-586, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Wei-Lun Hung, Xiaoxia Wu, Yuan Xie 0001 |
Guaranteeing performance yield in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 303-309, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
System-on-Chip Power Management Considering Leakage Power Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 877-882, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jinjun Xiong, Lei He 0001 |
Fast buffer insertion considering process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 128-135, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pruning rule, dynamic programming, process variation, transitive closure, buffer insertion |
14 | Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan |
TSV stress aware timing analysis with applications to 3D-IC layout optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 803-806, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
mobility variation, timing analysis, stress, TSV, 3DIC |
14 | David Z. Pan |
Synergistic modeling and optimization for nanometer IC design/manufacturing integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 2, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design for manufacturing |
12 | Fatemeh Khodayari, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri |
Low-Cost and Variation-Aware Spintronic Ternary Random Number Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 43(2), pp. 1175-1191, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Chao Wang 0094, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang |
Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1651-1664, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Inseong Jeon, Hyunho Park, Taehwan Yoon, Hanwool Jeong |
High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(3), pp. 1391-1395, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Abdullah Giray Yaglikçi, Yahya Can Tugrul, Geraldo F. Oliveira, Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, Onur Mutlu |
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2402.18652, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Abdullah Giray Yaglikçi, Yahya Can Tugrul, Geraldo F. Oliveira, Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, Onur Mutlu |
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High-Performance Computer Architecture, HPCA 2024, Edinburgh, United Kingdom, March 2-6, 2024, pp. 560-577, 2024, IEEE, 979-8-3503-9313-2. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
12 | Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho |
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(4), pp. 532-542, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Pengcheng Zhu 0002, Weiping Ding 0001, Lihua Wei, Xueyun Cheng, Zhijin Guan, Shiguang Feng |
A Variation-Aware Quantum Circuit Mapping Approach Based on Multi-Agent Cooperation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(8), pp. 2237-2249, August 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Xiaoliu Feng, Xianzhang Chen, Qingfeng Zhuge, Duo Liu, Edwin H.-M. Sha, Chun Jason Xue |
V-WAFA: An Endurance Variation Aware Fine-Grained Allocator for Persistent Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(4), pp. 998-1010, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Divyansh Maura, Tanmay Goel, Kaustav Goswami 0002, Dip Sankar Banerjee, Shirshendu Das |
Variation aware power management for GPU memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 96, pp. 104711, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li 0004, Runsheng Wang, Ru Huang |
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11), pp. 4139-4151, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Hameedah Sultan, Smruti R. Sarangi |
VarSim: A fast process variation-aware thermal modeling methodology using Green's functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 142, pp. 105995, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Tiantian Liu 0003, Zijin Feng, Huan Li 0003, Hua Lu 0001, Muhammad Aamir Cheema, Hong Cheng 0001, Jianliang Xu |
Towards Indoor Temporal-Variation Aware Shortest Path Query. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 35(1), pp. 998-1012, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Liu, Juinn-Dar Huang |
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 28(2), pp. 18:1-18:22, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Mingle Xu, Jaehwan Lee, Sook Yoon, Hyongsuk Kim, Dong Sun Park |
Variation-Aware Semantic Image Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2301.10551, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Hameedah Sultan, Smruti R. Sarangi |
VarSim: A Fast Process Variation-aware Thermal Modeling Methodology Using Green's Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2307.12119, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Xijie Huang, Zhiqiang Shen, Kwang-Ting Cheng |
Variation-aware Vision Transformer Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2307.00331, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Octavian Pascu, Catalin Visan, Georgian Nicolae, Mihai Boldeanu, Horia Cucu, Cristian Diaconu, Andi Buzo, Georg Pelz |
Efficient Multi-Objective Optimization for PVT Variation-Aware Circuit Sizing Using Surrogate Models and Smart Corner Sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023, Vienna, Austria, August 7-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-1175-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Kyungmin Lee, Jaehong Jung, Gyusik Kim, Joomyoung Kim, Seungjin Kim, Seunghyun Oh, Sung Min Park 0001, Jongwoo Lee |
A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023, pp. 1-3, 2023, IEEE, 979-8-3503-3003-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Sai Shubham, Shubham Pandit, Kailash Prasad, Joycee Mekie |
PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
12 | Lei Zhang 0195, Na Jiang, Qishuai Diao, Zhong Zhou, Wei Wu 0008 |
Person Re-identification with pose variation aware data augmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 34(14), pp. 11817-11830, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski |
A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(6), pp. 1684-1699, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Jinkui Hao, Fei Li, Huaying Hao, Huazhu Fu, Yanwu Xu 0001, Risa Higashita, Xiulan Zhang, Jiang Liu 0001, Yitian Zhao |
Hybrid Variation-Aware Network for Angle-Closure Assessment in AS-OCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Medical Imaging ![In: IEEE Trans. Medical Imaging 41(2), pp. 254-265, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Lalit Mohan Dani, Neeraj Mishra, Bulusu Anand |
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(3), pp. 1557-1561, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Yi Wang 0003, Jiangfan Huang, Jing Chen, Rui Mao 0001 |
PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5), pp. 1302-1315, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Wei Shi, Hanrui Wang 0002, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han 0003, Nan Sun 0001 |
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.06412, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Kaustav Goswami 0002, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee |
VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2201.06853, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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12 | Sunanda Thunder, Po-Tsang Huang |
Variation Aware Training of Hybrid Precision Neural Networks with 28nm HKMG FeFET Based Synaptic Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2202.10912, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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12 | Arkadiy Dushatskiy, Gerry Lowe, Peter A. N. Bosman, Tanja Alderliesten |
Data variation-aware medical image segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2202.12099, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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12 | Liang Shi, Yina Lv, Longfei Luo, Changlong Li, Chun Jason Xue, Edwin H.-M. Sha |
Read latency variation aware performance optimization on high-density NAND flash based storage systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCF Trans. High Perform. Comput. ![In: CCF Trans. High Perform. Comput. 4(3), pp. 265-280, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu |
Process variation aware DRAM-Cache resizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 123, pp. 102364, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
12 | Arkadiy Dushatskiy, Gerry Lowe, Peter A. N. Bosman, Tanja Alderliesten |
Data variation-aware medical image segmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Medical Imaging: Image Processing ![In: Medical Imaging 2022: Image Processing, San Diego, CA, USA, February 20-24, 2022 / Online, March 21-27, 2022, 2022, SPIE, 9781510649392. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Shamiul Alam, Md. Mazharul Islam 0006, Akhilesh Jaiswal 0001, Nathaniel C. Cady, Garrett S. Rose, Ahmedullah Aziz |
Variation-aware Design Space Exploration of Mott Memristor-based Neuristors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022, pp. 68-73, 2022, IEEE, 978-1-6654-6605-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou |
Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang |
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 80-85, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Wei Shi, Hanrui Wang 0002, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han 0003, Nan Sun 0001 |
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLCAD ![In: 2022 ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2022, Virtual Event, China, September 12-13, 2022, pp. 35-41, 2022, ACM / IEEE, 978-1-4503-9486-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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12 | Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001 |
Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022, pp. 24:1-24:6, 2022, ACM, 978-1-4503-9354-6. The full citation details ...](Pics/full.jpeg) |
2022 |
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