Search results for "variation-aware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
47	Seyed-Abdollah Aftabjahani, Linda S. Milor	Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.	ISQED	2008	DBLP DOI BibTeX RDF	Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis
42	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
40	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie 0001, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
39	Tarek A. El-Moselhy, Luca Daniel	Stochastic dominant singular vectors method for variation-aware extraction.	DAC	2010	DBLP DOI BibTeX RDF	intrusive algorithms, stochastic PDEs, stochastic dominant singular vectors, variation-aware extraction, stochastic simulation, integral equations, surface roughness, parasitic extraction
39	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001	Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator.	ISLPED	2009	DBLP DOI BibTeX RDF	significance driven computation, variation aware, voltage over-scaling, low power, motion estimation
38	Chen Dong 0003, Scott Chilstedt, Deming Chen	FPCNA: a field programmable carbon nanotube array.	FPGA	2009	DBLP DOI BibTeX RDF	cnt-based lut, discretized ssta, variation aware cad, fpga, nanoelectronics
38	Kanakagiri Raghavendra, Madhu Mutyam	Process Variation Aware Issue Queue Design.	DATE	2008	DBLP DOI BibTeX RDF
37	Madhu Mutyam, Narayanan Vijaykrishnan	Working with process variation aware caches.	DATE	2007	DBLP DOI BibTeX RDF
37	Lerong Cheng, Jinjun Xiong, Lei He 0001, Mike Hutton	FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.	FPL	2006	DBLP DOI BibTeX RDF
34	Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001	Efficient decoupling capacitance budgeting considering operation and process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
32	Tarek Moselhy, Luca Daniel	Stochastic integral equation solver for efficient variation-aware interconnect extraction.	DAC	2008	DBLP DOI BibTeX RDF	Neumann expansion, polynomial chaos expansion, stochastic field solvers, variation-aware extraction, surface roughness
32	Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy 0001	A process variation aware low power synthesis methodology for fixed-point FIR filters.	ISLPED	2007	DBLP DOI BibTeX RDF	fixed-point FIR filters, variation aware, low-power, synthesis
30	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay
30	HaNeul Chon, Taewhan Kim	Timing variation-aware task scheduling and binding for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
30	Gregory Lucas, Scott Cromar, Deming Chen	FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
30	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.	VLSI Design	2009	DBLP DOI BibTeX RDF
26	Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun	Power-efficient variation-aware photonic on-chip network management.	ISLPED	2010	DBLP DOI BibTeX RDF	networks on chip, optical interconnects, nanophotonics
26	Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah	Variation-aware performance verification using at-speed structural test and statistical timing.	ICCAD	2007	DBLP DOI BibTeX RDF
26	Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
26	Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
26	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VGTA: Variation Aware Gate Timing Analysis.	ICCD	2005	DBLP DOI BibTeX RDF
26	Rasit Onur Topaloglu, Alex Orailoglu	A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.	DAC	2005	DBLP DOI BibTeX RDF
26	Lin Huang 0002, Qiang Xu 0001	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
23	Feng Wang 0004, Guangyu Sun 0003, Yuan Xie 0001	A Variation Aware High Level Synthesis Framework.	DATE	2008	DBLP DOI BibTeX RDF
23	Kumar Yelamarthi, Chien-In Henry Chen	Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic.	ISQED	2008	DBLP DOI BibTeX RDF	binary-to-thermometer decoder, process variations, timing optimization, transistor sizing, dynamic circuits, binary adders
23	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
23	Venkataraman Mahalingam, N. Ranganathan	Variation Aware Timing Based Placement Using Fuzzy Programming.	ISQED	2007	DBLP DOI BibTeX RDF
23	Suresh Srinivasan, Narayanan Vijaykrishnan	Variation Aware Placement for FPGAs.	ISVLSI	2006	DBLP DOI BibTeX RDF
23	Ke Meng, Russ Joseph	Process variation aware cache leakage management.	ISLPED	2006	DBLP DOI BibTeX RDF	gated-VDD, selective cache ways, low power, process variation, leakage, cache management
23	Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III	A novel approach for variation aware power minimization during gate sizing.	ISLPED	2006	DBLP DOI BibTeX RDF
22	Jae-Seok Yang, Andrew R. Neureuther	Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.	ISQED	2008	DBLP DOI BibTeX RDF	worst corner, noise, crosstalk, variation, signal integrity
22	Masashi Imai, Takashi Nanya	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.	ASYNC	2006	DBLP DOI BibTeX RDF
22	Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
21	Patrick McGuinness	Variations, margins, and statistics.	ISPD	2008	DBLP DOI BibTeX RDF	design margins, process variations, yield, SSTA
21	Feng Wang 0004, Yuan Xie 0001	Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.	IPDPS	2008	DBLP DOI BibTeX RDF
20	Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).	CASES	2009	DBLP DOI BibTeX RDF	low power memory organization, memory organization., remapping cache, variation aware cache, fault tolerance, low power design, low power cache, vfs
20	Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik	Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
20	Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi	Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
20	Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung	A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.	FPL	2012	DBLP DOI BibTeX RDF
20	Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi	History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.	ISQED	2012	DBLP DOI BibTeX RDF
20	Maziar Goudarzi, Tohru Ishihara, Hamid Noori	Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.	HiPEAC	2008	DBLP DOI BibTeX RDF	process variation, cache memory, Leakage power, power reduction
20	Amit Agarwal 0001, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy 0001	Process variation in embedded memories: failure analysis and variation aware architecture.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
19	Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam	Variation-aware multimetric optimization during gate sizing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	optimization, delay, power, mathematical programming, Gate sizing, crosstalk noise
19	Feng Wang 0004, Yuan Xie 0001, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
19	Satish Sivaswamy, Kia Bazargan	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	skew assignment, routing, Statistical timing analysis
19	Siddharth Garg, Diana Marculescu	System-level throughput analysis for process variation aware multiple voltage-frequency island designs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	manufacturing process variations, maximum cycle mean, voltage-frequency islands, performance analysis, system-level design, Globally asynchronous locally synchronous
19	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Center and Range, Process Variation, Analog, Spline
19	Satish Sivaswamy, Kia Bazargan	Variation-aware routing for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	statistical timing analysis, FPGA routing
19	Ning Lu, Judy H. McCullen	Enablement of Variation-Aware Timing: Treatment of Parasitic Resistance and Capacitance.	ISQED	2007	DBLP DOI BibTeX RDF
19	Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira	Variation-Aware, Library Compatible Delay Modeling Strategy.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
19	Peng Yu, Sean X. Shi, David Z. Pan	Process variation aware OPC with variational lithography modeling.	DAC	2006	DBLP DOI BibTeX RDF	lithography modeling, process variation, OPC
18	Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu	Transistor sizing of custom high-performance digital circuits with parametric yield considerations.	DAC	2010	DBLP DOI BibTeX RDF	custom circuits, optimization
18	Xin Fu, Tao Li 0006, José A. B. Fortes	NBTI tolerant microarchitecture design in the presence of process variation.	MICRO	2008	DBLP DOI BibTeX RDF
18	Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001	Variability-driven module selection with joint design time optimization and post-silicon tuning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
18	Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Temperature and Process Variations Aware Power Gating of Functional Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Power Reduction of Functional Units Considering Temperature and Process Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Sayed Taha Muhammad, Mohamed Saad 0001, Ali A. El-Moursy, Magdy A. El-Moursy, Hesham F. A. Hamed	CFPA: Congestion aware, fault tolerant and process variation aware adaptive routing algorithm for asynchronous Networks-on-Chip.	J. Parallel Distributed Comput.	2019	DBLP DOI BibTeX RDF
15	Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy 0001	Coping with Variations through System-Level Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
15	Wei-Lun Hung, Xiaoxia Wu, Yuan Xie 0001	Guaranteeing performance yield in high-level synthesis.	ICCAD	2006	DBLP DOI BibTeX RDF
14	Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey	System-on-Chip Power Management Considering Leakage Power Variations.	DAC	2007	DBLP DOI BibTeX RDF
14	Jinjun Xiong, Lei He 0001	Fast buffer insertion considering process variations.	ISPD	2006	DBLP DOI BibTeX RDF	pruning rule, dynamic programming, process variation, transitive closure, buffer insertion
14	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
14	David Z. Pan	Synergistic modeling and optimization for nanometer IC design/manufacturing integration.	SBCCI	2008	DBLP DOI BibTeX RDF	design for manufacturing
12	Fatemeh Khodayari, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri	Low-Cost and Variation-Aware Spintronic Ternary Random Number Generator.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
12	Chao Wang 0094, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang	Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
12	Inseong Jeon, Hyunho Park, Taehwan Yoon, Hanwool Jeong	High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
12	Abdullah Giray Yaglikçi, Yahya Can Tugrul, Geraldo F. Oliveira, Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, Onur Mutlu	Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.	CoRR	2024	DBLP DOI BibTeX RDF
12	Abdullah Giray Yaglikçi, Yahya Can Tugrul, Geraldo F. Oliveira, Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, Onur Mutlu	Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions.	HPCA	2024	DBLP DOI BibTeX RDF
12	Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho	A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
12	Pengcheng Zhu 0002, Weiping Ding 0001, Lihua Wei, Xueyun Cheng, Zhijin Guan, Shiguang Feng	A Variation-Aware Quantum Circuit Mapping Approach Based on Multi-Agent Cooperation.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
12	Xiaoliu Feng, Xianzhang Chen, Qingfeng Zhuge, Duo Liu, Edwin H.-M. Sha, Chun Jason Xue	V-WAFA: An Endurance Variation Aware Fine-Grained Allocator for Persistent Memory.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
12	Divyansh Maura, Tanmay Goel, Kaustav Goswami 0002, Dip Sankar Banerjee, Shirshendu Das	Variation aware power management for GPU memories.	Microprocess. Microsystems	2023	DBLP DOI BibTeX RDF
12	Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li 0004, Runsheng Wang, Ru Huang	AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
12	Hameedah Sultan, Smruti R. Sarangi	VarSim: A fast process variation-aware thermal modeling methodology using Green's functions.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
12	Tiantian Liu 0003, Zijin Feng, Huan Li 0003, Hua Lu 0001, Muhammad Aamir Cheema, Hong Cheng 0001, Jianliang Xu	Towards Indoor Temporal-Variation Aware Shortest Path Query.	IEEE Trans. Knowl. Data Eng.	2023	DBLP DOI BibTeX RDF
12	Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Liu, Juinn-Dar Huang	Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
12	Mingle Xu, Jaehwan Lee, Sook Yoon, Hyongsuk Kim, Dong Sun Park	Variation-Aware Semantic Image Synthesis.	CoRR	2023	DBLP DOI BibTeX RDF
12	Hameedah Sultan, Smruti R. Sarangi	VarSim: A Fast Process Variation-aware Thermal Modeling Methodology Using Green's Functions.	CoRR	2023	DBLP DOI BibTeX RDF
12	Xijie Huang, Zhiqiang Shen, Kwang-Ting Cheng	Variation-aware Vision Transformer Quantization.	CoRR	2023	DBLP DOI BibTeX RDF
12	Octavian Pascu, Catalin Visan, Georgian Nicolae, Mihai Boldeanu, Horia Cucu, Cristian Diaconu, Andi Buzo, Georg Pelz	Efficient Multi-Objective Optimization for PVT Variation-Aware Circuit Sizing Using Surrogate Models and Smart Corner Sampling.	ISLPED	2023	DBLP DOI BibTeX RDF
12	Kyungmin Lee, Jaehong Jung, Gyusik Kim, Joomyoung Kim, Seungjin Kim, Seunghyun Oh, Sung Min Park 0001, Jongwoo Lee	A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS.	A-SSCC	2023	DBLP DOI BibTeX RDF
12	Sai Shubham, Shubham Pandit, Kailash Prasad, Joycee Mekie	PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs.	DAC	2023	DBLP DOI BibTeX RDF
12	Lei Zhang 0195, Na Jiang, Qishuai Diao, Zhong Zhou, Wei Wu 0008	Person Re-identification with pose variation aware data augmentation.	Neural Comput. Appl.	2022	DBLP DOI BibTeX RDF
12	Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski	A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
12	Jinkui Hao, Fei Li, Huaying Hao, Huazhu Fu, Yanwu Xu 0001, Risa Higashita, Xiulan Zhang, Jiang Liu 0001, Yitian Zhao	Hybrid Variation-Aware Network for Angle-Closure Assessment in AS-OCT.	IEEE Trans. Medical Imaging	2022	DBLP DOI BibTeX RDF
12	Lalit Mohan Dani, Neeraj Mishra, Bulusu Anand	A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
12	Yi Wang 0003, Jiangfan Huang, Jing Chen, Rui Mao 0001	PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
12	Wei Shi, Hanrui Wang 0002, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han 0003, Nan Sun 0001	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL.	CoRR	2022	DBLP DOI BibTeX RDF
12	Kaustav Goswami 0002, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee	VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design.	CoRR	2022	DBLP BibTeX RDF
12	Sunanda Thunder, Po-Tsang Huang	Variation Aware Training of Hybrid Precision Neural Networks with 28nm HKMG FeFET Based Synaptic Core.	CoRR	2022	DBLP BibTeX RDF
12	Arkadiy Dushatskiy, Gerry Lowe, Peter A. N. Bosman, Tanja Alderliesten	Data variation-aware medical image segmentation.	CoRR	2022	DBLP BibTeX RDF
12	Liang Shi, Yina Lv, Longfei Luo, Changlong Li, Chun Jason Xue, Edwin H.-M. Sha	Read latency variation aware performance optimization on high-density NAND flash based storage systems.	CCF Trans. High Perform. Comput.	2022	DBLP DOI BibTeX RDF
12	Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu	Process variation aware DRAM-Cache resizing.	J. Syst. Archit.	2022	DBLP DOI BibTeX RDF
12	Arkadiy Dushatskiy, Gerry Lowe, Peter A. N. Bosman, Tanja Alderliesten	Data variation-aware medical image segmentation.	Medical Imaging: Image Processing	2022	DBLP DOI BibTeX RDF
12	Shamiul Alam, Md. Mazharul Islam 0006, Akhilesh Jaiswal 0001, Nathaniel C. Cady, Garrett S. Rose, Ahmedullah Aziz	Variation-aware Design Space Exploration of Mott Memristor-based Neuristors.	ISVLSI	2022	DBLP DOI BibTeX RDF
12	Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou	Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
12	Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang	Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm.	ASP-DAC	2022	DBLP DOI BibTeX RDF
12	Wei Shi, Hanrui Wang 0002, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han 0003, Nan Sun 0001	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL.	MLCAD	2022	DBLP DOI BibTeX RDF
12	Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001	Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator.	ISLPED	2022	DBLP DOI BibTeX RDF