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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 57 occurrences of 39 keywords
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Results
Found 169 publication records. Showing 169 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Charles Hsu |
Future Prospective of Programmable Logic Non-volatile Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | |
Organizing Committee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Hsing-Chung Liang, Le-Quen Tzeng |
Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 15, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa |
MRAM Write Error Categorization with QCKB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 43-48, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | |
Foreword. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Peter Muhmenthaler |
New on-Chip DFT and ATE Features for Efficient Embedded Memory Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | T. A. Gyonjyan, Gurgen Harutunyan, Valery A. Vardanian |
A March-Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 9-14, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jordan Lai |
SRAM Design Techniques for Sub-nano CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Victor Chao-Wei Kuo, Chih-Ming Chao, Chih-Kai Kang, Li-Wei Liu, Tzung-Bin Huang, Liang-Tai Kuo, Shi-Hsien Chen, Houng-Chi Wei, Hann-Ping Hwang, Saysamone Pittikoun |
Detailed Comparisons of Program, Erase and Data Retention Characteristics between P+- and N+-Poly SONOS NAND Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 77-79, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | |
Program Committee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Chih-Yuan Lu |
Non-volatile Semiconductor Memory Technology in Nanotech Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev |
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 55-64, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou |
SRAM Cell Current in Low Leakage Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 65-70, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Pei-Lin Pai |
DRAM Industry Trend. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jia-Lin Wu, Hua-Ching Chien, Chien-Wei Liao, Cheng-Yen Wu, Chih-Yuan Lee, Houng-Chi Wei, Shih-Hsien Chen, Hann-Ping Hwang, Saysamone Pittikoun, Travis Cho, Chin-Hsing Kao |
Comparison of Electrical and Reliability Characteristics of Different Tunnel Oxides in SONOS Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 80-84, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Mohamed Azimane |
High-Quality Memory Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene |
On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 71-76, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Riichiro Shirota |
Roadmap of the Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jyi-Tsong Lin, Mike Chang |
A New 1T DRAM Cell With Enhanced Floating Body Ef. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 23-27, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng |
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 34-42, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, Cheng-Wen Wu |
Fault-Pattern Oriented Defect Diagnosis for Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 3-8, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson |
DDR2 DRAM Output Timing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 49-54, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu |
FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 28-33, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | |
14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![IEEE Computer Society, 0-7695-2572-5 The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
1 | |
Reviewers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Ching-Yuan Lin, Chung-Hung Lin, Chien-Hung Ho, Wei-Wu Liao, Shu-Yueh Lee, Ming-Chou Ho, Shih-Chen Wang, Shih-Chan Huang, Yuan-Tai Lin, Charles Ching-Hsiang Hsu |
Embedded OTP fuse in CMOS logic process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 13-15, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | |
13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![IEEE Computer Society, 0-7695-2313-7 The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
1 | Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Rob Wadsworth |
Impact of stresses on the fault coverage of memory tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 103-108, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Yang-Han Lee, Yih-Guang Jan, Jei-Jung Shen, Shian-Wei Tzeng, Ming-Hsueh Chuang, Jheng-Yao Lin |
DFT architecture for a dynamic fault model of the embedded mask ROM of SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 78-82, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Chin-Long Wey, Meng-Yao Liu, Shaolei Quan |
Reliability enhancement of CMOS SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 146-151, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Matthew J. Breitwisch, Chung Hon Lam, Jeffrey B. Johnson, Steven W. Mittl, Jian W. Zhu |
A novel CMOS compatible embedded nonvolatile memory with zero process adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 9-12, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Kamlesh R. Raiter, Bruce F. Cockburn |
An investigation into three-level ferroelectric memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 38-43, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Shyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang |
A BIRA algorithm for embedded memories with 2D redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 121-126, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang |
FSM-based programmable memory BIST with macro command. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 72-77, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Valerie Lines, Robert McKenzie, Hakjune Oh, Hong-Beom Pyeon, Matthew Dunn, Susan Palapar, Susan Coleman, Peter Nyasulu, Tony Mai, Seanna Pike, John McCready, Jody Defazio, Jin-Ki Kim, Robert Penchuk, Zvika Greenfield, Fredy Lange, Alberto Mandler, Eric C. Jones, Matthew Silverstein |
A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 47-51, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Meng-Yi Wu, Shin-Chang Feng, Ya-Chin King |
A novel single poly-silicon EEPROM using trench floating gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 35-37, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Chung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang |
Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 129-134, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Bruce McGaughy, S. Wünsche, K. K. Hung |
Advanced simulation technology and its application in memory design and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. xv-xx, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai |
Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 16-21, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama |
DFT techniques for memory macro with built-in ECC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 109-114, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Serguei Okhonin, Pierre Fazan, Mark-Eric Jones |
Zero capacitor embedded memory technology for system on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. xxi-xxv, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Jin-Fu Li 0001, Yu-Jane Huang |
An error detection and correction scheme for RAMs with partial-write function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 115-120, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen |
A systematic approach to reducing semiconductor memory test time in mass production. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 97-102, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Simon C. Li, J. P. Su, T.-H. Wu, J. M. Lee, M. F. Shu |
Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 29-34, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Amandeep Singh, Debashish Bose, Sandeep Darisala |
Software based in-system memory test for highly available systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 89-94, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Ching-Hua Hsiao, Ding-Ming Kwai |
Measurement and characterization of 6T SRAM cell current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 140-145, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya |
A programmable built-in self-test for embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 58-63, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Shin-Pao Cheng, Shi-Yu Huang |
A low-power SRAM design using quiet-bitline architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 135-139, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King |
Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 3-8, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee |
A high speed BIST architecture for DDR-SDRAM testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 52-57, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Star Sung, Thomas Chang, Juei Lung Chen |
A nor-type MLC ROM with novel sensing scheme for embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 22-25, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Wei-Lun Wang, Kuen-Jong Lee |
A complete memory address generator for scan based March algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 83-88, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Xiaogang Du, Nilanjan Mukherjee 0001, Wu-Tung Cheng, Sudhakar M. Reddy |
Full-speed field programmable memory BIST supporting multi-level looping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan, pp. 67-71, 2005, IEEE Computer Society, 0-7695-2313-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor |
The State-of-Art and Future Trends in Testing Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 54-59, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars |
The Effectiveness of the Scan Test and Its New Variants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 26-31, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | |
12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![IEEE Computer Society, 0-7695-2193-2 The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
1 | Luca Schiano, Marco Ottavi, Fabrizio Lombardi |
Markov Models of Fault-Tolerant Memory Systems under SEU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 38-43, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Shyue-Kung Lu, Shih-Chang Huang |
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 60-64, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Bruce F. Cockburn |
Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 46-51, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Zaid Al-Ars, Martin Herzog, Ivo Schanstra, Ad J. van de Goor |
Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 32-37, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Bit line twisting, bit line coupling, DRAMs, crosstalk noise, defect simulation, faulty behavior |
1 | R. Dean Adams, Robert Abbott, Xiaoliang Bai, Dwayne Burek, Eric MacDonald |
An Integrated Memory Self Test and EDA Solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 92-95, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Robert C. Aitken |
Redundancy & It's Not Just for Defects Anymore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 117-120, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Jaafar Alghazo, Adil Akaaboune, Nazeih Botros |
SF-LRU Cache Replacement Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 19-24, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
LFU, Replacement, LRU, Low Power Cache |
1 | Elaine Ou, Woodward Yang |
Fast Error-Correcting Circuits for Fault-Tolerant Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 8-12, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Swapnil Bahl |
A Novel Method for Silicon Configurable Test Flow and Algorithms for Testing, Debugging and Characterizing Different Types of Embedded Memories through a Shared Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 78-83, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Michael Spica, T. M. Mak |
Do We Need Anything More Than Single Bit Error Correction (ECC)? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 111-116, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu |
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 65-69, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Saman Adham, Benoit Nadeau-Dostie |
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 98-101, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | N. Derhacobian, Valery A. Vardanian, Yervant Zorian |
Embedded Memory Reliability: The SER Challenge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 104-110, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Adil Akaaboune, Nazeih Botros, Jaafar Alghazo |
Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 13-18, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Tag-Skipping, Victim Cache, Low-Power Cache |
1 | Carolina Selva, Cosimo Torelli, Danilo Rimondi, Rita Zappa, Stefano Corbani, Giovanni Mastrodomenico, Lara Albani |
A Programmable Built-in Self-Diagnosis for Embedded SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 84-89, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani |
Micro Programmable Built-In Self Repair for SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 72-77, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor |
A Fault Primitive Based Analysis of Linked Faults in RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 33-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Memory testing, march tests, functional fault models, linked faults, fault primitives |
1 | Betty Prince |
Application Specific DRAMs Today. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 7-13, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Robert C. Aitken |
Applying Defect-Based Test to Embedded Memories in a COT Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 72-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Roger Barth |
ITRS Commodity Memory Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 61-63, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott |
A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 14-19, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Zaid Al-Ars, Ad J. van de Goor |
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 27-32, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
two floating nodes, memory testing, DRAMs, dynamic faults, defect simulation |
1 | Baosheng Wang, Josh Yang, André Ivanov |
Reducing Test Time of Embedded SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 47-52, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time |
1 | Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri |
Optimal Spare Utilization in Repairable and Reliable Memory Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 64-71, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair |
1 | |
11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![IEEE Computer Society, 0-7695-2004-9 The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
1 | Youhei Zenda, Koji Nakamae, Hiromu Fujioka |
Cost Optimum Embedded DRAM Design by Yield Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 20-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li 0001 |
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 53-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Salamon, Bruce F. Cockburn |
An Electrical Simulation Model for the Chalcogenide Phase-Change Memory Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 86-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jean Michel Daga, Caroline Papaix, Emmanuel Racape, Marylene Combe, Vincent Sialelli, Jeanine Guichaoua |
A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 81-85, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jörg E. Vollrath |
Output Timing Measurement Using an Idd Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 43-46, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DDR, timing, DRAM |
1 | Farzin Karimi, Fabrizio Lombardi |
A Scan-Bist Environment for Testing Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 17-, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Daniele Rossi 0001, Cecilia Metra, Bruno Riccò |
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 27-31, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Caroline Papaix, Jean Michel Daga |
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 149-156, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | M. Templeton |
Challenges and Opportunities Created by the SoC Shockwave. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
1 | Luca Schiano, Cecilia Metra, Diego Marino |
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 49-56, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Toshiyuki Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye |
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
1 | Cyrille Dray, Philippe Gendrier |
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 143-148, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née |
An Automated Design Methodology for EEPROM Cell (ADE). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 137-142, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda |
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 12-16, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | D. Bied-Charreton, D. Guillon, B. Jacques |
The YATE Fail-Safe Interface: The User's Point of View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 39-43, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Bernard Coloma, Patrick Delaunay, Olivier Husson |
High Speed 15 ns 4 Mbits SRAM for Space Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 32-38, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Farzin Karimi, Fred J. Meyer, Fabrizio Lombardi |
Random Testing of Multi-Port Static Random Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 101-108, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu |
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 83-, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Romain Laffont, J. Razafindramora, Pierre Canet, Rachid Bouchakour, Jean-Michel Mirabel |
Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 168-176, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
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