Search results for "leakage"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
36	Jun Seomun, Insup Shin, Youngsoo Shin	Synthesis and implementation of active mode power gating circuits.	DAC	2010	DBLP DOI BibTeX RDF	active leakage, active-mode power gating, low power
36	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
36	Mahmoud Ben Naser, Csaba Andras Moritz	Power and performance tradeoffs with process variation resilient adaptive cache architectures.	SBCCI	2008	DBLP DOI BibTeX RDF	process variations, leakage power, adaptive cache
36	Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue	Improved Policies for Drowsy Caches in Embedded Processors.	DELTA	2008	DBLP DOI BibTeX RDF	Low Power Cache Design, Leakage Energy, Drowsy Cache
36	Rabiul Islam, Adam Brand, Dave Lippincott	Low power SRAM techniques for handheld products.	ISLPED	2005	DBLP DOI BibTeX RDF	back-bias, bitcell, memory, leakage
36	Meeta Srivastav, S. S. S. P. Rao, Himanshu Bhatnagar	Power Reduction Technique Using Multi-vt Libraries.	IWSOC	2005	DBLP DOI BibTeX RDF	High-Vt, Low-Vt, DFT, ASIC, Leakage power, DSM
36	Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reducing instruction cache energy consumption using a compiler-based strategy.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	compiler optimizations, Leakage power, cache design
36	Frank Sill, Frank Grassert, Dirk Timmermann	Low power gate-level design with mixed-Vth (MVT) techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
36	Bramha Allu, Wei Zhang 0002	Static next sub-bank prediction for drowsy instruction cache.	CASES	2004	DBLP DOI BibTeX RDF	compiler, instruction cache, leakage energy
36	Colin D. Walter	Simple Power Analysis of Unified Code for ECC Double and Add.	CHES	2004	DBLP DOI BibTeX RDF	unified code, elliptic curve cryptography, ECC, simple power analysis, SPA, Side channel leakage, Montgomery modular multiplication
36	Robert K. Grube, Qi Wang, Sung-Mo Kang	Design limitations in deep sub-0.1µm CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	GIDL, on-chip cache, tunneling currents, gate leakage
36	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
36	Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	programming method, decoupling capacitor budgeting algorithm, random walk approach, decap budgeting algorithm, power ground network design, isolation property, decap optimization process, leakage currents optimization algorithm, refined leakage model, heuristic method
36	Hari Ananthan, Chris H. Kim, Kaushik Roy 0001	Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.	ISLPED	2004	DBLP DOI BibTeX RDF	forward body bias, junction leakage, sub-threshold leakage, process variations
36	Manoj Sachdev	SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	junction leakage current, diagnostics, deep sub-micron, I DDQ testing, subthreshold leakage current
36	Jian Liu, Rafic Z. Makki	Power supply current detectability of SRAM defects.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	short-circuit currents, fault currents, power supply circuits, power supply current detectability, SRAM defects, SRAM cell, power supply current, I/sub DDQ/, quiescent power supply current, i/sub DDT/, transient power supply current, shorts, disturb-type pattern sensitivity, total current leakage, SRAM size, current detectability, large circuit effects, simulation, fault diagnosis, leakage currents, transients, SRAM chips, open defects, electric current measurement, physical defect
34	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
34	Yu-Hsun Lin, Xuan-Yi Lin, Yeh-Ching Chung	Reducing Leakage Power of JPEG Image on Asymmetric SRAM.	CSE (2)	2009	DBLP DOI BibTeX RDF
34	Chandra S. Nagarajan, Lin Yuan, Gang Qu 0001, Barbara G. Stamps	Leakage optimization using transistor-level dual threshold voltage cell library.	ISQED	2009	DBLP DOI BibTeX RDF
34	Amir Khatib Zadeh, Catherine H. Gebotys	Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC).	ISQED	2009	DBLP DOI BibTeX RDF
34	Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang	New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs.	ISQED	2009	DBLP DOI BibTeX RDF
34	Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel	A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi	Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction.	PATMOS	2008	DBLP DOI BibTeX RDF
34	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
34	Marc Bartels, Amit Joshi, John C. Rasmussen, Wolfgang Bangerth, Eva M. Sevick-Muraca	Post image acquisition mitigation of excitation light leakage in patterned illumination based NIR fluorescence tomography.	ISBI	2008	DBLP DOI BibTeX RDF
34	Josef Haid, Bernd Zimek, Thomas Leutgeb, Thomas Künemund	Impact of Leakage Current on Data Retention of RF-powered Devices During Amplitude-Modulation-based Communication.	DATE	2008	DBLP DOI BibTeX RDF
34	Siddharth Garg, Diana Marculescu	System-level mitigation of WID leakage power variability using body-bias islands.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	design, algorithms
34	Lang Lin, Wayne P. Burleson	Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems.	ISCAS	2008	DBLP DOI BibTeX RDF
34	Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled	Innovative power gating for leakage reduction.	ISCAS	2008	DBLP DOI BibTeX RDF
34	Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy 0001	Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii	Architectural leakage-aware management of partitioned scratchpad memories.	DATE	2007	DBLP DOI BibTeX RDF
34	Yulai Zhao 0003, Xianfeng Li, Dong Tong 0001, Xu Cheng 0001	Reuse Distance Based Cache Leakage Control.	HiPC	2007	DBLP DOI BibTeX RDF	Drowsy Cache Technique, Temporal Locality, Reuse Distance
34	Han Chen, Pasquale Malacaria	Quantitative analysis of leakage for multi-threaded programs.	PLAS	2007	DBLP DOI BibTeX RDF	multi-threaded languages, security, information theory
34	Kyung Ki Kim, Yong-Bin Kim	Optimal Body Biasing for Minimum Leakage Power in Standby Mode.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu	Leakage-Aware Design of Nanometer SoC.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu	A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.	ISQED	2007	DBLP DOI BibTeX RDF
34	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
34	Sarvesh Bhardwaj, Sarma B. K. Vrudhula	A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations.	VLSI Design	2007	DBLP DOI BibTeX RDF
34	Yuanlin Lu, Vishwani D. Agrawal	Statistical Leakage and Timing Optimization for Submicron Process Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
34	Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo	Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
34	Orlando José Tobias, Rui Seara	On the LMS algorithm with constant and variable leakage factor in a nonlinear environment.	IEEE Trans. Signal Process.	2006	DBLP DOI BibTeX RDF
34	Guangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk 0001, I. Demirkiran	Compiler-Directed Management of Leakage Power in Software-Managed Memories.	ISVLSI	2006	DBLP DOI BibTeX RDF
34	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.	DATE	2006	DBLP DOI BibTeX RDF
34	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
34	Lin Yuan, Sean Leventhal, Gang Qu 0001	Temperature-aware leakage minimization technique for real-time systems.	ICCAD	2006	DBLP DOI BibTeX RDF
34	Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim	A low power SoC bus with low-leakage and low-swing technique.	ISCAS	2006	DBLP DOI BibTeX RDF
34	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
34	Weiping Liao, Joseph M. Basile, Lei He 0001	Microarchitecture-level leakage reduction with data retention.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Mahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, Ibrahim Kolcu	Compiler-guided leakage optimization for banked scratch-pad memories.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein	Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
34	Wei Zhang 0002, Mahmut T. Kandemir, Mustafa Karaköy, Guangyu Chen	Reducing data cache leakage energy using a compiler-based approach.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	array-intensive applications, pointer-intensive applications, data caches, energy optimization, Compiler analysis
34	Yan Meng, Timothy Sherwood, Ryan Kastner	On the Limits of Leakage Power Reduction in Caches.	HPCA	2005	DBLP DOI BibTeX RDF
34	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	VLSI on-chip power/ground network optimization considering decap leakage currents.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia	Exploiting temporal idleness to reduce leakage power in programmable architectures.	ASP-DAC	2005	DBLP DOI BibTeX RDF
34	Chun-Yang Chen, Chia-Lin Yang, Shih-Hao Hung	Cache Leakage Management for Multi-programming Workloads.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
34	Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin	A divide-and-conquer approach to estimating minimum/maximum leakage current.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
34	Hangbae Chang, Kyung-kyu Kim	Design of Inside Information Leakage Prevention System in Ubiquitous Computing Environment.	ICCSA (4)	2005	DBLP DOI BibTeX RDF
34	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
34	Ankur Goel, Baquer Mazhari	Gate Leakage and Its Reduction in Deep Submicron SRAM.	VLSI Design	2005	DBLP DOI BibTeX RDF
34	Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Characterization and modeling of run-time techniques for leakage power reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
34	Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey	SRAM Leakage Suppression by Minimizing Standby Supply Voltage.	ISQED	2004	DBLP DOI BibTeX RDF
34	Wei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De	Compiler Support for Reducing Leakage Energy Consumption.	DATE	2003	DBLP DOI BibTeX RDF
34	Imad A. Ferzli, Farid N. Najm	Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations.	ICCAD	2003	DBLP DOI BibTeX RDF
34	Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein	Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.	ICCD	2003	DBLP DOI BibTeX RDF
34	Dongwoo Lee, Wesley Kwong, David T. Blaauw, Dennis Sylvester	Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design.	ISQED	2003	DBLP DOI BibTeX RDF
34	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains.	ISQED	2003	DBLP DOI BibTeX RDF
34	Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin	Analyzing Soft Errors in Leakage Optimized SRAM Design.	VLSI Design	2003	DBLP DOI BibTeX RDF
34	Chandramouli Gopalakrishnan, Srinivas Katkoori	Resource Allocation and Binding Approach for Low Leakage Power.	VLSI Design	2003	DBLP DOI BibTeX RDF
34	Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Compiler-directed instruction cache leakage optimization.	MICRO	2002	DBLP DOI BibTeX RDF
34	S. H. Tadas, Chaitali Chakrabarti	Architectural approaches to reduce leakage energy in caches.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
34	Zhanping Chen, Liqiong Wei, Kaushik Roy 0001	On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
34	Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai	Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.	MICRO	2001	DBLP DOI BibTeX RDF
34	Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, Rae McLellan	Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power.	PACS	2000	DBLP DOI BibTeX RDF
34	Zhanping Chen, Liqiong Wei, Kaushik Roy 0001	On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.	ISQED	2000	DBLP DOI BibTeX RDF
33	Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino	Dynamic indexing: concurrent leakage and aging optimization for caches.	ISLPED	2010	DBLP DOI BibTeX RDF	leakage optimization, memory hierarchy, aging, NBTI
33	Mingzhi Gao, Zuochang Ye, Yan Wang 0023, Zhiping Yu	Efficient tail estimation for massive correlated log-normal sums: with applications in statistical leakage analysis.	DAC	2010	DBLP DOI BibTeX RDF	comonotonicity, fast correlation transform, statistical leakage analysis, tail behavior
33	Pepijn J. de Langen, Ben H. H. Juurlink	Leakage-Aware Multiprocessor Scheduling.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Scheduling, Multiprocessor, Leakage power, Voltage scaling
33	Andrea Calimera, Enrico Macii, Massimo Poncino	NBTI-aware power gating for concurrent leakage and aging optimization.	ISLPED	2009	DBLP DOI BibTeX RDF	aging, leakage, power-gating, nbti
33	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
33	Sherief Reda, Aung Si, R. Iris Bahar	Reducing the leakage and timing variability of 2D ICcs using 3D ICs.	ISLPED	2009	DBLP DOI BibTeX RDF	3D integrated circuit, timing, variability, leakage
33	Bilge Mutlu, Fumitaka Yamaoka, Takayuki Kanda 0001, Hiroshi Ishiguro, Norihiro Hagita	Nonverbal leakage in robots: communication of intentions through seemingly unintentional behavior.	HRI	2009	DBLP DOI BibTeX RDF	geminoid, humanlikeness, nonverbal leakage, robovie, gaze, nonverbal behavior
33	Ziguo Zhong, Ting Zhu 0001, Tian He 0001, Zhi-Li Zhang	Leakage-aware energy synchronization on twin-star nodes.	SenSys	2008	DBLP DOI BibTeX RDF	energy synchronization, twin-star, leakage
33	Shaobo Liu, Qinru Qiu, Qing Wu 0002	Full-chip leakage current estimation based on statistical sampling techniques.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, statistical sampling, vlsi
33	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
33	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Leakage power reduction using stress-enhanced layouts.	DAC	2008	DBLP DOI BibTeX RDF	performance, mobility, layout, leakage, stress
33	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
33	Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari	Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.	ISPD	2007	DBLP DOI BibTeX RDF	multi-VTH, optimization, timing, low-power design, microprocessor, EDA, leakage power, sizing
33	Raphael C.-W. Phan, Kim-Kwang Raymond Choo, Swee-Huay Heng	Security of a Leakage-Resilient Protocol for Key Establishment and Mutual Authentication.	ProvSec	2007	DBLP DOI BibTeX RDF	mutual athentication, leakage-resilient, Key establishment
33	Amit Agarwal 0001, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy 0001, Chris H. Kim	Leakage Power Analysis and Reduction for Nanoscale Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	nanoscale circuits, CMOS, technology scaling, leakage power reduction
33	Javid Jaffari, Mohab Anis	Variability-aware device optimization under ION and leakage current constraints.	ISLPED	2006	DBLP DOI BibTeX RDF	device design, optimization, performance, process variation, leakage current
33	Georges Nabaa, Navid Azizi, Farid N. Najm	An adaptive FPGA architecture with process variation compensation and reduced leakage.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, process variations, leakage, body-biasing
33	Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri	An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.	ISLPED	2005	DBLP DOI BibTeX RDF	BDD, leakage, ADD
33	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
33	Linwei Niu, Gang Quan	Reducing both dynamic and leakage energy consumption for hard real-time systems.	CASES	2004	DBLP DOI BibTeX RDF	embedded system, low power design, DVS, real-time scheduling, leakage power reduction
33	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Post-layout leakage power minimization based on distributed sleep transistor insertion.	ISLPED	2004	DBLP DOI BibTeX RDF	sub-threshold current, leakage power, sleep transistor
33	Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David T. Blaauw	Leakage-and crosstalk-aware bus encoding for total power reduction.	DAC	2004	DBLP DOI BibTeX RDF	low power, encoding, leakage reduction
33	Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee	Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era.	DAC	2004	DBLP DOI BibTeX RDF	electrothermal couplings, temperature aware design, subthreshold leakage, energy delay product
33	Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Implications of technology scaling on leakage reduction techniques.	DAC	2003	DBLP DOI BibTeX RDF	low power, technology scaling, leakage reduction
30	Wihem Arsac, Luca Compagna, Samuel Paul Kaluvuri, Serena Elisa Ponta	Security validation tool for business processes.	SACMAT	2011	DBLP DOI BibTeX RDF