|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 2239 occurrences of 940 keywords
|
|
|
Results
Found 7472 publication records. Showing 7472 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
18 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 645-650, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Yi-Ting Chiang, Da-Wei Wang 0004, Churn-Jung Liau, Tsan-sheng Hsu |
Secrecy of Two-Party Secure Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DBSec ![In: Data and Applications Security XIX, 19th Annual IFIP WG 11.3 Working Conference on Data and Applications Security, Storrs, CT, USA, August 7-10, 2005, Proceedings, pp. 114-123, 2005, Springer, 3-540-28138-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Privacy Analysis, Scalar Product, Private Computation |
18 | Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir |
Understanding the energy efficiency of SMT and CMP with multiclustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 48-53, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
energy efficiency, simultaneous multithreading, chip multiprocessing |
18 | Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras |
Optimizing the Thermal Behavior of Subarrayed Data Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 625-630, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Kiyotaka Imai, Yasushi Yamagata, Sadaaki Masuoka, Naohiko Kimuzuka, Yuri Yasuda, Mitsuhiro Togo, Masahiro Ikeda, Yasutaka Nakashiba |
Device technology for body biasing scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 13-16, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Aditya Bansal, Kaushik Roy 0001 |
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1-4, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Ozcan Ozturk 0001, Mahmut T. Kandemir |
Energy management in software-controlled multi-level memory hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 270-275, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
software-managed memory, embedded systems |
18 | Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown |
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 284-290, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Puneet Gupta 0001, Andrew B. Kahng, Puneet Sharma |
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 421-426, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy 0001 |
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 453-458, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Ruchir Puri, Leon Stok, Subhrajit Bhattacharya |
Keeping hot chips cool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 285-288, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, high-performance, VLSI design |
18 | Hua Zhang 0002, Geoffrey Ye Li |
Clustered OFDM with adaptive antenna arrays for interference suppression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 3(6), pp. 2189-2197, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Rouwaida Kanj, Elyse Rosenbaum |
Critical evaluation of SOI design guidelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(9), pp. 885-894, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras |
Implementing branch-predictor decay using quasi-static memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(2), pp. 180-219, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Energy aware computing |
18 | Hartmut Klauck |
Quantum and Approximate Privacy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 37(1), pp. 221-246, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Yuan-Pei Lin, See-May Phoong |
DFT based transceivers with-windowing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 9th IEEE Symposium on Computers and Communications (ISCC 2006), June 28 - July 1, 2004, Alexandria, Egypt, pp. 574-579, 2004, IEEE Computer Society, 0-7803-8623-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Jason Helge Anderson, Farid N. Najm |
Low-power programmable routing circuitry for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 602-609, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Lin Li 0002, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Soft error and energy consumption interactions: a data cache perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 132-137, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
energy-efficiency, soft error, data cache |
18 | Joohee Kim, Marios C. Papaefthymiou |
Block-based multiperiod dynamic memory design for low data-retention power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1006-1018, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ali Keshavarzi, Kaushik Roy 0001, Charles F. Hawkins, Vivek De |
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(5), pp. 863-870, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger |
Static energy reduction techniques for microprocessor caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 303-313, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | S. Cservany, Jean-Marc Masgonty, Christian Piguet |
Stand-by Power Reduction for Storage Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 229-238, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Wei Zhang 0002, Mustafa Karaköy, Mahmut T. Kandemir, Guangyu Chen |
A compiler approach for reducing data cache energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 76-85, 2003, ACM, 1-58113-733-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
data caches, energy optimization, compiler analysis |
18 | Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi |
Multi-channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2003, 5th International Workshop, Cologne, Germany, September 8-10, 2003, Proceedings, pp. 2-16, 2003, Springer, 3-540-40833-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
EM Analysis, Side-channel attacks, DPA, Power Analysis, DEMA |
18 | R. M. Nussbaumer, D. G. Rüegg, L. M. Studer, J.-P. Gabriel |
Computer simulation of the motoneuron pool-muscle complex. I. Input system and motoneuron pool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Biol. Cybern. ![In: Biol. Cybern. 86(4), pp. 317-333, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Swarup Bhunia, Hai Li, Kaushik Roy 0001 |
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 157-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Mahesh Ketkar, Sachin S. Sapatnekar |
Standby power optimization via transistor sizing and dual threshold voltage assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 375-378, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Lipeng Cao |
Circuit power estimation using pattern recognition techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 412-417, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Hyun-Jeong Kim, Dong Hoon Lee 0001, Moti Yung |
Privacy against Piracy: Protecting Two-Level Revocable P-K Traitor Tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACISP ![In: Information Security and Privacy, 7th Australian Conference, ACISP 2002, Melbourne, Australia, July 3-5, 2002, Proceedings, pp. 482-496, 2002, Springer, 3-540-43861-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Hartmut Klauck |
On Quantum and Approximate Privacy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 2002, 19th Annual Symposium on Theoretical Aspects of Computer Science, Antibes - Juan les Pins, France, March 14-16, 2002, Proceedings, pp. 335-346, 2002, Springer, 3-540-43283-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Mun Wai Ng, Yuen-Hui Chee, Yong Ping Xu, Gamani Karunasiri |
On-chip compensation of dark current in infrared focal plane arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 509-512, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Sreejit Chakravarty, Sujit T. Zachariah |
STBM: a fast algorithm to simulate IDDQ tests forleakage faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5), pp. 568-576, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Vivek De, Shekhar Borkar |
Low power and high performance design challenges in future technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 1-6, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power design, memory, microprocessor, VLSI design |
18 | Shigeru Ohnishi, Michinori Nishihara |
A New Light-Based Logic IC Screening Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 358-366, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal |
Transistor Modeling for the VDSM Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 37-44, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field effect transistors, parameter extraction, SPICE, device modeling |
18 | Amit Sinha, Anantha P. Chandrakasan |
Energy Aware Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 50-, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Qi Wang, Sarma B. K. Vrudhula |
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 556-562, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low power, CMOS circuits, dual Vt |
18 | Kaushik Roy 0001, Liqiong Wei, Zhanping Chen |
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 366-370, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | M. Sivabalan, Stafford E. Tavares, Lloyd E. Peppard |
On the Design of SP Networks From an Information Theoretic Point of View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '92, 12th Annual International Cryptology Conference, Santa Barbara, California, USA, August 16-20, 1992, Proceedings, pp. 260-279, 1992, Springer, 3-540-57340-2. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 323-328, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nano-CMOS, power, leakage, SRAM, static noise margin |
18 | Sara Porat, Boaz Carmeli, Tamar Domany, Tal Drory, Ksenya Kveler, Alex Melament, Haim Nelken |
Masking Gateway for Enterprises. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Languages: From Formal to Natural ![In: Languages: From Formal to Natural, Essays Dedicated to Nissim Francez on the Occasion of His 65th Birthday, pp. 177-191, 2009, Springer, 978-3-642-01747-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Data Leakage Prevention (DLP), de-identification, Service Oriented Architecture (SOA), anonymization, Optical Character Recognition (OCR), data masking |
18 | David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat |
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 3-8, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage |
18 | Xin Huang, Kenli Li 0001, Renfa Li |
A Energy Efficient Scheduling Base on Dynamic Voltage and Frequency Scaling for Multi-core Embedded Real-Time System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP ![In: Algorithms and Architectures for Parallel Processing, 9th International Conference, ICA3PP 2009, Taipei, Taiwan, June 8-11, 2009. Proceedings, pp. 137-145, 2009, Springer, 978-3-642-03094-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
real-time, energy-efficiency, embedded, DVS, multi-core, leakage power, EDF |
18 | Werner Schindler, Colin D. Walter |
Optimal Recovery of Secret Keys from Weak Side Channel Traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMACC ![In: Cryptography and Coding, 12th IMA International Conference, Cryptography and Coding 2009, Cirencester, UK, December 15-17, 2009. Proceedings, pp. 446-468, 2009, Springer, 978-3-642-10867-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
power analysis, Side channel leakage, optimal strategy |
18 | Yasuhiro Fujii, Ryu Ebisawa, Satoshi Kai, Takaaki Yamada, Yoshinori Honda |
High-accuracy text search of hardcopy logs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iiWAS ![In: iiWAS'2009 - The Eleventh International Conference on Information Integration and Web-based Applications and Services, 14-16 December 2009, Kuala Lumpur, Malaysia, pp. 628-632, 2009, ACM, 978-1-60558-660-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
MFP, OCR, information leakage, text search, paper document |
18 | Cesare Ferri, Sherief Reda, R. Iris Bahar |
Parametric yield management for 3D ICs: Models and strategies for improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 19:1-19:22, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance, process variations, leakage, 3D integration, yield management |
18 | Kasper Bonne Rasmussen, Srdjan Capkun |
Location privacy of distance bounding protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 2008 ACM Conference on Computer and Communications Security, CCS 2008, Alexandria, Virginia, USA, October 27-31, 2008, pp. 149-160, 2008, ACM, 978-1-59593-810-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
wireless security, information leakage, distance bounding |
18 | Go Ohtake, Goichiro Hanaoka, Kazuto Ogawa |
An Efficient Strong Key-Insulated Signature Scheme and Its Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroPKI ![In: Public Key Infrastructure, 5th European PKI Workshop: Theory and Practice, EuroPKI 2008, Trondheim, Norway, June 16-17, 2008, Proceedings, pp. 150-165, 2008, Springer, 978-3-540-69484-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
strong key-insulated signature, key leakage, DL assumption, random oracle model, adaptive security |
18 | Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici |
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 11-20, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Sub-VToperation, variation compensation, logic style, active-mode leakage, process variations |
18 | Biswajit Mishra, Bashir M. Al-Hashimi |
Subthreshold FIR Filter Architecture for Ultra Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 1-10, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Subthreshold design, Minimum Energy Point, Ultra Low Power Design, Leakage, FIR |
18 | Kazuki Yoneyama |
Efficient and Strongly Secure Password-Based Server Aided Key Exchange (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2008, 9th International Conference on Cryptology in India, Kharagpur, India, December 14-17, 2008. Proceedings, pp. 172-184, 2008, Springer, 978-3-540-89753-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
password-based key exchange, password-based server aided key exchange, leakage of internal states, undetectable on-line dictionary attack |
18 | Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas |
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 407-410, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
leakage estimation, logic design, cmos gates |
18 | Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar |
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 30-34, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant |
18 | Po-Kuan Huang, Soheil Ghiasi |
Efficient and scalable compiler-directed energy optimization for realtime applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 27:1-27:16, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
energy-aware compiler, Leakage, technology scaling |
18 | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 86-91, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reconfigurable instant-on system, ultralow-power reconfigurable computing, complementary nanoelectromechanical carbon nanotube switches, coplanar carbon nanotubes, low operation voltages, built-in energy storage, CNEMS, stable on-off state, latching mechanism, nonvolatile memory-mode operation, CMOS transistors, system development, leakage current |
18 | Aveek Sarkar, Shen Lin, Kai Wang |
A methodology for analysis and verification of power gated circuits with correlated results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 351-354, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RedHawk, standby leakage current, design, verification, analysis, power gate, MTCMOS |
18 | Koji Kida, Hisashi Sakamoto, Hideo Shimazu, Hiroyuki Tarumi |
InfoCage: A Development and Evaluation of Confidential File Lifetime Monitoring Technology by Analyzing Events from File Systems and GUIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSEC ![In: Advances in Information and Computer Security, Second International Workshop on Security, IWSEC 2007, Nara, Japan, October 29-31, 2007, Proceedings, pp. 246-261, 2007, Springer, 978-3-540-75650-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Secure Office, Information Leakage Countemesure, Operation Monitoring, Knowledge Base, Log Analysis |
18 | Chanseok Hwang, Peng Rong, Massoud Pedram |
Sleep transistor distribution in row-based MTCMOS designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 235-240, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
leakage minimization, placement, MTCMOS |
18 | Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 501-504, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
layout, leakage power, insertion, standard-cell, sleep transistor |
18 | Zhiyu Liu, Volkan Kursun |
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 239-244, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling |
18 | T. M. Mak, Sani R. Nassif |
Guest Editors' Introduction: Process Variation and Stochastic Design and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 436-437, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage |
18 | Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee |
A low-cost memory remapping scheme for address bus protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 74-83, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
address bus leakage protection, secure processor |
18 | Ali Bastani, Charles A. Zukowski |
Monotonic static CMOS tradeoffs in sub-100nm technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 278-283, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gate leakage current, monotonic static CMOS logic, low power design, noise tolerance, static power |
18 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh |
Timing driven power gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 121-124, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage current, power gating, IR drop |
18 | Mathieu Ciet, Marc Joye |
Elliptic Curve Cryptosystems in the Presence of Permanent and Transient Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 36(1), pp. 33-43, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
elliptic curve cryptography, fault attacks, fault analysis, information leakage |
18 | Wei Huang 0004, Eric Humenay, Kevin Skadron, Mircea R. Stan |
The need for a full-chip and package thermal model for thermally optimized IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 245-250, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
leakage, package, thermal model, temperature-aware design |
18 | Walid Elgharbawy, Pradeep Golconda, Magdy A. Bayoumi |
Noise-tolerant high fan-in dynamic CMOS circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 134-137, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
high fan-in domino, CMOS, noise-tolerant, subthreshold leakage, dynamic circuits |
18 | John Wei, Chris Rowen |
Implementing low-power configurable processors: practical options and tradeoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 706-711, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power |
18 | Ravindra Jejurikar, Rajesh K. Gupta 0001 |
Procrastination scheduling in fixed priority real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 57-66, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
critical speed, procrastication scheduling, real-time systems, leakage power, fixed priority, low power scheduling |
18 | Maurice Meijer, Francesco Pessolano, José Pineda de Gyvez |
Technology exploration for adaptive power and frequency scaling in 90nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 14-19, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
adaptive body bias, low power, CMOS, performance optimization, leakage, adaptive voltage scaling |
18 | Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001 |
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 248-251, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DSM leakage control and scaling trends, dual supply ALU design, low power techniques |
18 | Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon |
A dual-core 64b ultraSPARC microprocessor for dense server applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 673-677, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
L2, UltraSPARC, coupling noise, deep submicron technology, dense server, dual-core, throughput computing, cache, multiprocessor, leakage, NBTI, negative bias temperature instability |
18 | Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin |
Performance, energy, and reliability tradeoffs in replicating hot cache lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 309-317, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
cache reliability, line replication, cache memories, leakage power |
18 | Kwang-Il Oh, Lee-Sup Kim |
A clock delayed sleep mode domino logic for wide dynamic OR gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 176-179, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clock delay, low power, leakage, sleep mode, dynamic circuits |
18 | Werner Schindler, Colin D. Walter |
More Detail for a Combined Timing and Power Attack against Implementations of RSA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMACC ![In: Cryptography and Coding, 9th IMA International Conference, Cirencester, UK, December 16-18, 2003, Proceedings, pp. 245-263, 2003, Springer, 3-540-20663-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
statistical decision problem, power analysis, exponentiation, timing attack, RSA cryptosystem, side channel leakage, Montgomery modular multiplication |
18 | Ryo Fujioka, Kiyokazu Katayama, Ryotaro Kobayashi, Hideki Ando, Toshio Shimada |
A preactivating mechanism for a VT-CMOS cache using address prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 247-250, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
L1 data cache, leakage current, address prediction |
18 | Michael Zhang, Krste Asanovic |
Fine-grain CAM-tag cache resizing using miss tags. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 130-135, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
cache resizing, low-power, energy efficiency, leakage current, content-addressable-memory |
18 | Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa |
Automated selective multi-threshold design for ultra-low standby applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 202-206, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
standby leakage current, automated design, multi-threshold |
18 | Fei Li 0003, Lei He 0001, Kewal K. Saluja |
Estimation of Maximum Power-Up Current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 51-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
current estimation, ATPG algorithm, leakage reduction |
18 | George Sery, Shekhar Borkar, Vivek De |
Life is CMOS: why chase the life after? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 78-83, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
leakage control, microarchitecture, technology scaling |
18 | Karine Gandolfi, Christophe Mourtel, Francis Olivier |
Electromagnetic Analysis: Concrete Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, pp. 251-261, 2001, Springer, 3-540-42521-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
smart cards, DPA, SPA, DEMA, side channel leakage, SEMA, electromagnetic analysis |
18 | Claude Thibeault |
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 80-87, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
IC diagnosis, probabilistic differential quiescent current signature, noise source, embedded logic, robustness, maximum likelihood estimation, maximum likelihood estimation, IDDQ testing, subthreshold leakage current |
18 | Adam L. Young, Moti Yung |
The Prevalence of Kleptographic Attacks on Discrete-Log Based Cryptosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '97, 17th Annual International Cryptology Conference, Santa Barbara, California, USA, August 17-21, 1997, Proceedings, pp. 264-276, 1997, Springer, 3-540-63384-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
DSA signature, Menezes-Vanstone PKCS, Schnorr signature algorithm, protocol abuse, leakage-bandwidth, cryptographic system implementations, randomness, pseudorandomness, Diffie-Hellman, subliminal channels, kleptography, setup, ElGamal encryption, ElGamal signature, Discrete-Log |
18 | Hisashi Kondo, Kwang-Ting Cheng |
An Efficient Compact Test Generator for IDDQ Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 177-182, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Selective IDDQ, Pattern Compaction, Pseudo Stuck-at Fault, Essential Fault, Test, ATPG, Fault Model, Testability, IDDQ, Leakage Fault |
18 | Weiwei Mao, Ravi K. Gulati |
Quietest: A methodology for selecting IDDQ test vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(4), pp. 349-357, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
weak faults, I DDQ testing, Leakage faults |
15 | Jung Yeon Hwang, Ji Young Chun, Dong Hoon Lee 0001 |
A note on leakage-resilient authenticated key exchange. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 8(5), pp. 2274-2279, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Panagiotis Papadimitriou 0002, Hector Garcia-Molina |
A Model for Data Leakage Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDE ![In: Proceedings of the 25th International Conference on Data Engineering, ICDE 2009, March 29 2009 - April 2 2009, Shanghai, China, pp. 1307-1310, 2009, IEEE Computer Society, 978-0-7695-3545-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Krzysztof Pietrzak |
A Leakage-Resilient Mode of Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT 2009, 28th Annual International Conference on the Theory and Applications of Cryptographic Techniques, Cologne, Germany, April 26-30, 2009. Proceedings, pp. 462-482, 2009, Springer, 978-3-642-01000-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Sheng-Chih Lin, Kaustav Banerjee |
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1488-1498, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ja Chun Ku, Yehea I. Ismail |
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 241-248, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Scott Rose, Anastase Nakassis |
Minimizing information leakage in the DNS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Netw. ![In: IEEE Netw. 22(2), pp. 22-25, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Marco Bucci, Raimondo Luzzi, Santos Torres Vargas |
A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 231-234, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Imad M. Abbadi, Muntaha Alawneh |
Preventing Insider Information Leakage for Enterprises. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SECURWARE ![In: Proceedings of the Second International Conference on Emerging Security Information, Systems and Technologies, SECURWARE 2008, August 25-31, 2008, Cap Esterel, France, pp. 99-106, 2008, IEEE Computer Society, 978-0-7695-3329-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino |
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 298-303, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Muntaha Alawneh, Imad M. Abbadi |
Preventing information leakage between collaborating organisations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEC ![In: Proceedings of the 10th International Conference on Electronic Commerce 2008, Innsbruck, Austria, August 19-22, 2008, pp. 38:1-38:10, 2008, ACM, 978-1-60558-075-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
collaborating organisations, enterprise rights management, share but protect |
15 | Jungseob Lee, Lin Xie, Azadeh Davoodi |
A Dual-Vt low leakage SRAM array robust to process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 580-583, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2761-2764, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Meikang Qiu, Jiande Wu, Jingtong Hu, Yi He 0001, Edwin Hsing-Mean Sha |
Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (1) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume I, pp. 192-198, 2008, IEEE Computer Society, 978-0-7695-3492-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun |
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 305-310, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory |
15 | Mirette Sadek, Alireza Tarighat, Ali H. Sayed |
A Leakage-Based Precoding Scheme for Downlink Multi-User MIMO Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 6(5), pp. 1711-1721, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
|
|