Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
43	Xiaojun Wang, Miriam Leeser	Efficient FPGA implementation of qr decomposition using a systolic array architecture.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA
43	Scott Sirowy, Greg Stitt, Frank Vahid	C is for circuits: capturing FPGA circuits as sequential code for portability.	FPGA	2008	DBLP DOI BibTeX RDF	sequential code, FPGA, synthesis, portability, circuit design
43	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
43	Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck	Exploration of pipelined FPGA interconnect structures.	FPGA	2004	DBLP DOI BibTeX RDF	PipeRoute, pipelined FPGA, pipelined interconnect, registered routing, architecture explorations
43	Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
43	Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport	An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm.	FPGA	2004	DBLP DOI BibTeX RDF	finite-difference time-domain, FPGA, hardware acceleration, hardware implementation, FDTD
43	Joydeep Ray, James C. Hoe	High-level modeling and FPGA prototyping of microprocessors.	FPGA	2003	DBLP DOI BibTeX RDF	operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture
43	Adam J. Elbirt, Christof Paar	An FPGA implementation and performance evaluation of the Serpent block cipher.	FPGA	2000	DBLP DOI BibTeX RDF	algorithm-agility, FPGA, cryptography, VHDL, block cipher
43	Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance	A Novel Predictable Segmented FPGA Routing Architecture.	FPGA	1998	DBLP DOI BibTeX RDF	FPGA, routing, programmable logic
43	Bryan Catanzaro, Brent E. Nelson	Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
43	K. K. Lee, D. F. Wong 0001	Incremental reconfiguration of multi-FPGA systems.	FPGA	2002	DBLP DOI BibTeX RDF
43	Andy Yan, Rebecca Cheng, Steven J. E. Wilton	On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques.	FPGA	2002	DBLP DOI BibTeX RDF
43	Andreas Dandalis, Viktor K. Prasanna	Configuration compression for FPGA-based embedded systems.	FPGA	2001	DBLP DOI BibTeX RDF
43	Steven Trimberger	Scheduling Designs into a Time-Multiplexed FPGA.	FPGA	1998	DBLP DOI BibTeX RDF
43	Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor	Constraints from Hell: How to Tell Makes a Good FPGA (Panel).	FPGA	1998	DBLP DOI BibTeX RDF
43	Vaughn Betz, Jonathan Rose	Using Architectural "Families" to Increase FPGA Speed and Density.	FPGA	1995	DBLP DOI BibTeX RDF
43	Scott Hauck, Gaetano Borriello	Logic Partition Orderings for Multi-FPGA Systems.	FPGA	1995	DBLP DOI BibTeX RDF
42	Reza M. Rad, Mohammad Tehranipoor	Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	performance, FPGA, reliability, CMOS, Nanotechnology
41	Shepard Siegel, Michael J. Wirthlin	FPGA-2010 pre-conference workshop on open-source for FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, open-source
41	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Embedded floating-point units in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPU, FPGA, floating-point, FPGA architecture
41	Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao 0001, Russell Tessier	Scalable network virtualization using FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, virtual networks
41	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
41	Weirong Jiang, Viktor K. Prasanna	Large-scale wire-speed packet classification on FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, decision tree, pipeline, sram, packet classification
41	Rosemary M. Francis, Simon W. Moore	FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.	FPGA	2009	DBLP DOI BibTeX RDF	tdm wiring, fpga, routing
41	Ishaan L. Dalal, Deian Stefan	A hardware framework for the fast generation of multiple long-period random number streams.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, parallelized architecture, random number generator, mersenne twister
41	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
41	Ian Kuon, Jonathan Rose	Measuring the gap between FPGAs and ASICs.	FPGA	2006	DBLP DOI BibTeX RDF	area comparison, delay comparison, power comparison, FPGA, ASIC
41	Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu	Design, implementation, and verification of active cache emulator (ACE).	FPGA	2006	DBLP DOI BibTeX RDF	FPGA-based emulator, real-time emulation, cache modeling
41	Jianhua Liu, Michael Chang, Chung-Kuan Cheng	An iterative division algorithm for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, low power, high performance, division
41	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft error rate estimation and mitigation for SRAM-based FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	soft error rate estimation, error recovery, SRAM-based FPGA
41	Yuzheng Ding, Peter Suaris, Nan-Chi Chou	The effect of post-layout pin permutation on timing.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
41	Lesley Shannon, Paul Chow	Using reconfigurability to achieve real-time profiling for hardware/software codesign.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, profiling, performance measurement, embedded processor, hardware/software codesign, soft processor
41	John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor	Reprogrammable network packet processing on the field programmable port extender (FPX).	FPGA	2001	DBLP DOI BibTeX RDF	Internet, FPGA, routing, network, ATM, modularity, reconfiguration, processing, IP, hardware, packet
41	Yanteng Sun, Peng Li 0031, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	HMMer acceleration using systolic array based reconfigurable architecture.	FPGA	2009	DBLP DOI BibTeX RDF	reconfigurable., systolic array, acceleration, hmmer
41	Tim Güneysu, Christof Paar, Jan Pelzl	Attacking elliptic curve cryptosystems with special-purpose hardware.	FPGA	2007	DBLP DOI BibTeX RDF	Pollard's Rho, cryptanalysis, elliptic curve cryptosystem, discrete logarithm
41	Dmitri B. Strukov, Konstantin K. Likharev	A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.	FPGA	2006	DBLP DOI BibTeX RDF	integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect
41	Akshay Sharma, Carl Ebeling, Scott Hauck	Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
41	Daniel Denning, Malachy Devlin, James Irvine 0001	Hardware co-simulation in system generator of the AES-128 encryption algorithm.	FPGA	2004	DBLP DOI BibTeX RDF
41	Huiqun Liu, Kai Zhu 0001, D. F. Wong 0001	Circuit Partitioning with Complex Resource Constraints in FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
41	Jordan S. Swartz, Vaughn Betz, Jonathan Rose	A Fast Routability-Driven Router for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
41	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
40	Wen-Jong Fang, Allen C.-H. Wu	A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations.	ICCAD	1996	DBLP DOI BibTeX RDF	Multiple-FPGA partitioning, multiple-FPGA synthesis, functional structuring and functional partitioning
40	S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot	Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA-based hardware accelerator, lattice Boltzman simulations, High-performance computing, cellular automata
40	Reza M. Rad, Mohammad Tehranipoor	A new hybrid FPGA with nanoscale clusters and CMOS routing.	DAC	2006	DBLP DOI BibTeX RDF	reconfigurable nanoscale devices, FPGA, molecular electronics
40	Máire McLoone, John V. McCanny	High Performance Single-Chip FPGA Rijndael Algorithm Implementations.	CHES	2001	DBLP DOI BibTeX RDF	Encryption, AES, Rijndael, FPGA Implementation
40	Wen-Jong Fang, Allen C.-H. Wu	Multiway FPGA partitioning by fully exploiting design hierarchy.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis
40	Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong	Performance Benefits of Monolithically Stacked 3-D FPGA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
40	Bryan Catanzaro, Brent E. Nelson	Higher Radix Floating-Point Representations for FPGA-Based Arithmetic.	FCCM	2005	DBLP DOI BibTeX RDF
40	Andrzej Krasniewski	Application-Dependent Testing of FPGA Delay Faults.	EUROMICRO	1999	DBLP DOI BibTeX RDF
39	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
39	Peter A. Jamieson, Kenneth B. Kent	Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, verilog hdl
39	Y. Hamid, Martin Langhammer	Multiplier architectures for FPGA double precision functions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, floating point
39	Claudio Favi, Edoardo Charbon	A 17ps time-to-digital converter implemented in 65nm FPGA technology.	FPGA	2009	DBLP DOI BibTeX RDF	65nm fpga, deep sub-nanosecond time resolution, high-speed readout, time-correlated instrumentation, time-to-digital converters, ultra-fast digital electronics, optical communications, tdc
39	Edward C. Lin, Rob A. Rutenbar	A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.	FPGA	2009	DBLP DOI BibTeX RDF	in silico vox, fpga, speech recognition, dsp
39	JIanDe Yu, Jinmei Lai	A novel minloop SB design to improve FPGA routability.	FPGA	2009	DBLP DOI BibTeX RDF	minimum-loop-size maximization method, minloop switch box, routing resources design, fpga
39	Ray Bittner	Bus mastering PCI express in an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	bus mastering, pcie, performance, fpga, design, pci express
39	Daniel Le Ly, Paul Chow	A high-performance FPGA architecture for restricted boltzmann machines.	FPGA	2009	DBLP DOI BibTeX RDF	neural network hardware, restricted boltzmann machines, scalable hardware designs, fpga, high-performance computing, complexity reduction
39	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, multiprocessor, network on chip
39	Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner	Fpga-based face detection system using Haar classifiers.	FPGA	2009	DBLP DOI BibTeX RDF	haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost
39	Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck	Fpga-based data acquisition system for a positron emission tomography (PET) scanner.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, positron emission tomography
39	David Sheldon, Frank Vahid	A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA
39	Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong	FPGA interconnect design using logical effort.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, logical effort
39	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
39	Bita Gorjiara, Daniel Gajski	FPGA-friendly code compression for horizontal microcoded custom IPs.	FPGA	2007	DBLP DOI BibTeX RDF	dictionary-based compression, microcoded architectures, no-instruction-set computer, FPGA, memory optimization
39	Kevin Oo Tinmaung, David Howland, Russell Tessier	Power-aware FPGA logic synthesis using binary decision diagrams.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, binary decision diagram, dynamic power
39	Nicholas Weaver, Vern Paxson, José M. González	The shunt: an FPGA-based accelerator for network intrusion prevention.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, intrusion detection, hardware acceleration, NIC
39	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
39	Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon	Magnetic tunnelling junction based FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	magnetic tunneling junction, FPGA, non volatility
39	Norbert Pramstaller, Christian Rechberger, Vincent Rijmen	A compact FPGA implementation of the hash function whirlpool.	FPGA	2006	DBLP DOI BibTeX RDF	compact hardware implementation, FPGA, hash function, whirlpool
39	Julien Lamoureux, Steven J. E. Wilton	FPGA clock network architecture: flexibility vs. area and power.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, architecture, low-power, clock network
39	Fernanda Lima 0001, Luigi Carro, Ricardo Augusto da Luz Reis	Reducing pin and area overhead in fault-tolerant FPGA-based designs.	FPGA	2003	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
39	Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun	Wire type assignment for FPGA routing.	FPGA	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, wire type assignment, FPGA routing
39	William Chow, Jonathan Rose	EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits.	FPGA	2002	DBLP DOI BibTeX RDF	event horizon, manual placement and pipelining, FPGA, programmable logic
39	Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider	FPGA implementation of neighborhood-of-four cellular automata random number generators.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, cellular automata, random number generator
39	Herman Schmit, Vikas Chandra	FPGA switch block layout and evaluation.	FPGA	2002	DBLP DOI BibTeX RDF	VLSI layout, FPGA interconnect
39	Jörg Ritter 0002, Paul Molitor	A pipelined architecture for partitioned DWT based lossy image compression using FPGA's.	FPGA	2001	DBLP DOI BibTeX RDF	embedded zero tree coding, FPGA, field programmable gate arrays, architecture, wavelet transformation, pipelining, Xilinx, lossy image compression
39	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
39	Marc-André Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
39	Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez	A multilevel hierarchical interconnection structure for FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
39	Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Evaluation of granularity on threshold voltage control in flex power FPGA.	FPGA	2006	DBLP DOI BibTeX RDF
39	Yirong OuYang, Jiarong Tong	A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
39	Michael J. Wirthlin	Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement.	FPGA	2004	DBLP DOI BibTeX RDF
39	Erik Chmelar	Subframe multiplexing for FPGA manufacturing test configuration.	FPGA	2004	DBLP DOI BibTeX RDF
39	Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity.	FPGA	2004	DBLP DOI BibTeX RDF
39	Katarzyna Leijten-Nowak, Jef L. van Meerbergen	An FPGA architecture with enhanced datapath functionality.	FPGA	2003	DBLP DOI BibTeX RDF	adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry
39	Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat	Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES.	FPGA	2003	DBLP DOI BibTeX RDF
39	Michael G. Wrighton, André DeHon	Hardware-assisted simulated annealing with application for fast FPGA placement.	FPGA	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation
39	Mehdi Baradaran Tahoori	A high resolution diagnosis technique for open and short defects in FPGA interconnects.	FPGA	2003	DBLP DOI BibTeX RDF
39	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
39	Pak K. Chan, Martine D. F. Schlag	New parallelization and convergence results for NC: a negotiation-based FPGA router.	FPGA	2000	DBLP DOI BibTeX RDF
39	Paul S. Graham, Brent E. Nelson	FPGA-Based Sonar Processing.	FPGA	1998	DBLP DOI BibTeX RDF
38	Navin Vemuri, Priyank Kalla, Russell Tessier	BDD-based logic synthesis for LUT-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, decomposition, logic synthesis, BDD
38	Rajeev Jayaraman	Physical design for FPGAs.	ISPD	2001	DBLP DOI BibTeX RDF	FPGA, routing, placement, physical design
38	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	FCCM	1995	DBLP DOI BibTeX RDF
38	Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic	A stochastic model to predict the routability of field-programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
37	Julien Lamoureux, Scott Miller, Mihai Sima	Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	shift-and-add arithmetic, fpga, cordic, coarse-grained
37	Kristian Stevens, Henry Chen, Terry Filiba, Peter L. McMahon, Yun S. Song	Application of a reconfigurable computing cluster to ultra high throughput genome resequencing (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	genome resequencing, fpga, acceleration, reconfigurable logic
37	David L. Foster, Darrin M. Hanna	Maximizing area-constrained partial fault tolerance in reconfigurable logic.	FPGA	2010	DBLP DOI BibTeX RDF	area-constrained, FPGA
37	Mohammed Y. Niamat, Sowmya Panuganti, Tejas Raviraj	Modeling and simulation of nano quantum FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	nano, fpga, qca, quantum
37	Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing