|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 59 occurrences of 34 keywords
|
|
|
Results
Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Bhavya Kumar, Megha Sharma, Rishu Chaujar |
Gate electrode work function engineered JAM-GS-GAA FinFET for analog/RF applications: Performance estimation and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 135, pp. 105766, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Abhishek Ray, Alok Naugarhiya, Guru Prasad Mishra |
Total ionizing dose effect of bulk and SOI P-FinFET with linear workfunction modulation technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 137, pp. 105822, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Kallolini Banerjee, Abhijit Biswas |
Enhanced analog/RF performance of hybrid charge plasma based junctionless C-FinFET amplifiers at 10 nm technology node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 131, pp. 105662, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Vipin Kumar Sharma, Mohammad Samar Ansari, Tahira Parveen |
FinFET-based non-linear analog signal processing modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 131, pp. 105626, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Sunitha Bhukya, Bheema Rao Nistala |
Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 139, pp. 105907, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Sameer Yadav, P. N. Kondekar, Bhaskar Awadhiya |
Performance estimation of non-hysteretic negative capacitance FinFET based SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 137, pp. 105796, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bhavya Kumar, Megha Sharma, Rishu Chaujar |
Junctionless-accumulation-mode stacked gate GAA FinFET with dual-k spacer for reliable RFIC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 139, pp. 105910, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Zhijia Zhao 0005, Yuxi Wei, Tao Sun, Kemeng Yang, Jie Wei, Yanjiang Jia, Siyu Deng, Xiaorong Luo, Bo Zhang 0027 |
High voltage GaN vertical FinFET with a compatible integrated fin diode for low reverse conduction loss. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 136, pp. 105781, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Pushkar Praveen, R. K. Singh |
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 28(6), pp. 105:1-105:29, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Andrada Muntean, Yonatan Shoshan, Slava Yuzhaninov, Emanuele Ripiccini, Claudio Bruschini, Alexander Fish, Edoardo Charbon |
On-chip fully reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2302.08291, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | M. V. Nageswara Rao, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak, Baseem Khan |
Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2023, pp. 7069746:1-7069746:13, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bo Zhao, Minghui Yin, Weihua Zhang, Hongwei Liu, Zhiqiang Li |
Design of a variable precision CORDIC coprocessor for RISC-V architecture based on FinFET process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(19), pp. 20230362, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bart Philippe, Patrick Reynaert |
Mm-wave Circuit Design in 16nm FinFET for 6G Applications ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2023 |
DOI RDF |
|
14 | Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier |
Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3 ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2023 |
DOI RDF |
|
14 | Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S 0001, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani |
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 69-72, 2023, IEEE, 979-8-3503-0423-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Valentina Marazzi, Enrico Monaco, Claudio Nani, Danilo Manstretta |
Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 18th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023, Valencia, Spain, June 18-21, 2023, pp. 29-32, 2023, IEEE, 979-8-3503-0320-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Ying-Ru Xiong, Yu-Hsien Lin |
Comparison of Conventional I-Type and T-Type FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-Taiwan ![In: International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2023, PingTung, Taiwan, July 17-19, 2023, pp. 725-726, 2023, IEEE, 979-8-3503-2417-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx |
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 895-899, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Shayesteh Masoumian, Roel Maes, Rui Wang, Karthik Keni Yerriswamy, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil |
Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, October 16-18, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2599-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Taiki Uemura, Byungjin Chung, Shin-Young Chung, Seungbae Lee, Yuchul Hwang, Sangwoo Pae |
Impact of Design and Process on Alpha-Induced SER in 4 nm Bulk-FinFET SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-8, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Emmanuel Bender, Joseph B. Bernstein, Duane S. Boning |
The Effects of Process Variations and BTI in Packaged FinFET Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Balaji Narasimham, H. Luk, C. Paone, A-R. Montoya, T. Riehle, Mike Smith, Liming Tsau |
Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Zixuan Sun, Haoran Lu, Yongkang Xue, Wenpu Luo, Zirui Wang, Jiayang Zhang, Zhigang Ji, Runsheng Wang, Ru Huang |
Investigation of Hot Carrier Enhanced Body Bias Effect in Advanced FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Ri-an Zhao, Matthew Koskinen, Yang Liu, Xinggong Wan |
Voltage Ramp Stress Test Optimization for Wafer Level Hot Carrier Monitoring in FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Yoni Xiong, Yueh Chiang, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva |
Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | M. Jamil, S. Mukhopadhay, M. Ghoneim, A. Shailos, Chetan Prasad, Inanc Meric, Stephen Ramey |
Reliability Studies on Advanced FinFET Transistors of the Intel 4 CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Manisha Sharma, Hokyung Park, Yinghong Zhao, Ki-Don Lee, Liangshan Chen, Joonah Yoon, Rakesh Ranjan, Caleb Dongkyan Kwon, Hyewon Shim, Myungsoo Yeo, Shin-Young Chung, Jon Haefner |
Polarity Dependency of MOL-TDDB in FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-3, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Nicholas J. Pieper, Yoni Xiong, Dennis R. Ball, J. Pasternak, Bharat L. Bhuva |
Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023, pp. 1-6, 2023, IEEE, 978-1-6654-5672-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Ankit Dixit, Navneen Kumar, Vihar Georgiev, Navjeet Bagga |
Gate Oxide Induced Reliability Assessment of Junctionless FinFET-Based Hydrogen Gas Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SENSORS ![In: 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-0387-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Santiago S. Pérez, Alessandro Bedoya, Luis-Miguel Prócel, Ramiro Taco |
Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 14th IEEE Latin America Symposium on Circuits and System, LASCAS 2023, Quito, Ecuador, February 28 - March 3, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5705-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Lorenzo Stevenazzi, Andrea Baschirotto, Marcello De Matteis |
Static Noise Margin in 16 nm FinFET 6T and 8T SRAM Cells for Compute-in-Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Sriraj Chennamadhavuni, Shara Mathew, Rathnamala Rao |
An Exploration of the Effective Path for Current Conduction in a Triple Gate Junctionless FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TENCON ![In: IEEE Region 10 Conference, TENCON 2023, Chiang Mai, Thailand, October 31 - Nov. 3, 2023, pp. 473-478, 2023, IEEE, 979-8-3503-0219-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Xinshu Xie, Jiongzhe Su, Hao Zhang, Hao Cai |
A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-4428-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Guangao Wang, Qi Xiao, Haigang Feng, Jingjing Dong |
A 0.9V 1.2GHz-BW 15.8dBm-OIP3 Current Mode Analog Baseband for Broadband Receivers in 12nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023, pp. 81-82, 2023, IEEE, 979-8-3503-4428-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Mattias Palm, Daniele Mastantuono, Christer Jansson, Erik Backenius, Nikola Ivanisevic, Mikael Normark, Prakash Harikumar, My-Chien Yee, Andreas Leidenhed, Roland Strandberg, Sunny Sharma, Hanie Ghaedrahmati, Martin Anderson, Peter Nygren, Peter Sjögren, Erik Säll, Robert Hägglund, Lars Sundström |
A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 333-336, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Huanhuan Zhang, Alexander Lyakhov, Arvind Raghavan |
A 4nm FinFET 0.8V 13ppm/°C Switched Capacitor Based Current Mode Bandgap Reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 81-84, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami |
A 0.82pJ/b 50Gb/s PAM4 VCSEL Driver with 3-Tap Asymmetric FFE in 12nm CMOS FinFET Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 369-372, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Lida Kouhalvandi, Eva Catoggio, Simona Donati Guerrieri |
Synergic Exploitation of TCAD and Deep Neural Networks for Nonlinear FinFET Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: 20th IEEE International Conference on Smart Technologies, EUROCON 2023, Torino, Italy, July 6-8, 2023, pp. 542-546, 2023, IEEE, 978-1-6654-6397-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang |
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li |
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Kihwang Son, Seulki Park, Kyunghoon Jung, Jun-Gyu Kim, Younggun Ko, Keonyong Cheon, Changkeun Yoon, Jiho Kim, Jaehun Jeong, Taehun Myung, Changmin Hong, Weonwi Jang, Min-Chul Sun, Sungil Jo, Ju-Youn Kim, Byungmoo Song, Yuri Yasuda-Masuoka, Ja-Hum Ku, Gitae Jeong |
Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | S. Ko, J. H. Park, J. H. Bak, H. Jung, J. Shim, D. S. Kim, W. Lim, D.-E. Jeong, J. H. Lee, K. Lee, J.-H. Park, Y. Kim, C. Kim, J. H. Jeong, C. Y. Lee, S. H. Han, Y. Ji, S. H. Hwang, H. J. Shin, Y. J. Song, Y. G. Shin, J. H. Song |
Highly Reliable and Manufacturable MRAM embedded in 14nm FinFET node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck |
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Po-Hsuan Chang, Anirban Samanta, Peng Yan, Mingye Fu, Yu Zhang, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, S. J. Ben Yoo, Samuel Palermo |
A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Rishabh Mittal, Hajime Shibata, Sharvil Patil, Erik Krommenhoek, Prawal Shrestha, Gabriele Manganaro, Anantha P. Chandrakasan, Hae-Seung Lee |
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC with Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | N. Jungmann, R. Joshi, E. Kachir, K. Shimanovich, B. He, T. Cohen, T. Miller, D. Leu, Dinesh Kannambadi, I. Wagner, Kenneth Reyer, H. Konen, M. Suleiman, V. Sindhe, Y. Freiman |
A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Fan-Wei Liao, Shan-Chih Tsou, Chien-Sheng Chao |
A 6nW 30.8kHz Relaxation Oscillator with Sampling Bias-Free RC Circuit and Dynamic Power Scaling in a 12nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Milad Haghi Kashani, Hossein Shakiba, Ali Sheikholeslami |
A 0.32pJ/b 90Gbps PAM4 Optical Receiver Front-End with Automatic Gain Control in 12nm CMOS FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Jaehong Jung, Kyungmin Lee, Gunwoo Kong, Baekmin Lim, Seungjin Kim, Seunghyun Oh, Jongwoo Lee |
A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo |
A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Fei Gao 0016, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu 0001, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff |
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-9948-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh, Chen-Yu Hsiao |
A 37.8dB Channel Loss 0.6μs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 116-117, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Henry Park, Mohammed Abdullatif, Ehung Chen, Ahmed Elmallah, Qaiser Nehal, Miguel Gandara, Tsz-Bin Liu, Amr Khashaba, Joonyeong Lee, Chih-Yi Kuan, Dhinessh Ramachandran, Ruey-Bo Sun, Atharav Atharav, Yusang Chun, Mantian Zhang, Deng-Fu Weng, Chung-Hsien Tsai, Chen-Hao Chang, Chia-Sheng Peng, Sheng-Tsung Hsu, Tamer A. Ali 0001 |
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 110-111, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bo Zhang 0029, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao 0001, Afshin Momtaz |
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 108-109, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai, Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang |
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 40-41, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Abhishek Agrawal, Amy Whitcombe, Woorim Shin, Ritesh Bhat, Somnath Kundu, Peter Sagazio, Hariprasad Chandrakumar, Thomas William Brown, Brent R. Carlton, Christopher D. Hull, Steven Callender, Stefano Pellerano |
A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 284-285, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Waqas Gul, Maitham Shams, Dhamin Al-Khalili |
FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Graham Gobieski, Oguz Atli, Cagri Erbagci, Ken Mai, Nathan Beckmann, Brandon Lucia |
MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-4, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bernardo Borges Sandoval, Leonardo Heitich Brendler, Fernanda Lima Kastensmidt, Ricardo Reis 0001, Alexandra L. Zimpeck, Rafael B. Schvittz, Cristina Meinhardt |
Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Anirban Samanta, Po-Hsuan Chang, Peng Yan, Mingye Fu, Mehmet Berkay On, Ankur Kumar, Hyungryul Kang, Il-Min Yi, Dedeepya Annabattuni, Yu Zhang, David Scott, Robert Patti, Yang-Hang Fan, Yuanming Zhu, Samuel Palermo, S. J. Ben Yoo |
A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET with -20.3dBm OMA Sensitivity and 691fJ/bit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2023, San Diego, CA, USA, March 5-9, 2023, pp. 1-3, 2023, IEEE, 978-1-957171-18-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli |
A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 24th IEEE Latin American Test Symposium, LATS 2023, Veracruz, Mexico, March 21-24, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2597-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Devender Pal Singh, Priyanka Yadav, Menka Yadav |
A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2023, Ahmedabad, India, December 18-20, 2023, pp. 109-114, 2023, IEEE, 979-8-3503-8324-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Bashetty Vishnu Vardhan, MD Khadir, Kulkarni Sunnyhith, Sriharsha Paruchuri |
Design and Implementation of Low Power NAND Gate Based Combinational Circuits Using FinFET Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | K. L. V. Ramana Kumari, L. Padma Sree, Penumala Raji |
Design of Dynamic comparator using CMOS and FINFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch |
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2023, Santa Barbara, CA, USA, June 25-28, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-2310-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Matthias Sinnwell, Michael Dammann, Rachid Driad, Sebastian Krause, Stefano Leone, Michael Mikulla, Rüdiger Quay |
Normally-off quasi-vertical GaN FinFET on SiC substrate with record small-signal current gain of $\mathrm{f}_{\mathrm{t}}=10.2$ GHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRC ![In: Device Research Conference, DRC 2023, Santa Barbara, CA, USA, June 25-28, 2023, pp. 1-2, 2023, IEEE, 979-8-3503-2310-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Umme Rani Irin, Sajib Barua, Md Minhajul Azmir, Tasnuva Hassan, Dewan Mohammed |
Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCWC ![In: 13th IEEE Annual Computing and Communication Workshop and Conference, CCWC 2023, Las Vegas, NV, USA, March 8-11, 2023, pp. 928-932, 2023, IEEE, 979-8-3503-3286-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Elif Demirci, Sinem Keles |
Low Voltage FinFET Based OTA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RADIOELEKTRONIKA ![In: 33rd International Conference Radioelektronika, RADIOELEKTRONIKA 2023, Pardubice, Czech Republic, April 19-20, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-9834-2. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala |
A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023, pp. 284-289, 2023, IEEE, 979-8-3503-4678-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Saurabh Goyal, Sanjay Kumar Wadhwa, Divya Tripathi, Gaurav Agrawal, Krishna Thakur, Deependra Kumar Jain, Alvin Leng Sun Loke, Atul Kumar, Manish Kumar Upadhyay, Bhawna, Sanjoy Kumar Dey |
Design Challenges and Techniques for 5nm FinFET CMOS Analog/Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023, pp. 98-103, 2023, IEEE, 979-8-3503-4678-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Vinay Kumar, Vijay Sahu, Ambar Khanda, Sudhir Kumar |
Dynamic Keeper for 1R1W 8T-SRAM to Enable Read Operation at 150c till 0.5v in 5nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023, pp. 163-168, 2023, IEEE, 979-8-3503-4678-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Krishnan Sukumar, Santosh Vodnala, Ravindra Ayyagari, Animesh Jain, Thanapandi Ganesan, Rajesh R |
Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023, pp. 157-162, 2023, IEEE, 979-8-3503-4678-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Jyoti Patel, Govind Sharma, Chitraja Rajan, Vivek Kumar, Sudeb Dasgupta |
Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 90-94, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang |
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 271-275, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Saeid Daneshgar, Hao Li 0047, Taehwan Kim, Ganesh Balamurugan |
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(5), pp. 1397-1408, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | James Bailey 0002, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto |
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(1), pp. 32-43, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Chi Fung Poon, Wenfeng Zhang, Junho Cho, Shaojun Ma, Yipeng Wang 0003, Ying Cao 0010, Asma Laraba, Eugene Ho, Winson Lin, Zhaoyin Daniel Wu, Kee Hian Tan, Parag Upadhyaya, Yohan Frans |
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(4), pp. 1199-1210, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Hao Luo, Somnath Kundu, Timo Huusari, Sarah Shahraini, Eduardo Alban, Jason Mix, Nasser A. Kurd, Mohamed Abdel-Moneum, Brent R. Carlton |
A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(3), pp. 688-697, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Steven Callender, Abhishek Agrawal, Amy Whitcombe, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Christopher D. Hull, Stefano Pellerano |
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(12), pp. 3582-3598, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman |
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(11), pp. 3258-3273, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Jihwan Kim, Sandipan Kundu, Ajay Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyasaachi Keshava Murthy, Priya Wali, Kai Yu 0016, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen 0001, Yoav Segal, Yongping Fan, Peng Li, Frank O'Mahony |
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(1), pp. 6-20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Jih Ren Goh, C. Thomas Gray |
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(10), pp. 2898-2908, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee 0005, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee |
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(12), pp. 3646-3655, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Colin Schmidt 0001, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woorham Bae, Sean Huang, Vladimir M. Milovanovic, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic |
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 57(1), pp. 140-152, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Jani Babu Shaik, Sonal Singhal, Siona Menezes Picardo, Nilesh Goel |
Impact of various NBTI distributions on SRAM performance for FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 83, pp. 60-66, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Fábio G. R. G. da Silva, Rafael N. M. Oliveira, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001 |
Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 87, pp. 137-146, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Johann Knechtel, Tarek Ashraf, Natascha Fernengel, Satwik Patnaik, Mohammed Nabeel 0001, Mohammed Ashraf, Ozgur Sinanoglu, Hussam Amrouch |
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 85, pp. 27-34, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Aram Yousefi, Nima Eslami, Mohammad Hossein Moaiyeri |
A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 105040-105051, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Taeeon Park, Jihwan Kwak, Hongjoon Ahn, Jinwoong Lee, Jaehyuk Lim, Sangho Yu, Changhwan Shin, Taesup Moon |
GAN-Based Framework for Unified Estimation of Process-Induced Random Variation in FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 130001-130023, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Sangho Yu, Sang Min Won, Hyoung Won Baac, Donghee Son, Changhwan Shin |
Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 26340-26346, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Yosef Lempel, Rinat Breuer, Joseph Shor |
A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(2), pp. 248-252, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | T. Venkata Lakshmi, M. Kamaraju |
A Review on SRAM Memory Design Using FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Syst. Dyn. Appl. ![In: Int. J. Syst. Dyn. Appl. 11(6), pp. 1-21, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | D. Ajitha, M. Chandra Sekhar Reddy |
Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(1), pp. 299-320, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Erfan Abbasian, Elangovan Mani, Morteza Gholipour, Mehrzad Karamimanesh, Mohd Sahid, Adil Zaidi |
A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(6), pp. 3081-3105, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Jun Wang, Haozhou Zhu, Yang Yu 0066, Xu Liu, Eryuan Feng, Chuanzhen Lei, Yanfei Cai, Hao Zhu, Qing-Qing Sun, David Wei Zhang |
A Transistor-Level DFF Based on FinFET Technology for Low Power Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(2), pp. 584-588, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Virinchi Roy Surabhi, Prashanth Krishnamurthy, Hussam Amrouch, Jörg Henkel, Ramesh Karri, Farshad Khorrami |
Trojan Detection in Embedded Systems With FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 71(11), pp. 3061-3071, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Mridul Prakash Kashyap, Harshal Gudaghe, Rishu Chaujar |
Compatibility of a Truncated Fin-FinFET as a k-modulated Biosensor with Optimum parameters for Pre-emptive Diagnosis of Diseases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 100, pp. 107850, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Swagat Nanda, Rudra Sankar Dhar |
Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 98, pp. 107687, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Kajal, Vijay Kumar Sharma |
An efficient low power method for FinFET domino OR logic circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 95, pp. 104719, November 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
14 | A. Bernard Rayappa, T. V. P. Sundararajan |
Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(5), pp. 2250080:1-2250080:24, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
Displaying result #101 - #200 of 1191 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ >>] |
|