Search results for "scan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
55	Cheng-Han Tsai, Edward T.-H. Chu, Tai-Yi Huang	WRR-SCAN: a rate-based real-time disk-scheduling algorithm.	EMSOFT	2004	DBLP DOI BibTeX RDF	real-time disk-scheduling, real-time multimedia servers, weighted round-robin
55	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	Asynchronous Scan-Latch controller for Low Area Overhead DFT.	ICCD	2004	DBLP DOI BibTeX RDF
55	Anshuman Chandra, Krishnendu Chakrabarty	Low-power scan testing and test data compression forsystem-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
55	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan Architecture for Shift and Capture Cycle Power Reduction.	DFT	2002	DBLP DOI BibTeX RDF
55	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Scan Power Reduction Through Test Data Transition Frequency Analysis.	ITC	2002	DBLP DOI BibTeX RDF
55	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
55	Frank Poehl, Jan Rzeha, Matthias Beck, Michael Gössel, Ralf Arnold, Peter Ossimitz	On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture.	ETS	2006	DBLP DOI BibTeX RDF
55	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.	ITC	2003	DBLP DOI BibTeX RDF
55	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
52	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Multiple Scan Chains.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	deterministic scan-based BIST, multiple scan paths, parallel scan
52	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with multiple scan chains.	ITC	1998	DBLP DOI BibTeX RDF	deterministic scan-based BIST, multiple scan paths, parallel scan
52	Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar	A critical-path-aware partial gating approach for test power reduction.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	partial gating, scan cell gating, Low-power testing, scan testing
51	Janusz Rajski, Jerzy Tyszer, Nadime Zacharia	Test Data Decompression for Multiple Scan Designs with Boundary Scan.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	reseeding of LFSRs, multiple scan chains, test data decompression, built-in self-test, design for testability, Boundary scan, scan-based designs
51	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Scan-Based Tests with Low Switching Activity.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	scan shift, test response capture, supply current, power dissipation, switching activity, scan-based test
51	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Reducing Average and Peak Test Power Through Scan Chain Modification.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	test power reduction, scan chain modification, average test power, peak test power, scan testing
51	Rajesh Gupta 0003, Melvin A. Breuer	Partial scan design of register-transfer level circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	serial scan design, I-paths, design for testability, register-transfer level designs, balanced structures, partial scan design
51	Johannes Steensma, Francky Catthoor, Hugo De Man	Partial scan and symbolic test at the register-transfer level.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	data path test, partial scan selection, symbolic test pattern generation, partial scan application schemes
51	Ajay Khoche, Erik Brunvand	Testing self-timed circuits using partial scan.	ASYNC	1995	DBLP DOI BibTeX RDF	sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits
51	Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz	A Low Power Pseudo-Random BIST Technique.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	low power, BIST, scan, pseudo-random, peak power
51	Anshuman Chandra, Rohit Kapur	Interval Based X-Masking for Scan Compression Architectures.	ISQED	2008	DBLP DOI BibTeX RDF	X masking, test, compression, DFT, scan
51	Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski	Using a software testing technique to identify registers for partial scan implementation.	SBCCI	2006	DBLP DOI BibTeX RDF	hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
51	Irith Pomeranz	N-detection under transparent-scan.	DAC	2005	DBLP DOI BibTeX RDF	test generation, scan design, n-detection test sets
51	Yu Huang 0005, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy	Synthesis of Scan Chains for Netlist Descriptions at RT-Level.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	scan synthesis, design for testability (DFT), register transfer level (RTL)
51	Ilker Hamzaoglu, Janak H. Patel	Reducing Test Application Time for Full Scan Embedded Cores.	FTCS	1999	DBLP DOI BibTeX RDF	test generation, design-for-testability, fault simulation, embedded cores, full scan
51	Chau-Shen Chen, TingTing Hwang	Layout Driven Selection and Chaining of Partial Scan Flip-Flops.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	design for testability, matching, placement, global routing, partial scan, digital testing, layout optimization
51	Alex Brodsky, Faith Ellen Fich	Efficient synchronous snapshots.	PODC	2004	DBLP DOI BibTeX RDF	multiprocessor algorithms, shared memory objects
50	Juan I. Nieto 0001, Tim Bailey, Eduardo Mario Nebot	Scan-SLAM: Combining EKF-SLAM and Scan Correlation.	FSR	2005	DBLP DOI BibTeX RDF	Simultaneous localisation and mapping (SLAM), EKF-SLAM, scan correlation, Sum of Gaussians (SoG), observation model
50	Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler	Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
50	Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri	Secure Scan: A Design-for-Test Architecture for Crypto Chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
50	Eijiro Takeuchi, Takashi Tsubouchi	A 3-D Scan Matching using Improved 3-D Normal Distributions Transform for Mobile Robotic Mapping.	IROS	2006	DBLP DOI BibTeX RDF
50	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
50	Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic	At-Speed Transition Fault Testing With Low Speed Scan Enable.	VTS	2005	DBLP DOI BibTeX RDF
50	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DATE	2004	DBLP DOI BibTeX RDF
50	Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang	Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
50	Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams	Changing the Scan Enable during Shift.	VTS	2004	DBLP DOI BibTeX RDF
50	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DELTA	2004	DBLP DOI BibTeX RDF
50	Ozgur Sinanoglu, Alex Orailoglu	Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
50	Kohei Miyase, Seiji Kajihara	Optimal Scan Tree Construction with Test Vector Modification for Test Compression.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
50	Nicola Nicolici, Bashir M. Al-Hashimi	Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Digital systems testing, design for test, low power circuits
50	Seongmoon Wang, Sandeep K. Gupta 0001	An automatic test pattern generator for minimizing switching activity during scan testing activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
50	Ranganathan Sankaralingam, Nur A. Touba	Controlling Peak Power During Scan Testing.	VTS	2002	DBLP DOI BibTeX RDF
50	Huan-Chih Tsai, Kwang-Ting Cheng, Sudipta Bhawmik	On improving test quality of scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
50	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee	Test-point insertion: scan paths through functional logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
50	Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano	A Consistent Scan Design System for Large-Scale ASICs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
50	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
49	Dong Xiang, Yang Zhao 0001, Krishnendu Chakrabarty, Hideo Fujiwara	A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
49	Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy	Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.	ISQED	2004	DBLP DOI BibTeX RDF
49	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.	ITC	2003	DBLP DOI BibTeX RDF
49	Irith Pomeranz, Sudhakar M. Reddy	Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
47	Malav Shah	Efficient scan-based BIST scheme for low power testing of VLSI chips.	ISLPED	2006	DBLP DOI BibTeX RDF	test-per-clock, test-per-scan, scan, partial scan, switching activity, test length
47	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
47	Amer El Helwani, Patrice Le Scan	VLSI architecture of the generalized multi delay frequency-domain algorithm for acoustic echo cancellation.	ICASSP	1995	DBLP DOI BibTeX RDF
47	M. Cand, P. Le Scan, A. Roset	An integrated processor for adaptive and parallel algorithms.	ICASSP	1982	DBLP DOI BibTeX RDF
46	Ozgur Sinanoglu	Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Combinational decompressors, Scan cell partitioning, Test data compression, Scan-based testing
46	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
46	Deepak Agarwal, Andrew McGregor 0001, Jeff M. Phillips, Suresh Venkatasubramanian, Zhengyuan Zhu	Spatial scan statistics: approximations and performance study.	KDD	2006	DBLP DOI BibTeX RDF	Kulldorff scan statistic, discrepancy, spatial scan statistics
46	Mehrdad Nourani, Mohammad H. Tehranipour	RL-huffman encoding for test compression and power reduction in scan applications.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Huffman encoding, scan applications, scan-in test power, test pattern compression, power reduction, switching activities, test compression, Compression ratio, run-length encoding, decompression
46	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Partial Scan.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	deterministic scan-based BIST, partial scan
46	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe	Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique.	DATE	1998	DBLP DOI BibTeX RDF	Scan chain selection, RT and gate levels, Partial scan, Synthesis for testability
46	Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara	An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	synchronizable finite state machines, sequential circuits synthesis, extended synchronizing sequence, scan inputs, normal inputs, MCNC'91 benchmark FSM, minimum-length extended synchronizing sequence, test generation, finite state machines, DFT, heuristic algorithm, minimization, partial scan, synthesis for testability, state assignment, state transition, state encoding
46	Jason P. Hurst, Nick Kanopoulos	Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	flip-flop sharing, standard scan path, standard scan path design, two-vector test sets, VLSI, fault diagnosis, logic testing, delays, design for testability, logic design, sequential circuits, sequential circuits, flip-flops, integrated logic circuits, sequential machines, delay fault testing
46	Ajay Khoche, Erik Brunvand	A partial scan methodology for testing self-timed circuits.	VTS	1995	DBLP DOI BibTeX RDF	partial scan methodology, control section testing, macromodule based circuits, sequential network, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault coverage, stuck-at faults, integrated logic circuits, boundary scan testing, self-timed circuits
46	Thomas A. Ziaja, Earl E. Swartzlander Jr.	Boundary scan in board manufacturing.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Board and system test, boundary scan description language, design-for-test, boundary scan
46	Matthew L. Fichtenbaum, Gordon D. Robinson	Scan test architectures for digital board testers.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	tester architecture, scan, boundary scan
46	Chauchin Su, Shyh-Jye Jou	Decentralized BIST Methodology for System Level Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, BIST, DFT, boundary scan
46	Antoni Burguera, Yolanda González Cid, Gabriel Oliver	On the use of likelihood fields to perform sonar scan matching localization.	Auton. Robots	2009	DBLP DOI BibTeX RDF	Likelihood fields, Sonar, Scan matching
46	Sverre Wichlund, Frank Berntsen, Einar J. Aas	Scan Test Response Compaction Combined with Diagnosis Capabilities.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Scan compression, Diagnosis, ATPG, Yield, Design for test, ATE
46	James Chien-Mo Li	Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Fault diagnosis, ATPG, scan chain
46	Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik	Routing-aware scan chain ordering.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	testing, Layout, scan chain
46	Dong Xiang, Janak H. Patel	Partial Scan Design Based on Circuit State Information and Functional Analysis.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Valid state, invalid state, testability improvement potential, conflict, testability measure, partial scan design
46	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A System Level Boundary Scan Controller Board for VME Applications.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	IEEE 1149.1 boundary scan test, board level test and system level test, ATPG
46	Ondrej Novák, Jiri Nosek	Test Pattern Decompression Using a Scan Chain.	DFT	2001	DBLP DOI BibTeX RDF	hardware test pattern generators, BIST, test pattern generation, scan design
46	T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas	Self-Timed Boundary-Scan Cells for Multi-Chip Module Test.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
46	David R. Helman, Joseph F. JáJá	Efficient Image Processing Algorithms on the Scan Line Array Processor.	IEEE Trans. Pattern Anal. Mach. Intell.	1995	DBLP DOI BibTeX RDF	SIMD algorithms, scan line array processors, video procesor, parallel algorithms, Image processing, linear array
46	Ray-I Chang, Wei-Kuan Shih, Ruei-Chuan Chang	Multimedia Real-Time Disk Scheduling by Hybrid Local/Global Seek-Optimizing Approaches.	ICPADS	2000	DBLP DOI BibTeX RDF
45	Paola Flocchini, Andrzej Pelc, Nicola Santoro	Fault-Tolerant Sequential Scan.	Theory Comput. Syst.	2009	DBLP DOI BibTeX RDF
45	Mehdi Salmani Jelodar, Kiarash Mizanian	Power Aware Scan-Based Testing using Genetic Algorithm.	CCECE	2006	DBLP DOI BibTeX RDF
45	Martin E. Dyer, Leslie Ann Goldberg, Mark Jerrum	Dobrushin Conditions and Systematic Scan.	APPROX-RANDOM	2006	DBLP DOI BibTeX RDF
45	Vandana Pursnani Janeja, Vijayalakshmi Atluri	FS3: A Random Walk Based Free-Form Spatial Scan Statistic for Anomalous Window Detection.	ICDM	2005	DBLP DOI BibTeX RDF
45	Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha	A low-power scan-path architecture.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
45	Min-Hao Chiu, Chien-Mo James Li	Jump Scan: A DFT Technique for Low Power Testing.	VTS	2005	DBLP DOI BibTeX RDF
45	Andreas Leininger, Michael Gössel, Peter Muhmenthaler	Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code.	DATE	2004	DBLP DOI BibTeX RDF
45	Md. Saffat Quasem, Sandeep K. Gupta 0001	Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip.	VTS	2004	DBLP DOI BibTeX RDF
45	Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch	Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.	DATE	2003	DBLP DOI BibTeX RDF
45	Irith Pomeranz, Sudhakar M. Reddy	A New Approach to Test Generation and Test Compaction for Scan Circuits.	DATE	2003	DBLP DOI BibTeX RDF
45	Md. Saffat Quasem, Sandeep K. Gupta 0001	Designing Multiple Scan Chains for Systems-on-Chip.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
45	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage.	ICCAD	2003	DBLP DOI BibTeX RDF
45	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
45	Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams	A Reconfigurable Shared Scan-in Architecture.	VTS	2003	DBLP DOI BibTeX RDF
45	Ozgur Sinanoglu, Alex Orailoglu	A novel scan architecture for power-efficient, rapid test.	ICCAD	2002	DBLP DOI BibTeX RDF
45	Yannick Bonhomme, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Power Driven Chaining of Flip-Flops in Scan Architectures.	ITC	2002	DBLP DOI BibTeX RDF
45	Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.	FPL	2001	DBLP DOI BibTeX RDF
45	Sunggu Lee, Kang G. Shin	Design for test using partial parallel scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
45	George F. Corliss	SCAN-98 Collected Bibliography.	SCAN	1998	DBLP DOI BibTeX RDF
44	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.	VLSI Design	2007	DBLP DOI BibTeX RDF
44	Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.	IOLTS	2006	DBLP DOI BibTeX RDF
44	Nabil Badereddine, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
44	Yu Hu 0001, Xiaowei Li 0001, Huawei Li 0001, Xiaoqing Wen	Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.	PRDC	2005	DBLP DOI BibTeX RDF
44	Chunsheng Liu, Krishnendu Chakrabarty	Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
44	Irith Pomeranz, Sudhakar M. Reddy	On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.	ICCD	2004	DBLP DOI BibTeX RDF