Search results for "FinFET"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera	NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Bahareh Seyedzadeh Sany, Behzad Ebrahimi	A 1-GHz GC-eDRAM in 7-nm FinFET with static retention time at 700 mV for ultra-low power on-chip memory applications.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
14	Damodhar Rao M., Y. V. Narayana, V. V. K. D. V. Prasad	Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells.	Sustain. Comput. Informatics Syst.	2022	DBLP DOI BibTeX RDF
14	Shelja Kaushal, Ashwani K. Rana	Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad	On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Erfan Abbasian, Shilpi Birla, Morteza Gholipour	Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Rajeewa Kumar Jaisawal, P. N. Kondekar, Sameer Yadav, Pranshoo Upadhyay, Bhaskar Awadhiya, Sunil Rathore	Insights into the operation of negative capacitance FinFET for low power logic applications.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Zhaoqing Wang, Lan Chen, Minghui Yin	Analysis and characterization of layout dependent effect for advance FinFET circuit design.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Libo Zheng, Qiuliang Li, Haowei Xie, Yufeng Guo, Yi Liu	A low power broadband LC-VCO using high quality-factor multi-path stacked inductors in 14-nm FinFET.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Epiphany Jebamalar Leavline, Somasekaran Sujitha	Design of FinFET based low power, high speed hybrid decoder for SRAM.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Xinlong Shi, Huiyong Hu, Ying Wang, Liming Wang, Ningning Zhang, Bin Wang, Maolong Yang, Lingyao Meng	A comparative study on performance of junctionless Bulk SiGe and Si FinFET.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
14	Dhandeep Challagundla, Mehedi Galib, Ignatius Bezzam, Riadul Islam	Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks.	CoRR	2022	DBLP DOI BibTeX RDF
14	G. Vidhya Sagar, D. Vijayakumar	Simulation based study on parameter variation of Si0.9Ge0.1 junction-less SELBOX FinFET for high-performance application.	Comput. Intell.	2022	DBLP DOI BibTeX RDF
14	Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda	A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers.	HCS	2022	DBLP DOI BibTeX RDF
14	Zsolt Tokei	Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene.	FPGA	2022	DBLP DOI BibTeX RDF
14	H. Zheng, Y. S. Sun, J. L. Huang	Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking.	IRPS	2022	DBLP DOI BibTeX RDF
14	Nicholas J. Pieper, Yoni Xiong, Alexandra Feeley, Dennis R. Ball, Bharat L. Bhuva	Single-Event Latchup Vulnerability at the 7-nm FinFET Node.	IRPS	2022	DBLP DOI BibTeX RDF
14	Taiki Uemura, Byungjin Chung, Jegon Kim, Hyewon Shim, Shin-Young Chung, Brandon Lee, Jaehee Choi, Shota Ohnishi, Ken Machida	Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology.	IRPS	2022	DBLP DOI BibTeX RDF
14	Yoni Xiong, Alexandra Feeley, Nicholas J. Pieper, Dennis R. Ball, Balaji Narasimham, John Brockman, N. A. Dodds, S. A. Wender, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva	Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment.	IRPS	2022	DBLP DOI BibTeX RDF
14	Md Iqbal Mahmud, Rakesh Ranjan, Ki-Don Lee, Pavitra Ramadevi Perepa, Caleb Dongkyun Kwon, Seungjin Choo, Kihyun Choi	Reverse Body Bias Dependence of HCI Reliability in Advanced FinFET.	IRPS	2022	DBLP DOI BibTeX RDF
14	P. S. Chen, Y. W. Lee, D. S. Huang, S. C. Chen, C. F. Cheng, J. H. Lee, Jun He	AC TDDB Analysis for HK/IL Gate Stack Breakdown and Frequency-dependent Oxygen Vacancy Trap Generation in Advanced nodes FinFET Devices by SILC Spectrum Methodology.	IRPS	2022	DBLP DOI BibTeX RDF
14	Yanshul Sharma, Sanjay Moulik, Shounak Chakraborty 0001	RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore.	DATE	2022	DBLP DOI BibTeX RDF
14	Shayesteh Masoumian, Georgios N. Selimis, Rui Wang, Geert Jan Schrijen, Said Hamdioui, Mottaqiallah Taouil	Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology Nodes.	DATE	2022	DBLP DOI BibTeX RDF
14	Hao Chen 0059, Walker J. Turner, David Z. Pan, Haoxing Ren	Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories.	DATE	2022	DBLP DOI BibTeX RDF
14	Jan Lappas, André Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn	Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node.	DATE	2022	DBLP DOI BibTeX RDF
14	Mohamed Saleh Abouelyazid, Sherif Hammouda, Yehea Ismail	A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning.	ASP-DAC	2022	DBLP DOI BibTeX RDF
14	Seungju Hwang, Ilgu Yun	Self-heating effect of GAAFET and FinFET for over 2-V applications using TCAD simulation.	ICEIC	2022	DBLP DOI BibTeX RDF
14	Ariana Musello, Santiago S. Pérez, Marco Villegas, Luis-Miguel Prócel, Ramiro Taco, Lionel Trojman	Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells.	LASCAS	2022	DBLP DOI BibTeX RDF
14	André Lucas Chinazzo, Jan Lappas, Christian Weis, Qinhui Huang, Zhihang Wu, Leibin Ni, Norbert Wehn	Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology.	ICECS 2022	2022	DBLP DOI BibTeX RDF
14	Hao Chen 0059, Walker J. Turner, Sanquan Song, Keren Zhu 0001, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren	AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.	ISPD	2022	DBLP DOI BibTeX RDF
14	Pietro Caragiulo, Athanasios Ramkaj, Amin Arbabian, Boris Murmann	A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS.	ESSCIRC	2022	DBLP DOI BibTeX RDF
14	Staffan Ek, Patrik Karlsson, Andreas Kämpe, Roland Strandberg, Aravind Tharayil Narayanan, Martin Anderson, Hind Dafallah, Mesrop Daghbashyan, Tayebeh Ghanavati Nejad, Robert Hägglund, Nikola Ivanisevic, Robert Nilsson, Peter Nygren, Mattias Palm, Erik Säll, Sha Tao, My-Chien Yee, Lars Sundström	A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology.	ESSCIRC	2022	DBLP DOI BibTeX RDF
14	Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee	A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET.	ESSCIRC	2022	DBLP DOI BibTeX RDF
14	Sajjad Rostami Sani, Anas Razzaq, Andy Gean Ye	Evaluating the impact of using multiple-metal layers on the layout area of switch blocks for tile-based FPGAs in FinFET 7nm.	FCCM	2022	DBLP DOI BibTeX RDF
14	Guofu Niu	Physics, Characterization and Modeling of RF Linearity in SiGe HBT and FinFET Technologies.	BCICTS	2022	DBLP DOI BibTeX RDF
14	Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos	A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Rajiv V. Joshi, John Timmerwilke, Kevin Tien, Mark Yeck, Sudipto Chakraborty	A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Byeongwoo Koo, Sunghan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho, Michael Choi, Jongshin Shin	A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Kyoung-Jun Moon, Dong-Ryeol Oh, Young-Hyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyo-Chul Shin, Young-Jae Cho, Michael Choi, Jongshin Shin	A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Nail Etkin Can Akkaya, Gary Chan, Hung-Jen Liao, Yih Wang, Jonathan Chang	A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw	A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi	Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Bernhard Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang, D. Basu, S. Bendapudi, D. Bergstrom, R. Bhandavat, S. Bhowmick, M. Buehler, D. Caselli, S. Cekli, Vrsk. Chaganti, Y. J. Chang, K. Chikkadi, T. Chu, T. Crimmins, G. Darby, C. Ege, P. Elfick, Tyler Elko-Hansen, S. Fang, C. Gaddam, M. Ghoneim, H. Gomez, S. Govindaraju, Z. Guo, Walid M. Hafez, M. Haran, M. Hattendorf, S. Hu, A. Jain, S. Jaloviar, M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy, S. Klopcic, D. Krishnan, J. Leib, Y.-T. Lin, N. Lindert, G. Liu, O. Loh, Y. Luo, S. Mani, M. Mleczko, S. Mocherla, P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar, L. Pipes, P. Plekhanov, Chetan Prasad, M. Prince, G. Ramalingam, R. Ramaswamy, J. Riley, J. R. Sanchez Perez, Justin Sandford, A. Sathe, F. Shah, H. Shim, S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta, T. Troeger, X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu, P. Yashar, J. Yaung, K. Yoon, N. Young	Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Jin Luo, Weikai Xu, Boyi Fu, Zheru Yu, Mengxuan Yang, Yiqing Li, Qianqian Huang, Ru Huang	A Novel Ambipolar Ferroelectric Tunnel FinFET based Content Addressable Memory with Ultra-low Hardware Cost and High Energy Efficiency for Machine Learning.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Jaehoon Lee 0005, Yong Lim, Jongmi Lee, Taejin Jang, Kwonwoo Kang, Jongpil Cho, Seunghyun Oh, Jongwoo Lee	A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier	A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert	Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray	An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin	A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Jyothi Bhaskarr Velamala, Siang-jhih Sean Wu, Padma Penmatsa, Kuan-Yueh James Shen, David Johnston, Rachael J. Parker	PVT Tolerant Zero Bit-Error-Rate Physical Unclonable Function Exploiting Hot Carrier Injection Aging in 7nm FinFET Technology.	CICC	2022	DBLP DOI BibTeX RDF
14	Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, II-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo	A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET.	CICC	2022	DBLP DOI BibTeX RDF
14	Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, II-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo	A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET.	CICC	2022	DBLP DOI BibTeX RDF
14	Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang 0029, Afshin Momtaz	An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Christopher Schaef, Tamir Salus, Rachid Rayess, Siddarth Kulasekaran, Mat Manusharow, Kaladhar Radhakrishnan, Jonathan Douglas	A IMax \|max, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in 4nm Class FinFET CMOS.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull	A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Jiang Gong, Bishnu Patra, Luc Enthoven, Job van Staveren, Fabio Sebastiano, Masoud Babaie	A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMA in 22nm FinFET.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Z. Guo, A. Mostafa, A. Elshazly, B. Chen, B. Wang, C. Han, C. Wang, D. Zhou, D. Visani, E. Hsiao, F. Chu, F. Lu, G. Cui, H. Zhang, H. Wang, H. Zhao, J. Lin, J. Gu, L. Luo, L. Jiang, M. Singh, M. Gambhir, M. Hasan, M. Wu, M. J. Yoo, P. Liu, S. Kollu, T. Ye, X. Zhao, X. Yang, X. Han, Y. Huang, Y. Sun, Z. Yu, Z. H. Jiang, Z. Adal, Z. Yan	A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET.	ISSCC	2022	DBLP DOI BibTeX RDF
14	David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman	A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Amit Kumar Mishra, Yifei Li, Pawan Agarwal, Sudip Shekhar	A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin	A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Barosaim Sung, Hyun-Gi Seok, Jaekwon Kim, Jaehoon Lee 0005, Taejin Jang, Ilhoon Jang, Youngmin Kim, Anna Yu, Jong-Hyun Jang, Jiyoung Lee, Jeongyeol Bae, Euiyoung Park, Sung-Jun Lee, Seokwon Lee, Joohan Kim, Beomkon Kim, Yong Lim, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho, Inyup Kang	A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Somnath Kundu, Timo Huusari, Hao Luo, Abhishek Agrawal, Eduardo Alban, Sarah Shahraini, Thao Xiong, Dan Lake, Stefano Pellerano, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton	A 2-to-2.48GHz Voltage-Interpolator-Based Fractional-N Type-I Sampling PLL in 22nm FinFET Assisting Fast Crystal Startup.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Shounak Chakraborty 0001, Vassos Soteriou, Magnus Själander	STIFF: thermally safe temperature effect inversion aware FinFET based multi-core.	CF	2022	DBLP DOI BibTeX RDF
14	Ping Lu, Charlie Boecker, Bupesh Pandita, Minhan Chen, Sheethal Nayak	A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Chang Xue, Yihan Zhang 0002, Peiyu Chen, Mingwei Zhu, Tianqiao Wu, Meng Wu, Yandong He, Le Ye	Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET.	ISCAS	2022	DBLP DOI BibTeX RDF
14	David Dolt, Quintin Livingston, Tong Liu, Ankur Kumar, Samuel Palermo	SEE Sensitivity of a 16GHz LC-Tank VCO in a 22nm FinFET Technology.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Dhandeep Challagundla, Mehedi Galib, Ignatius Bezzam, Riadul Islam	Power and Skew Reduction Using Resonant Energy Recycling in 14-nm FinFET Clocks.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas 0001, Jaume Segura 0001	Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations.	LATS	2022	DBLP DOI BibTeX RDF
14	Semiu A. Olowogemo, Hao Qiu, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick	Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies.	DFT	2022	DBLP DOI BibTeX RDF
14	Devender Pal Singh, Menka Yadav	Performance Analysis of Junctionless and Inversion Mode Trigate SOI FinFET at 20nm Gate Length.	iSES	2022	DBLP DOI BibTeX RDF
14	Yuan Lou, Lijun Zhang, Yuling Yan, Lijun Ma, Zhongda Zhang	Two-stage Pipelined SRAM Design Based on 14nm FinFET Process.	EITCE	2022	DBLP DOI BibTeX RDF
14	Mahta Mayahinia, Mehdi B. Tahoori, Gurgen Harutyunyan, Grigor Tshagharyan, Karen Amirkhanyan	An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories.	ITC	2022	DBLP DOI BibTeX RDF
14	Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga	Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α).	VDAT	2022	DBLP DOI BibTeX RDF
14	Kun-Da Chu, Steven Callender, Yanjie Wang, Jacques Christophe Rudell, Stefano Pellerano, Christopher D. Hull	A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm Psat and 26.5% PAE in 16-nm FinFET CMOS.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai	ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal 0001, Monodeep Kar, Seongjong Kim, Mark A. Anders 0001, Himanshu Kaul, Ram K. Krishnamurthy	A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Eric Groen, Charlie Boecker, Masum Hossain, Roxanne Vu, Socrates D. Vamvakos, Haidang Lin, Simon Li, Marcus van Ierssel, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Mohammad Hossein Taghavi, Kulwant Brar, Nhat Nguyen, Shaishav Desai	10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet	A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li	A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton	A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Jay Im, Kevin Zheng, Chuen-Huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang 0003, Hao-Wei Hung, Kee Hian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao 0010, David Mahashin, Hong Ahn, Hongtao Zhang 0002, Yohan Frans, Ken Chang	A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Pietro Caragiulo, Oscar Elisio Mattia, Amin Arbabian, Boris Murmann	A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm2 Switched-Capacitor DAC in 16-nm FinFET CMOS.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Endri Taka, Konstantinos Maragos 0001, George Lentaris, Dimitrios Soudris	Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2021	DBLP DOI BibTeX RDF
14	Yan Zheng, Jingchao Lan, Fan Ye 0001, Junyan Ren	A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET.	IEEE Access	2021	DBLP DOI BibTeX RDF
14	Jaehyuk Lim, Jinwoong Lee, Changhwan Shin	Probabilistic Artificial Neural Network for Line-Edge-Roughness-Induced Random Variation in FinFET.	IEEE Access	2021	DBLP DOI BibTeX RDF
14	Amin A. Zayed, Hanady Hussien Issa, Khaled A. Shehata, Hani Fikry Ragai	Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET.	IEEE Access	2021	DBLP DOI BibTeX RDF
14	Guilherme Cardoso Medeiros, Moritz Fieback, Lizhou Wu, Mottaqiallah Taouil, Letícia Maria Bolzani Poehls, Said Hamdioui	Hard-to-Detect Fault Analysis in FinFET SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
14	Ehsan Panahifar, Alireza Hassanzadeh	DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
14	Pengcheng Huang, Chiyuan Ma, Zhenyu Wu	Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies.	Symmetry	2021	DBLP DOI BibTeX RDF
14	Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski	A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
14	Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng	A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
14	Sarika Madhukar Jagtap, Vitthal Janardan Gond	Performance Parameter Evaluation of 7nm FinFET by Tuning Metal Work Function and High K Dielectrics.	Int. J. Nat. Comput. Res.	2021	DBLP DOI BibTeX RDF
14	Vijay Kumar Sharma	A Novel Low Power Technique for FinFET Domino OR Logic.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
14	Víctor H. Champac, Javier Mesalles, Hector Villacorta, Fabian Vargas 0001	Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF
14	Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Letícia Maria Bolzani Poehls, Tiago Roberto Balen	Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.	J. Electron. Test.	2021	DBLP DOI BibTeX RDF
14	T. Santosh Kumar, Suman Lata Tripathi	Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique.	Wirel. Pers. Commun.	2021	DBLP DOI BibTeX RDF
14	Rinku Rani Das, Santanu Maity, Atanu Chowdhury, Apurba Chakraborty	RF/Analog performance of GaAs Multi-Fin FinFET with stress effect.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14	Mehrzad Karamimanesh, Ebrahim Abiri, Kourosh Hassanli, Mohammad Reza Salehi, Abdolreza Darabi	A robust and write bit-line free sub-threshold 12T-SRAM for ultra low power applications in 14 nm FinFET technology.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14	Vinay Vashishtha, Lawrence T. Clark	Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14	Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury	FinFET based SRAMs in Sub-10nm domain.	Microelectron. J.	2021	DBLP DOI BibTeX RDF