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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2833 occurrences of 878 keywords
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Results
Found 2210 publication records. Showing 2210 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
35 | Krishna B. Rajan, David E. Long, Miron Abramovici |
Increasing testability by clock transformation (getting rid of those darn states). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 224-230, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning |
35 | Rohit Kapur, M. Ray Mercer |
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(12), pp. 1580-1588, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
bounding algorithm, circuit faults, conditional syndromes, auxiliary gate, pseudorandom pattern resistant faults, circuit structure, computational complexity, lower bounds, built-in self test, integrated circuit testing, circuit analysis computing, signal probabilities, testability measurement, random pattern testability |
35 | Anastasios Vergis, Kenneth Steiglitz |
Testability Conditions for Bilateral Arrays of Combinational Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(1), pp. 13-22, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
testability conditions, Bilateral arrays, combinational cells, linear growth, one-step testability, preset test sequences, quadratic growth, fault detection, systolic array |
34 | Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell |
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(1), pp. 9-16, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
testability evaluation, design-for-test, analog and mixed-signal testing |
34 | Roger T. Alexander, James M. Bieman, Sudipto Ghosh, Bixia Ji |
Mutation of Java Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 13th International Symposium on Software Reliability Engineering (ISSRE 2002), 12-15 November 2002, Annapolis, MD, USA, pp. 341-351, 2002, IEEE Computer Society, 0-7695-1763-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Java, software testing, object-oriented programming, testability, Faults, mutation analysis, test adequacy |
34 | Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao |
Easily Testable Data Path Allocation Using Input/Output Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 142-, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design |
34 | Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik |
Integration of partial scan and built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 125-137, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
test points, built-in self-test, design for testability, partial scan |
34 | Sujit Dey, Srimat T. Chakradhar |
Design of testable sequential circuits by repositioning flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 105-114, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault |
34 | Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer |
On testable multipliers for fixed-width data path architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 541-547, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability |
32 | Phil McMinn, David W. Binkley, Mark Harman |
Empirical evaluation of a nesting testability transformation for evolutionary testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Softw. Eng. Methodol. ![In: ACM Trans. Softw. Eng. Methodol. 18(3), pp. 11:1-11:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
testability transformation, test data generation, Evolutionary testing, search-based software engineering |
32 | Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001 |
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(6), pp. 1037-1046, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microprocessor design-for-testability, built-in self-test, test generation, at-speed testing |
32 | Teemu Kanstrén |
A Study on Design for Testability in Component-Based Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SERA ![In: Proceedings of the 6th ACIS International Conference on Software Engineering Research, Management and Applications, SERA 2008, 20-22 August 2008, Prague, Czech Republic, pp. 31-38, 2008, IEEE Computer Society, 978-0-7695-3302-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
testing, components, design for testability, embedded software |
32 | Hao-Chiao Hong |
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 527-538, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Design-for-digital-testability, Stimulus evaluation, ?-? modulator, Behavioral model |
32 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 125-142, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function |
32 | Barbara Cannas, Alessandra Fanni, Stefano Manetti, Augusto Montisci, Maria Cristina Piccirilli |
Neural network-based analog fault diagnosis using testability analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 13(4), pp. 288-298, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Neural networks, Diagnosis, Analog circuits, Testability analysis |
32 | Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni |
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 133-142, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Radio Frequency (RF) Testing, Design for Testability (DFT), Voltage Controlled Oscillator (VCOs) |
32 | André Baresel, David W. Binkley, Mark Harman, Bogdan Korel |
Evolutionary testing in the presence of loop-assigned flags: a testability transformation approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2004, Boston, Massachusetts, USA, July 11-14, 2004, pp. 108-118, 2004, ACM, 1-58113-820-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
flags, testability transformation, empirical evaluation, evolutionary testing |
32 | Cecilia Metra, T. M. Mak, Martin Omaña 0001 |
Fault secureness need for next generation high performance microprocessor design for testability structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 444-450, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
built in self test, design for testability, microprocessor, comparator, fault secureness |
32 | Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev |
Design for Delay Testability in High-Speed Digital ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(3-4), pp. 225-231, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
BIST, delay-fault testing, design for delay testability, high-speed testing |
32 | Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda |
High speed IDDQ test and its testability for process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 344-349, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing |
32 | Ayoob E. Dooply, Kenneth Y. Yun |
Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 200-214, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault |
32 | Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang |
Novel Design for Testability of a Mixed-Signal VLSI IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 97-100, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Mixed-signal VLSI, verification, microprocessor, testability, RF |
32 | Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti |
A System for Evaluating On-Line Testability at the RT-level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 284-291, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Testability estimation, On-line testing, Design exploration |
32 | Yervant Zorian |
Fundamentals of MCM Testing and Design-for-Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(1-2), pp. 7-14, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
known good dies, design-for-testability, MCM testing |
32 | Joan Carletta, Christos A. Papachristou |
Behavioral Testability Insertion for Datapath/Controller Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 9-28, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
behavioral testability analysis, BIST, test synthesis |
32 | Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto |
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 112-115, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Delay Test Generation, Design for Testability, Delay Testing |
32 | Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida |
Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 122-125, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
core test, design-for-testability, BIST, scan, boundary scan, test bus |
32 | Jacob Savir |
Random pattern testability of memory control logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 399-409, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
embedded memory control logic, exposure probability, fault detection, integrated memory circuits, signal probability, random pattern testability |
32 | Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth |
Synthesis for Testability by Two-Clock Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 279-283, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph |
32 | Chien-Chung Tsai, Malgorzata Marek-Sadowska |
Logic Synthesis for Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 118-121, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Fixed-Polarity Reed-Muller Forms, Logic synthesis, Testability |
32 | Jeffrey M. Voas, Jeffery E. Payne, R. Mills, John McManus |
Software Testability: An Experiment in Measuring Simulation Reusability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSR ![In: Proceedings of the ACM SIGSOFT Symposium on Software Reusability, SSR@ICSE 1995, April 23-30, 1995, Seattle, WA, USA, pp. 247-255, 1995, ACM, 0-89791-739-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
software testability, software testing, software reusability |
32 | Joan Carletta, Christos A. Papachristou |
Testability analysis and insertion for RTL circuits based on pseudorandom BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 162-167, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits |
32 | Prab Varma, Tushar Gheewala |
The economics of scan-path design for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(2-3), pp. 179-193, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs |
32 | Dhamin Al-Khalili, Côme Rozon, B. Stewart |
Testability analysis and fault modeling of BiCMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 207-217, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
modeling, testability, faults, defects, BiCMOS |
32 | Bernd Becker 0001 |
Synthesis for Testability: Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 92, 9th Annual Symposium on Theoretical Aspects of Computer Science, Cachan, France, February 13-15, 1992, Proceedings, pp. 501-512, 1992, Springer, 3-540-55210-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures |
32 | Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda |
Exact probabilistic testability measures for multi-output circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 1(3), pp. 229-234, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
probabilistic testability analysis, Built-in self-test, test-pattern generation, CAD tools |
32 | Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker |
Design-for-testability of PLA's using statistical cooling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 339-345, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
PLA testing, statistical cooling, design-for-testability, PLA |
30 | Kaarina Karppinen, Lyly Yonkwa, Mikael Lindvall |
Why Developers Insert Security Vulnerabilities into Their Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACHI ![In: Second International Conference on Advances in Computer-Human Interaction, ACHI 2009, February 1-7, 2009, Cancun, Mexico, pp. 289-294, 2009, IEEE, 978-0-7695-3529-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre |
Securing Scan Control in Crypto Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(5), pp. 457-464, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Crypto-chips, Security, Scan |
30 | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
A DFT Method for Time Expansion Model at Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 682-687, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Petros Oikonomakos, Mark Zwolinski |
An Integrated High-Level On-Line Test Synthesis Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2479-2491, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri |
Secure Scan: A Design-for-Test Architecture for Crypto Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2287-2293, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Sami Beydeda |
Self-Metamorphic-Testing Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC (2) ![In: 30th Annual International Computer Software and Applications Conference, COMPSAC 2006, Chicago, Illinois, USA, September 17-21, 2006. Volume 2, pp. 265-272, 2006, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir |
A novel improvement technique for high-level test synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 609-612, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Shyue-Kung Lu, Chien-Hung Yeh |
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 230-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Stefan Jungmayr |
Identifying Test-Critical Dependencies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 18th International Conference on Software Maintenance (ICSM 2002), Maintaining Distributed Heterogeneous Systems, 3-6 October 2002, Montreal, Quebec, Canada, pp. 404-413, 2002, IEEE Computer Society, 0-7695-1819-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Lionel C. Briand, Yvan Labiche |
A UML-Based Approach to System Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UML ![In: «UML» 2001 - The Unified Modeling Language, Modeling Languages, Concepts, and Tools, 4th International Conference, Toronto, Canada, October 1-5, 2001, Proceedings, pp. 194-208, 2001, Springer, 3-540-42667-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi |
Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 161-169, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Dong Xiang, Yi Xu |
Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 82-87, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara |
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 5-12, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Sandeep Bhatia, Niraj K. Jha |
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 608-619, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Katzalin Olcoz, Francisco Tirado |
Register Allocation with Simultaneous BIST Intrusio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10099-10106, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Gwo-Haur Hwang, Wen-Zen Shen |
Restructuring and logic minimization for testable PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 488-496, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Srinivas Devadas, Kurt Keutzer |
Validatable nonrobust delay-fault testable circuits via logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(12), pp. 1559-1573, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
29 | Eliane Martins, Cristina Maria Toyota, Rosileny Lie Yanagawa |
Constructing Self-Testable Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 1-4 July 2001, Göteborg, Sweden, Proceedings, pp. 151-160, 2001, IEEE Computer Society, 0-7695-1101-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
component testability, self-testable component, OO testing, design for testability |
29 | Michael J. Liebelt, Cheng-Chew Lim |
A method for determining whether asynchronous circuits are self-checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 472-477, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise |
29 | Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu |
DFT closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 8-9, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability |
29 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis |
C-Testable modified-Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 241-260, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model |
29 | Roberto Bevacqua, Luca Guerrazzi, Franco Fummi |
SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 351-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences |
29 | Seiken Yano |
Unified scan design with scannable memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 153-159, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits |
29 | Mohamed Soufi, Yvon Savaria, Bozena Kaminska |
On the design of at-speed testable VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 290-295, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique |
29 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
29 | U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta |
PLA based synthesis and testing of hazard free logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 121-124, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions |
29 | Elizabeth M. Rudnick, Janak H. Patel |
A genetic approach to test application time reduction for full scan and partial scan circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 288-293, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits |
29 | Tak-Yung Kim, Taewhan Kim |
Clock tree synthesis with pre-bond testability for 3D stacked IC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 723-728, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
optimization, routing, buffer insertion, 3D ICs, clock tree |
29 | Tao Niu, Yingjiao Zhang, Debo Zhang, Liqiang Liu, Xianjue Luo |
Testability Analysis of Grounding Grids Using Network Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAS ![In: Proceedings of the Fifth International Conference on Information Assurance and Security, IAS 2009, Xi'An, China, 18-20 August 2009, pp. 589-592, 2009, IEEE Computer Society, 978-0-7695-3744-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Ismael Rodríguez |
A General Testability Theory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR 2009 - Concurrency Theory, 20th International Conference, CONCUR 2009, Bologna, Italy, September 1-4, 2009. Proceedings, pp. 572-586, 2009, Springer, 978-3-642-04080-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1535-1544, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Kazuteru Namba, Hideo Ito |
Delay Fault Testability on Two-Rail Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 482-490, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Sying-Jyan Wang, Tung-Hua Yeh |
High-level test synthesis for delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 45-50, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang |
An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 255-258, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Thomas W. Williams |
Design for Testability: The Path to Deep Submicron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Bogdan Korel, Mark Harman, S. Chung, P. Apirukvorapinit, Rajiv Gupta 0001, Q. Zhang |
Data Dependence Based Testability Transformation in Automated Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 16th International Symposium on Software Reliability Engineering (ISSRE 2005), 8-11 November 2005, Chicago, IL, USA, pp. 245-254, 2005, IEEE Computer Society, 0-7695-2482-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Mansour H. Assaf, Sunil R. Das, Emil M. Petriu, Mehmet Sahinoglu |
Enhancing Testability in Architectural Design for the New Generation of Core-Based Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 8th IEEE International Symposium on High-Assurance Systems Engineering (HASE 2004), 25-26 March 2004, Tampa, FL, USA, pp. 312-313, 2004, IEEE Computer Society, 0-7695-2094-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Y. S. Son, Jong Whoa Na |
A New Logic Transformation Method for Both Low Power and High Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 770-779, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Sule Ozev, Alex Orailoglu |
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 72-77, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Troy Lamoreaux, Mark Ofori-Kyei, Mark Pinone |
A Process for Improving Software Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 20th International Conference on Software Maintenance (ICSM 2004), 11-17 September 2004, Chicago, IL, USA, pp. 502, 2004, IEEE Computer Society, 0-7695-2213-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir |
Testability Improvement During High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 505, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Junhao Shi, Görschwin Fey, Rolf Drechsler |
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 290-293, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Avraham Trakhtman |
Reducing the Time Complexity of Testing for Local Threshold Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 8th International Conference, CIAA 2003, Santa Barbara, California, USA, July 16-18, 2003, Proceedings, pp. 141-149, 2003, Springer, 3-540-40561-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
threshold locally testable, algorithm, graph, Automaton |
29 | Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li 0001 |
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 53-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Jonathan Vincent, Graham King, Peter Lay, John Kinghorn |
Principles of Built-In-Test for Run-Time-Testability in Component-Based Software Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 10(2), pp. 115-133, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
continuous test, component based software engineering, built-in-test, verification and validation |
29 | Jin-Cherng Lin, Szu-Wen Lin |
An Analytic Software Testability Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 278-283, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Andrzej Krasniewski |
Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 310-317, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara |
Design for Hierarchical Two-Pattern Testability of Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 11-16, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Kelly A. Ockunzzi, Christos A. Papachristou |
Breaking Correlation to Improve Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 75-81, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
BIST, DFT, Test Synthesis |
29 | Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst |
Tools for the Characterization of Bipolar CML Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 388-395, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
IFA, Automatic characterization, Fault-Modeling, CML |
29 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8), pp. 894-906, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Susanta Chakrabarti, Sandip Das 0001, Debesh Kumar Das, Bhargab B. Bhattacharya |
Synthesis of symmetric functions for path-delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9), pp. 1076-1081, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Synthesis-for-testability of controller-datapath pairs that use gated clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 613-618, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Jacob Savir |
Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(3), pp. 279-296, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
exposure probability, escape probability, Markov chain, detection probability, signal probability, random patterns |
29 | A. N. Trahtman |
An Algorithm to Verify Local Threshold Testability of Deterministic Finite Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WIA ![In: Automata Implementation, 4th International Workshop on Implementing Automata, WIA'99, Potsdam, Germany, July 17-19, 1999, Revised Papers, pp. 164-173, 1999, Springer, 3-540-42812-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
locally threshold testable, semigroup AMS subject classification 68Q25, 68Q68, 20M07, algorithm, deterministic finite automaton, 68Q45 |
29 | Mostafa I. H. Abd-El-Barr, Maher Al-Sherif, Mohamed Osman |
Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 262-267, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 398-406, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Susanta Chakraborty, Sandip Das 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Synthesis of Symmetric Functions for Path-Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 512-517, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto |
Testability analysis and behavioral testing of the Hopfield neural paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 507-511, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
A controller redesign technique to enhance testability of controller-data path circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2), pp. 157-168, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Irith Pomeranz, Sudhakar M. Reddy |
Design-for-testability for path delay faults in large combinational circuits using test points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4), pp. 333-343, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
29 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1514-1521, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Junji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok |
Testability Features of R10000 Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 108-111, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Lfsr, Observability Register, Clock Stretch, Fault Simulation, Memory Test |
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