Search results for "Testability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
35	Krishna B. Rajan, David E. Long, Miron Abramovici	Increasing testability by clock transformation (getting rid of those darn states).	VTS	1996	DBLP DOI BibTeX RDF	clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning
35	Rohit Kapur, M. Ray Mercer	Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	bounding algorithm, circuit faults, conditional syndromes, auxiliary gate, pseudorandom pattern resistant faults, circuit structure, computational complexity, lower bounds, built-in self test, integrated circuit testing, circuit analysis computing, signal probabilities, testability measurement, random pattern testability
35	Anastasios Vergis, Kenneth Steiglitz	Testability Conditions for Bilateral Arrays of Combinational Cells.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	testability conditions, Bilateral arrays, combinational cells, linear growth, one-step testability, preset test sequences, quadratic growth, fault detection, systolic array
34	Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell	A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	testability evaluation, design-for-test, analog and mixed-signal testing
34	Roger T. Alexander, James M. Bieman, Sudipto Ghosh, Bixia Ji	Mutation of Java Objects.	ISSRE	2002	DBLP DOI BibTeX RDF	Java, software testing, object-oriented programming, testability, Faults, mutation analysis, test adequacy
34	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao	Easily Testable Data Path Allocation Using Input/Output Registers.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design
34	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
34	Sujit Dey, Srimat T. Chakradhar	Design of testable sequential circuits by repositioning flip-flops.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault
34	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	On testable multipliers for fixed-width data path architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Fixed-Width Architectures, Built-in Self -Test, High-level Synthesis, Design for Testability
32	Phil McMinn, David W. Binkley, Mark Harman	Empirical evaluation of a nesting testability transformation for evolutionary testing.	ACM Trans. Softw. Eng. Methodol.	2009	DBLP DOI BibTeX RDF	testability transformation, test data generation, Evolutionary testing, search-based software engineering
32	Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
32	Teemu Kanstrén	A Study on Design for Testability in Component-Based Embedded Software.	SERA	2008	DBLP DOI BibTeX RDF	testing, components, design for testability, embedded software
32	Hao-Chiao Hong	A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Design-for-digital-testability, Stimulus evaluation, ?-? modulator, Behavioral model
32	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function
32	Barbara Cannas, Alessandra Fanni, Stefano Manetti, Augusto Montisci, Maria Cristina Piccirilli	Neural network-based analog fault diagnosis using testability analysis.	Neural Comput. Appl.	2004	DBLP DOI BibTeX RDF	Neural networks, Diagnosis, Analog circuits, Testability analysis
32	Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni	A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	Radio Frequency (RF) Testing, Design for Testability (DFT), Voltage Controlled Oscillator (VCOs)
32	André Baresel, David W. Binkley, Mark Harman, Bogdan Korel	Evolutionary testing in the presence of loop-assigned flags: a testability transformation approach.	ISSTA	2004	DBLP DOI BibTeX RDF	flags, testability transformation, empirical evaluation, evolutionary testing
32	Cecilia Metra, T. M. Mak, Martin Omaña 0001	Fault secureness need for next generation high performance microprocessor design for testability structures.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	built in self test, design for testability, microprocessor, comparator, fault secureness
32	Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev	Design for Delay Testability in High-Speed Digital ICs.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	BIST, delay-fault testing, design for delay testability, high-speed testing
32	Masaki Hashizume, Hiroyuki Yotsuyanagi, Masahiro Ichimiya, Takeomi Tamesada, Masashi Takeda	High speed IDDQ test and its testability for process variation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	high speed IDDQ test, charge current, gate load capacitances, test input vector application, CMOS IC production, logic testing, integrated circuit testing, process variation, testability, CMOS logic circuits, production testing
32	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
32	Erik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, Victor Boyadzhyan, Brent R. Blaes, Wai-Chi Fang	Novel Design for Testability of a Mixed-Signal VLSI IC.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Mixed-signal VLSI, verification, microprocessor, testability, RF
32	Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda, Roberto Vietti	A System for Evaluating On-Line Testability at the RT-level.	DFT	1998	DBLP DOI BibTeX RDF	Testability estimation, On-line testing, Design exploration
32	Yervant Zorian	Fundamentals of MCM Testing and Design-for-Testability.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	known good dies, design-for-testability, MCM testing
32	Joan Carletta, Christos A. Papachristou	Behavioral Testability Insertion for Datapath/Controller Circuits.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	behavioral testability analysis, BIST, test synthesis
32	Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto	Application of a Design for Delay Testability Approach to High Speed Logic LSIs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Delay Test Generation, Design for Testability, Delay Testing
32	Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida	Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	core test, design-for-testability, BIST, scan, boundary scan, test bus
32	Jacob Savir	Random pattern testability of memory control logic.	VTS	1997	DBLP DOI BibTeX RDF	embedded memory control logic, exposure probability, fault detection, integrated memory circuits, signal probability, random pattern testability
32	Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth	Synthesis for Testability by Two-Clock Control.	VLSI Design	1997	DBLP DOI BibTeX RDF	two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph
32	Chien-Chung Tsai, Malgorzata Marek-Sadowska	Logic Synthesis for Testability.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	Fixed-Polarity Reed-Muller Forms, Logic synthesis, Testability
32	Jeffrey M. Voas, Jeffery E. Payne, R. Mills, John McManus	Software Testability: An Experiment in Measuring Simulation Reusability.	SSR	1995	DBLP DOI BibTeX RDF	software testability, software testing, software reusability
32	Joan Carletta, Christos A. Papachristou	Testability analysis and insertion for RTL circuits based on pseudorandom BIST.	ICCD	1995	DBLP DOI BibTeX RDF	pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits
32	Prab Varma, Tushar Gheewala	The economics of scan-path design for testability.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	state retention problem, Design for testability, scan, partial scan, test economics, life-cycle costs
32	Dhamin Al-Khalili, Côme Rozon, B. Stewart	Testability analysis and fault modeling of BiCMOS circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	modeling, testability, faults, defects, BiCMOS
32	Bernd Becker 0001	Synthesis for Testability: Binary Decision Diagrams.	STACS	1992	DBLP DOI BibTeX RDF	VLSI structures, (complete, full) testability, synthesis, fault model, algorithms and data structures
32	Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda	Exact probabilistic testability measures for multi-output circuits.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	probabilistic testability analysis, Built-in self-test, test-pattern generation, CAD tools
32	Michiel M. Ligthart, Emile H. L. Aarts, Frans P. M. Beenker	Design-for-testability of PLA's using statistical cooling.	DAC	1986	DBLP DOI BibTeX RDF	PLA testing, statistical cooling, design-for-testability, PLA
30	Kaarina Karppinen, Lyly Yonkwa, Mikael Lindvall	Why Developers Insert Security Vulnerabilities into Their Code.	ACHI	2009	DBLP DOI BibTeX RDF
30	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre	Securing Scan Control in Crypto Chips.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Crypto-chips, Security, Scan
30	Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara	A DFT Method for Time Expansion Model at Register Transfer Level.	DAC	2007	DBLP DOI BibTeX RDF
30	Petros Oikonomakos, Mark Zwolinski	An Integrated High-Level On-Line Test Synthesis Tool.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
30	Bo Yang 0010, Kaijie Wu 0001, Ramesh Karri	Secure Scan: A Design-for-Test Architecture for Crypto Chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
30	Sami Beydeda	Self-Metamorphic-Testing Components.	COMPSAC (2)	2006	DBLP DOI BibTeX RDF
30	Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir	A novel improvement technique for high-level test synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
30	Shyue-Kung Lu, Chien-Hung Yeh	Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
30	Stefan Jungmayr	Identifying Test-Critical Dependencies.	ICSM	2002	DBLP DOI BibTeX RDF
30	Lionel C. Briand, Yvan Labiche	A UML-Based Approach to System Testing.	UML	2001	DBLP DOI BibTeX RDF
30	Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi	Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays.	DFT	2001	DBLP DOI BibTeX RDF
30	Dong Xiang, Yi Xu	Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset Signals.	VTS	2001	DBLP DOI BibTeX RDF
30	Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
30	Sandeep Bhatia, Niraj K. Jha	Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
30	Katzalin Olcoz, Francisco Tirado	Register Allocation with Simultaneous BIST Intrusio.	EUROMICRO	1998	DBLP DOI BibTeX RDF
30	Gwo-Haur Hwang, Wen-Zen Shen	Restructuring and logic minimization for testable PLA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
30	Srinivas Devadas, Kurt Keutzer	Validatable nonrobust delay-fault testable circuits via logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
29	Eliane Martins, Cristina Maria Toyota, Rosileny Lie Yanagawa	Constructing Self-Testable Software Components.	DSN	2001	DBLP DOI BibTeX RDF	component testability, self-testable component, OO testing, design for testability
29	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
29	Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu	DFT closure.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
29	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
29	Roberto Bevacqua, Luca Guerrazzi, Franco Fummi	SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation.	EUROMICRO	1996	DBLP DOI BibTeX RDF	test storage, scan-path techniques, Built-In Self Test, design for testability, Design for Testability, BIST, test pattern generation, SCAN, test sequences
29	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
29	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
29	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
29	U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
29	Elizabeth M. Rudnick, Janak H. Patel	A genetic approach to test application time reduction for full scan and partial scan circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	partial scan circuits, design-for-testability techniques, compact test set generation, genetic algorithms, genetic algorithms, logic testing, design for testability, logic design, sequential circuits, combinational circuits, DFT, flip-flops, test application time reduction, full scan circuits
29	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree
29	Tao Niu, Yingjiao Zhang, Debo Zhang, Liqiang Liu, Xianjue Luo	Testability Analysis of Grounding Grids Using Network Transformation.	IAS	2009	DBLP DOI BibTeX RDF
29	Ismael Rodríguez	A General Testability Theory.	CONCUR	2009	DBLP DOI BibTeX RDF
29	Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
29	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
29	Sying-Jyan Wang, Tung-Hua Yeh	High-level test synthesis for delay fault testability.	DATE	2007	DBLP DOI BibTeX RDF
29	Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang	An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders.	APCCAS	2006	DBLP DOI BibTeX RDF
29	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
29	Bogdan Korel, Mark Harman, S. Chung, P. Apirukvorapinit, Rajiv Gupta 0001, Q. Zhang	Data Dependence Based Testability Transformation in Automated Test Generation.	ISSRE	2005	DBLP DOI BibTeX RDF
29	Mansour H. Assaf, Sunil R. Das, Emil M. Petriu, Mehmet Sahinoglu	Enhancing Testability in Architectural Design for the New Generation of Core-Based Embedded Systems.	HASE	2004	DBLP DOI BibTeX RDF
29	Y. S. Son, Jong Whoa Na	A New Logic Transformation Method for Both Low Power and High Testability.	PATMOS	2004	DBLP DOI BibTeX RDF
29	Sule Ozev, Alex Orailoglu	End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths.	ICCD	2004	DBLP DOI BibTeX RDF
29	Troy Lamoreaux, Mark Ofori-Kyei, Mark Pinone	A Process for Improving Software Testability.	ICSM	2004	DBLP DOI BibTeX RDF
29	Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir	Testability Improvement During High-Level Synthesis.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
29	Junhao Shi, Görschwin Fey, Rolf Drechsler	BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
29	Avraham Trakhtman	Reducing the Time Complexity of Testing for Local Threshold Testability.	CIAA	2003	DBLP DOI BibTeX RDF	threshold locally testable, algorithm, graph, Automaton
29	Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li 0001	A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.	MTDT	2003	DBLP DOI BibTeX RDF
29	Jonathan Vincent, Graham King, Peter Lay, John Kinghorn	Principles of Built-In-Test for Run-Time-Testability in Component-Based Software Systems.	Softw. Qual. J.	2002	DBLP DOI BibTeX RDF	continuous test, component based software engineering, built-in-test, verification and validation
29	Jin-Cherng Lin, Szu-Wen Lin	An Analytic Software Testability Model.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
29	Andrzej Krasniewski	Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing.	DSD	2001	DBLP DOI BibTeX RDF
29	Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara	Design for Hierarchical Two-Pattern Testability of Data Paths.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
29	Kelly A. Ockunzzi, Christos A. Papachristou	Breaking Correlation to Improve Testability.	VTS	2001	DBLP DOI BibTeX RDF	BIST, DFT, Test Synthesis
29	Ginette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst	Tools for the Characterization of Bipolar CML Testability.	VTS	2001	DBLP DOI BibTeX RDF	IFA, Automatic characterization, Fault-Modeling, CML
29	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
29	Susanta Chakrabarti, Sandip Das 0001, Debesh Kumar Das, Bhargab B. Bhattacharya	Synthesis of symmetric functions for path-delay fault testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
29	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou	Synthesis-for-testability of controller-datapath pairs that use gated clocks.	DAC	2000	DBLP DOI BibTeX RDF
29	Jacob Savir	Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	exposure probability, escape probability, Markov chain, detection probability, signal probability, random patterns
29	A. N. Trahtman	An Algorithm to Verify Local Threshold Testability of Deterministic Finite Automata.	WIA	1999	DBLP DOI BibTeX RDF	locally threshold testable, semigroup AMS subject classification 68Q25, 68Q68, 20M07, algorithm, deterministic finite automaton, 68Q45
29	Mostafa I. H. Abd-El-Barr, Maher Al-Sherif, Mohamed Osman	Fault Characterization and Testability Considerations in Multi-Valued Logic Circuits.	ISMVL	1999	DBLP DOI BibTeX RDF
29	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
29	Susanta Chakraborty, Sandip Das 0001, Debesh K. Das, Bhargab B. Bhattacharya	Synthesis of Symmetric Functions for Path-Delay Fault Testability.	VLSI Design	1999	DBLP DOI BibTeX RDF
29	Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto	Testability analysis and behavioral testing of the Hopfield neural paradigm.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
29	Sujit Dey, Vijay Gangaram, Miodrag Potkonjak	A controller redesign technique to enhance testability of controller-data path circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
29	Irith Pomeranz, Sudhakar M. Reddy	Design-for-testability for path delay faults in large combinational circuits using test points.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
29	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
29	Junji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok	Testability Features of R10000 Microprocessor.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Lfsr, Observability Register, Clock Stretch, Fault Simulation, Memory Test