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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10002 occurrences of 3019 keywords
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Results
Found 11893 publication records. Showing 11893 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Kaamran Raahemifar, Majid Ahmadi |
A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 249-, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Jan Otterstedt, Dirk Niggemeyer, T. W. Williams |
Detection of CMOS address decoder open faults with March and pseudo random memory tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 53-62, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Irith Pomeranz, Sudhakar M. Reddy |
On the Detection of Reset Faults in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 470-474, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri |
NEST: a nonenumerative test generation method for path delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1505-1515, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò |
Fault simulation of parametric bridging faults in CMOS IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9), pp. 1403-1410, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor |
Testing Static and Dynamic Faults in Random Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 395-400, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
static faults, fault coverage, memory tests, dynamic faults, fault primitives |
28 | Brian Chess, Tracy Larrabee |
Logic Testing of Bridging Faults in CMOS Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(3), pp. 338-345, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
realistic faults, fault models, fault simulation, test pattern generation, Bridging faults |
28 | Fran Hanchek, Shantanu Dutt |
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(1), pp. 15-33, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
cell faults, wiring faults, Fault tolerance, Field Programmable Gate Array (FPGA), reconfiguration, yield improvement |
28 | Fabrizio Lombardi, Chao Feng, Wei-Kang Huang |
Detection and Location of Multiple Faults in Baseline Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(10), pp. 1340-1344, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
multiple faults location, baseline interconnection networks, faulty switching element, functional description, algorithm, fault diagnosis, fault tolerant computing, multiprocessor interconnection networks, multistage interconnection network, fault location, iterative process, multiple faults detection |
28 | K. H. Kim, Howard O. Welch |
Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(5), pp. 626-636, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
uniform treatment, time cost, distributed recovery blocks scheme, DRB scheme, forward recovery, load-sharing multiprocessing scheme, multimicrocomputer networks, fault tolerant computing, distributed processing, real-time applications, tolerance, software faults, distributed execution, distributed execution, recovery blocks, real-time computer systems, hardware faults |
28 | Petra De Jong, Ad J. van de Goor |
Test Pattern Generation for API Faults in RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1426-1428, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
API faults, near optimal WRITE sequence, integrated circuit testing, BIST, automatic testing, fault location, test pattern generation, Hamiltonian paths, random-access storage, RAM, integrated memory circuits, pattern-sensitive faults |
28 | Bhabani P. Sinha, Bhargab B. Bhattacharya |
On the Numerical Complexity of Short-Circuit Faults in Logic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(2), pp. 186-190, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
Stirling numbers, Bell numbers, short-circuit faults, bridging faults, Fibonacci numbers, logic networks |
28 | Kewal K. Saluja, Kozo Kinoshita |
Test Pattern Generation for API Faults in RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(3), pp. 284-287, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
static pattern-sensitive faults, fault detection, Built-in testing, random-access memory, pattern-sensitive faults |
28 | Christos A. Papachristou, Narendar B. Sahgal |
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 34(2), pp. 110-116, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
random access memories (RAM's), fault models, memory testing, Coupling faults, functional faults |
27 | Paul P. Lin, James H. Zhu |
Detection and isolation of process faults from actuator faults and sensor faults for a typical MIMO dynamic system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCA ![In: 11th IEEE International Conference on Control & Automation, ICCA 2014, Taichung, Taiwan, June 18-20, 2014, pp. 371-376, 2014, IEEE, 978-1-4799-2837-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
27 | Marek Chrobak, Mathilde Hurand, Jirí Sgall |
Algorithms for testing fault-tolerance of sequenced jobs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sched. ![In: J. Sched. 12(5), pp. 501-515, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Scheduling, Fault-tolerance, Algorithms, Real-time systems |
27 | Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramachandran, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou |
Using likely program invariants to detect hardware errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 70-79, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Tianshe Yang, Zheng Xi, Lida Xu, Xiaoshe Dong, YongXuan Huang |
Application of uncertainty reasoning theory to satellite fault detection and diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: Proceedings of the IEEE International Conference on Systems, Man and Cybernetics, Montréal, Canada, 7-10 October 2007, pp. 3230-3234, 2007, IEEE, 978-1-4244-0990-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | James A. Jones, Mary Jean Harrold, James F. Bowring |
Debugging in Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of the ACM/SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 2007, London, UK, July 9-12, 2007, pp. 16-26, 2007, ACM, 978-1-59593-734-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
execution clustering, empirical study, program analysis, fault localization, automated debugging |
27 | Ilia Polian, Damian Nowroth, Bernd Becker 0001 |
Identification of Critical Errors in Imaging Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 201-202, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Low-cost on-line test, Selective hardening, Imaging applications, Error tolerance |
27 | Mats Grindal, Birgitta Lindström, Jeff Offutt, Sten F. Andler |
An evaluation of combination strategies for test case selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Empir. Softw. Eng. ![In: Empir. Softw. Eng. 11(4), pp. 583-611, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
AETG, Testing experiment, Test case selection, Orthogonal arrays, Combination strategies |
27 | Feng Shi 0010, Yiorgos Makris |
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 57-67, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Piotr Tomaszewski, Lars-Ola Damm |
Comparing the fault-proneness of new and modified code: an industrial case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISESE ![In: 2006 International Symposium on Empirical Software Engineering (ISESE 2006), September 21-22, 2006, Rio de Janeiro, Brazil, pp. 2-7, 2006, ACM, 1-59593-218-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
modified code, fault-proneness, fault prediction |
27 | Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy |
On Improving Defect Coverage of Stuck-at Fault Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 216-223, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
Path delay test compaction with process variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 845-850, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
process variation, delay testing, path delay fault, test compaction |
27 | Yuanyuan Yang 0001, Jianchao Wang |
Fault-Tolerant Rearrangeable Permutation Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(4), pp. 414-426, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
losing-contact fault, Fault tolerance, routing, cluster computing, fault model, permutation, switching networks, Clos networks, rearrangeable |
27 | Giovanni Cantone, Zeiad A. Abdulnabi, Anna Lomartire, Giuseppe Calavaro |
Effectiveness of Code Reading and Functional Testing with Event-Driven Object-Oriented Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESERNET ![In: Empirical Methods and Studies in Software Engineering, Experiences from ESERNET, pp. 166-192, 2003, Springer, 3-540-40672-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu |
Test and Diagnosis of Word-Oriented Multiport Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 248-253, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Dolores M. Zage, Wayne M. Zage |
An Analysis of the Fault Correction Process in a Large-Scale SDL Production Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: Proceedings of the 25th International Conference on Software Engineering, May 3-10, 2003, Portland, Oregon, USA, pp. 570-577, 2003, IEEE Computer Society, 0-7695-1877-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Vivekananda M. Vedula, Jacob A. Abraham |
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 730-734, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Roger T. Alexander, Jeff Offutt, James M. Bieman |
Syntactic Fault Patterns in OO Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 8th International Conference on Engineering of Complex Computer Systems (ICECCS 2002), 2-4 December 2002, Greenbelt, MD, USA, pp. 193-202, 2002, IEEE Computer Society, 0-7695-1757-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Itsuo Takanami, Masaru Sato, Yun Ping Yang |
A Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (3) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 3, pp. 515-520, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multi-layered neural network, weight fault, fault-tolerance, fault injection |
27 | Laurence Goodby, Alex Orailoglu |
Redundancy and testability in digital filter datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5), pp. 631-644, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Mei-Huei Tang, Ming-Hung Kao, Mei-Hwa Chen |
An Empirical Study on Object-Oriented Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 6th IEEE International Software Metrics Symposium (METRICS 1999), 4-6 November 1999, Boca Raton, FL, USA, pp. 242-249, 1999, IEEE Computer Society, 0-7695-0403-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
CK metrics, object-oriented fault analysis, object-oriented metrics |
27 | Irith Pomeranz, Sudhakar M. Reddy |
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 216-221, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
dynamic test compaction, synchronous sequential circuits, static test compaction |
27 | Inhwan Lee, Ravishankar K. Iyer |
Software Dependability in the Tandem GUARDIAN System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 21(5), pp. 455-467, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fault categorization, operational phase, Tandem GUARDIAN System, Measurement, software reliability, software fault tolerance, recurrence |
27 | Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001 |
A comprehensive fault macromodel for opamps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 344-348, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Patrick Kam Lui, Jon C. Muzio |
Constrained parity testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(3), pp. 279-291, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
compaction testing, parity testing, Built-in self-test, signature analysis |
27 | F. Joel Ferguson, John Paul Shen |
A CMOS fault extractor for inductive fault analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(11), pp. 1181-1194, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
27 | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
Energy-efficient redundant execution for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 143-146, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
redundant execution, microarchitecture, transient faults, permanent faults |
27 | Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero |
PPM Reduction on Embedded Memories in System on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 85-90, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
static faults, PPM reduction, memory testing, dynamic faults |
27 | Frances Perry, Lester W. Mackey, George A. Reis, Jay Ligatti, David I. August, David Walker 0001 |
Fault-tolerant typed assembly language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, San Diego, California, USA, June 10-13, 2007, pp. 42-53, 2007, ACM, 978-1-59593-633-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
transient hardware faults, fault tolerance, typed assembly language, soft faults |
27 | Kanad Chakraborty, Pinaki Mazumder |
New March Tests for Multiport RAM Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 389-395, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults |
27 | Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi |
Cyclic greedy generation method for limited number of IDDQ tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 362-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns |
27 | Takehiro Ito, Itsuo Takanami |
On fault injection approaches for fault tolerance of feedforward neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 88-93, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
snapping faults, learning cycle, ditribution of correlations, output neuron, fault tolerance, reliabilities, fault injection, stuck-at faults, computer simulation, learning algorithm, feedforward neural networks, feedforward neural nets, recognition rate, learning methods, internal structure |
27 | Takaki Yoshida, Reisuke Shimoda, Takashi Mizokawa, Katsuhiro Hirayama |
An effective fault simulation method for core based LSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 116-121, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
effective fault simulation, core based LSI, handling time, random sampling method, distributed fault simulation, FPP, faults per pass, hyper faults, mask patterns, random processes, DFS, yield analysis |
27 | James Jacob, Vishwani D. Agrawal |
Multiple fault detection in two-level multi-output circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 171-173, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
checkpoint faults, crosspoint faults, multi-output combinational circuits, fault modeling |
27 | Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi |
Fault simulation for general FCMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(2), pp. 181-190, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, bridging faults, CMOS circuits, stuck-open faults, critical path analysis |
26 | Umberto Ferraro Petrillo, Irene Finocchi, Giuseppe F. Italiano |
The Price of Resiliency: a Case Study on Sorting with Memory Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 53(4), pp. 597-620, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Memory faults, Computing with unreliable information, Sorting, Fault injection, Memory models, Experimental algorithmics |
26 | Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor |
Opens and Delay Faults in CMOS RAM Address Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(12), pp. 1630-1639, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects |
26 | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001 |
Automatic Test Pattern Generation for Resistive Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(1), pp. 61-69, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
resistive short defects, ATPG, SAT, bridging faults |
26 | Kai Chen 0009, Fan Jiang 0005, Chuan-dong Huang |
A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), Dijon, France, April 23-27, 2006, pp. 1791-1797, 2006, ACM, 1-59593-108-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
output-shifting faults, synchronization problems, distributed system, conformance testing, FSM |
26 | Zeng Shuiping, Li Jinhong |
Diagnosis System of the Anode Faults for Alumina Reduction Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA (1) ![In: Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), October 16-18, 2006, Jinan, China, pp. 844-849, 2006, IEEE Computer Society, 0-7695-2528-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Aluminum production, diagnosis system, Anode effect, Anode faults, Fuzzy relation |
26 | Stefan Dobrev |
Communication-Efficient Broadcasting in Complete Networks with Dynamic Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 36(6), pp. 695-709, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Sense of Direction, Fault Tolerance, Distributed Computing, Broadcasting, Dynamic Faults, Complete Networks |
26 | Ad J. van de Goor, Magdy S. Abadir, Alan Carlin |
Minimal Test for Coupling Faults in Word-Oriented Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 944-948, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
State coupling faults, word-oriented memories, tests, data backgrounds, m-out-of-n codes |
26 | Said Hamdioui, Ad J. van de Goor, Mike Rodgers |
March SS: A Test for All Static Simple RAM Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 95-100, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
simple/linked faults, fault models, fault coverage, Memory testing, march test |
26 | Andrea Bondavalli, Silvano Chiaradonna, Felicita Di Giandomenico, Fabrizio Grandoni 0002 |
Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 230-245, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fault discrimination, threshold-based identification, transient and intermittent faults, fault diagnosis, modeling and evaluation |
26 | Mohammad H. Azadmanesh, Roger M. Kieckhafer |
Exploiting Omissive Faults in Synchronous Approximate Agreement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1031-1042, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Approximate agreement, convergent voting algorithms, hybrid faults, clock synchronization, fault-tolerant distributed systems |
26 | Andrzej Krasniewski |
Self-Testing of FPGA Delay Faults in the System Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 40-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, BIST, random testing, delay faults |
26 | Chul Young Lee, D. M. H. Walker |
PROBE: A PPSFP Simulator for Resistive Bridging Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 105-112, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
PPSFP, fault model, fault simulation, bridging fault, resistive bridging faults |
26 | Klaus Echtle |
Avoiding Malicious Byzantine Faults by a New Signature Generation Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-3, Third European Dependable Computing Conference, Prague, Czech Republic, September 15-17, 1999, Proceedings, pp. 106-123, 1999, Springer, 3-540-66483-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Malicious Byzantine Faults, Digital Signatures for Fault Tolerance, Agreement Protocols |
26 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
26 | Ankan K. Pramanick, Sudhakar M. Reddy |
Efficient multiple path propagating tests for delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(3), pp. 157-172, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay testing, path delay faults, robust tests, test efficiency |
26 | Irith Pomeranz, Sudhakar M. Reddy |
Functional test generation for delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 687-694, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation |
26 | Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee |
Diagnosis of realistic bridging faults with single stuck-at information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 185-192, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
match requirement, match restriction, realistic bridging faults diagnosis, single stuck-at dictionaries, single stuck-at information, stuck-at diagnosis, stuck-at methods, fault diagnosis, logic testing, fault location, failure analysis, failure recovery |
26 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis |
Testing combinational iterative logic arrays for realistic faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 35-41, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model |
26 | Sreejit Chakravarty, Yiming Gong |
Voting model based diagnosis of bridging faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 338-342, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure |
26 | Michele Favalli, Piero Olivo, Bruno Riccò |
Dynamic effects in the detection of bridging faults in CMOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 197-205, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
test invalidation, fault models, fault simulation, Bridging faults |
26 | Yoshihiro Tohma, Kenshin Tokunaga, Shinji Nagase, Yukihisa Murata |
Structural Approach to the Estimation of the Number of Residual Software Faults Based on the Hyper-Geometric Distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 15(3), pp. 345-355, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
residual software faults, hyper-geometric distribution, segmentation technique, composite estimation, growth curve, debugging, software reliability, software reliability, statistical analysis, programming theory, program debugging, hypergeometric distribution |
26 | Sousuke Amasaki, Takashi Yoshitomi, Osamu Mizuno, Tohru Kikuno, Yasunari Takagi |
Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 272-277, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
software testing, software quality, statistical analysis |
25 | Y. C. Tay, X. R. Zong |
A page fault equation for dynamic heap sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOSP/SIPEW ![In: Proceedings of the first joint WOSP/SIPEW International Conference on Performance Engineering, San Jose, California, USA, January 28-30, 2010, pp. 201-206, 2010, ACM, 978-1-60558-563-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic tuning, heap size, garbage collection, page faults |
25 | Liting Han, James F. Peters |
Rough Neural Fault Classification of Power System Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Rough Sets ![In: Transactions on Rough Sets VIII, pp. 396-519, 2008, Springer, 978-3-540-85063-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Power system faults, knowledge-based fault recognition, rough membership, rough neuron, rough neural network, classification, classify fusion |
25 | Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez |
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 471-484, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Analogue fault simulation, Catastrophic and parametric faults, Process deviations, Analogue test, Statistical modeling |
25 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 287-296, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
address decoders, memory testing, dynamic faults |
25 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan |
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(5), pp. 551-561, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults |
25 | Rim Belhassine-Cherif, Abderrazak Ghedamsi |
Multiple Fault Diagnostics for Communicating Nondeterministic Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 3-5 July 2001, Hammamet, Tunisia, pp. 661-666, 2001, IEEE Computer Society, 0-7695-1177-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Communicating Nondetermistic Finite State Machine, Multiple faults, Diagnostic, Symptom |
25 | Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya |
Isomorph-Redundancy in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(9), pp. 992-997, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines |
25 | Eric Rotenberg |
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-29, The Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, USA, June 15-18, 1999, pp. 84-91, 1999, IEEE Computer Society, 0-7695-0213-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy |
25 | Ad J. van de Goor, Issam B. S. Tlili |
Disturb Neighborhood Pattern Sensitive Fault. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 37-47, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Memory fault models, disturb coupling fault model, neighborhood pattern sensitive faults, test algorithms |
25 | Janusz A. Brzozowski, Kaamran Raahemifar |
Testing C-elements is not elementary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 150-159, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence |
25 | Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Test preparation for high coverage of physical defects in CMOS digital ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 330-337, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high defect coverage, CMOS digital ICs, pseudo realistic faults generation, test quality assessment, tabloid, iceTgen, I/sub DDQ/ test generation, test preparation, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, CMOS digital integrated circuits, physical defects |
25 | Dhamin Al-Khalili, Côme Rozon, B. Stewart |
Testability analysis and fault modeling of BiCMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 207-217, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
modeling, testability, faults, defects, BiCMOS |
24 | Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
Effective BIST for crosstalk faults in interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 164-169, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Dennis Jeffrey, Neelam Gupta, Rajiv Gupta 0001 |
Effective and efficient localization of multiple faults using value replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 25th IEEE International Conference on Software Maintenance (ICSM 2009), September 20-26, 2009, Edmonton, Alberta, Canada, pp. 221-230, 2009, IEEE Computer Society, 978-1-4244-4897-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li |
Diagnosis of Multiple Scan Chain Timing Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6), pp. 1104-1116, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Irith Pomeranz, Sudhakar M. Reddy |
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 137-146, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang |
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 9:1-9:27, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
profiling, design for testability, Diagnosis, fault, scan chain |
24 | Sunghun Kim 0001, Thomas Zimmermann 0001, E. James Whitehead Jr., Andreas Zeller |
Predicting faults from cached history. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISEC ![In: Proceeding of the 1st Annual India Software Engineering Conference, ISEC 2008, Hyderabad, India, February 19-22, 2008, pp. 15-16, 2008, ACM, 978-1-59593-917-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cache, locality, prediction, fault, bug |
24 | Khaled El-Fakih, Anton Kolomeez, Svetlana Prokopenko, Nina Yevtushenko 0001 |
Extended Finite State Machine Based Test Derivation Driven by User Defined Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICST ![In: First International Conference on Software Testing, Verification, and Validation, ICST 2008, Lillehammer, Norway, April 9-11, 2008, pp. 308-317, 2008, IEEE Computer Society, 978-0-7695-3127-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Ilinca Ciupa, Bertrand Meyer 0001, Manuel Oriol, Alexander Pretschner |
Finding Faults: Manual Testing vs. Random+ Testing vs. User Reports. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSRE ![In: 19th International Symposium on Software Reliability Engineering (ISSRE 2008), 11-14 November 2008, Seattle/Redmond, WA, USA, pp. 157-166, 2008, IEEE Computer Society, 978-0-7695-3405-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Frances Perry, David Walker |
Reasoning about Control Flow in the Presence of Transient Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAS ![In: Static Analysis, 15th International Symposium, SAS 2008, Valencia, Spain, July 16-18, 2008. Proceedings, pp. 332-346, 2008, Springer, 978-3-540-69163-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Zhaoxiang Yi, Xiaodong Mu, Li Zhang, Xiongmei Zhang |
Interactive Software and Hardware Faults Diagnosis Based on Negative Selection Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNSC ![In: Proceedings of the IEEE International Conference on Networking, Sensing and Control, ICNSC 2008, Hainan, China, 6-8 April 2008, pp. 433-437, 2008, IEEE, 978-1-4244-1685-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Alexandre Peixoto Ferreira, Daniel Mossé, Jae C. Oh |
Thermal Faults Modeling Using a RC Model with an Application to Web Farms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 19th Euromicro Conference on Real-Time Systems, ECRTS'07, 4-6 July 2007, Pisa, Italy, Proceedings, pp. 113-124, 2007, IEEE Computer Society, 978-0-7695-2914-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
Performance of Graceful Degradation for Cache Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 409-415, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz |
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 817-822, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Peter Nabende, Tom Wanyama |
An Expert System for Diagnosing Heavy-Duty Diesel Engine faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSS (1) ![In: Advances in Computer and Information Sciences and Engineering, Proceedings of the 2007 International Conference on Systems, Computing Sciences and Software Engineering (SCSS), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2007), Bridgeport, CT, USA, December 3-12, 2007, pp. 384-389, 2007, Springer, 978-1-4020-8740-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Uncertainty, Diagnosis, Bayesian Belief Networks |
24 | Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou |
Handling Pattern-Dependent Delay Faults in Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 151-157, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Sunghun Kim 0001, Thomas Zimmermann 0001, E. James Whitehead Jr., Andreas Zeller |
Predicting Faults from Cached History. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: 29th International Conference on Software Engineering (ICSE 2007), Minneapolis, MN, USA, May 20-26, 2007, pp. 489-498, 2007, IEEE Computer Society, 0-7695-2828-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Irith Pomeranz, Sudhakar M. Reddy |
Generation of Functional Broadside Tests for Transition Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2207-2218, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
Automatic march tests generations for static linked faults in SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1258-1263, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
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