Search results for "faults"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Kaamran Raahemifar, Majid Ahmadi	A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
28	Jan Otterstedt, Dirk Niggemeyer, T. W. Williams	Detection of CMOS address decoder open faults with March and pseudo random memory tests.	ITC	1998	DBLP DOI BibTeX RDF
28	Irith Pomeranz, Sudhakar M. Reddy	On the Detection of Reset Faults in Synchronous Sequential Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
28	Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri	NEST: a nonenumerative test generation method for path delay faults in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
28	Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò	Fault simulation of parametric bridging faults in CMOS IC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
28	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor	Testing Static and Dynamic Faults in Random Access Memories.	VTS	2002	DBLP DOI BibTeX RDF	static faults, fault coverage, memory tests, dynamic faults, fault primitives
28	Brian Chess, Tracy Larrabee	Logic Testing of Bridging Faults in CMOS Integrated Circuits.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	realistic faults, fault models, fault simulation, test pattern generation, Bridging faults
28	Fran Hanchek, Shantanu Dutt	Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	cell faults, wiring faults, Fault tolerance, Field Programmable Gate Array (FPGA), reconfiguration, yield improvement
28	Fabrizio Lombardi, Chao Feng, Wei-Kang Huang	Detection and Location of Multiple Faults in Baseline Interconnection Networks.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	multiple faults location, baseline interconnection networks, faulty switching element, functional description, algorithm, fault diagnosis, fault tolerant computing, multiprocessor interconnection networks, multistage interconnection network, fault location, iterative process, multiple faults detection
28	K. H. Kim, Howard O. Welch	Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in Real-Time Applications.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	uniform treatment, time cost, distributed recovery blocks scheme, DRB scheme, forward recovery, load-sharing multiprocessing scheme, multimicrocomputer networks, fault tolerant computing, distributed processing, real-time applications, tolerance, software faults, distributed execution, distributed execution, recovery blocks, real-time computer systems, hardware faults
28	Petra De Jong, Ad J. van de Goor	Test Pattern Generation for API Faults in RAM.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	API faults, near optimal WRITE sequence, integrated circuit testing, BIST, automatic testing, fault location, test pattern generation, Hamiltonian paths, random-access storage, RAM, integrated memory circuits, pattern-sensitive faults
28	Bhabani P. Sinha, Bhargab B. Bhattacharya	On the Numerical Complexity of Short-Circuit Faults in Logic Networks.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	Stirling numbers, Bell numbers, short-circuit faults, bridging faults, Fibonacci numbers, logic networks
28	Kewal K. Saluja, Kozo Kinoshita	Test Pattern Generation for API Faults in RAM.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	static pattern-sensitive faults, fault detection, Built-in testing, random-access memory, pattern-sensitive faults
28	Christos A. Papachristou, Narendar B. Sahgal	An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	random access memories (RAM's), fault models, memory testing, Coupling faults, functional faults
27	Paul P. Lin, James H. Zhu	Detection and isolation of process faults from actuator faults and sensor faults for a typical MIMO dynamic system.	ICCA	2014	DBLP DOI BibTeX RDF
27	Marek Chrobak, Mathilde Hurand, Jirí Sgall	Algorithms for testing fault-tolerance of sequenced jobs.	J. Sched.	2009	DBLP DOI BibTeX RDF	Scheduling, Fault-tolerance, Algorithms, Real-time systems
27	Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramachandran, Sarita V. Adve, Vikram S. Adve, Yuanyuan Zhou	Using likely program invariants to detect hardware errors.	DSN	2008	DBLP DOI BibTeX RDF
27	Tianshe Yang, Zheng Xi, Lida Xu, Xiaoshe Dong, YongXuan Huang	Application of uncertainty reasoning theory to satellite fault detection and diagnosis.	SMC	2007	DBLP DOI BibTeX RDF
27	James A. Jones, Mary Jean Harrold, James F. Bowring	Debugging in Parallel.	ISSTA	2007	DBLP DOI BibTeX RDF	execution clustering, empirical study, program analysis, fault localization, automated debugging
27	Ilia Polian, Damian Nowroth, Bernd Becker 0001	Identification of Critical Errors in Imaging Applications.	IOLTS	2007	DBLP DOI BibTeX RDF	Low-cost on-line test, Selective hardening, Imaging applications, Error tolerance
27	Mats Grindal, Birgitta Lindström, Jeff Offutt, Sten F. Andler	An evaluation of combination strategies for test case selection.	Empir. Softw. Eng.	2006	DBLP DOI BibTeX RDF	AETG, Testing experiment, Test case selection, Orthogonal arrays, Combination strategies
27	Feng Shi 0010, Yiorgos Makris	A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
27	Piotr Tomaszewski, Lars-Ola Damm	Comparing the fault-proneness of new and modified code: an industrial case study.	ISESE	2006	DBLP DOI BibTeX RDF	modified code, fault-proneness, fault prediction
27	Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy	On Improving Defect Coverage of Stuck-at Fault Tests.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
27	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
27	Yuanyuan Yang 0001, Jianchao Wang	Fault-Tolerant Rearrangeable Permutation Network.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	losing-contact fault, Fault tolerance, routing, cluster computing, fault model, permutation, switching networks, Clos networks, rearrangeable
27	Giovanni Cantone, Zeiad A. Abdulnabi, Anna Lomartire, Giuseppe Calavaro	Effectiveness of Code Reading and Functional Testing with Event-Driven Object-Oriented Software.	ESERNET	2003	DBLP DOI BibTeX RDF
27	Chih-Wea Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu	Test and Diagnosis of Word-Oriented Multiport Memories.	VTS	2003	DBLP DOI BibTeX RDF
27	Dolores M. Zage, Wayne M. Zage	An Analysis of the Fault Correction Process in a Large-Scale SDL Production Model.	ICSE	2003	DBLP DOI BibTeX RDF
27	Vivekananda M. Vedula, Jacob A. Abraham	FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.	DATE	2002	DBLP DOI BibTeX RDF
27	Roger T. Alexander, Jeff Offutt, James M. Bieman	Syntactic Fault Patterns in OO Programs.	ICECCS	2002	DBLP DOI BibTeX RDF
27	Itsuo Takanami, Masaru Sato, Yun Ping Yang	A Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs.	IJCNN (3)	2000	DBLP DOI BibTeX RDF	multi-layered neural network, weight fault, fault-tolerance, fault injection
27	Laurence Goodby, Alex Orailoglu	Redundancy and testability in digital filter datapaths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
27	Mei-Huei Tang, Ming-Hung Kao, Mei-Hwa Chen	An Empirical Study on Object-Oriented Metrics.	IEEE METRICS	1999	DBLP DOI BibTeX RDF	CK metrics, object-oriented fault analysis, object-oriented metrics
27	Irith Pomeranz, Sudhakar M. Reddy	Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	dynamic test compaction, synchronous sequential circuits, static test compaction
27	Inhwan Lee, Ravishankar K. Iyer	Software Dependability in the Tandem GUARDIAN System.	IEEE Trans. Software Eng.	1995	DBLP DOI BibTeX RDF	fault categorization, operational phase, Tandem GUARDIAN System, Measurement, software reliability, software fault tolerance, recurrence
27	Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta 0001	A comprehensive fault macromodel for opamps.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Patrick Kam Lui, Jon C. Muzio	Constrained parity testing.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	compaction testing, parity testing, Built-in self-test, signature analysis
27	F. Joel Ferguson, John Paul Shen	A CMOS fault extractor for inductive fault analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
27	Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson	Energy-efficient redundant execution for chip multiprocessors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	redundant execution, microarchitecture, transient faults, permanent faults
27	Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero	PPM Reduction on Embedded Memories in System on Chip.	ETS	2007	DBLP DOI BibTeX RDF	static faults, PPM reduction, memory testing, dynamic faults
27	Frances Perry, Lester W. Mackey, George A. Reis, Jay Ligatti, David I. August, David Walker 0001	Fault-tolerant typed assembly language.	PLDI	2007	DBLP DOI BibTeX RDF	transient hardware faults, fault tolerance, typed assembly language, soft faults
27	Kanad Chakraborty, Pinaki Mazumder	New March Tests for Multiport RAM Devices.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults
27	Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi	Cyclic greedy generation method for limited number of IDDQ tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	cyclic greedy generation method, undetected faults, ISCAS85Y circuits, short circuit faults, fault diagnosis, integrated circuit testing, iterative methods, iterative method, CMOS integrated circuits, IDDQ tests, test patterns, CMOS IC, electric current measurement, cyclic, random patterns
27	Takehiro Ito, Itsuo Takanami	On fault injection approaches for fault tolerance of feedforward neural networks.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	snapping faults, learning cycle, ditribution of correlations, output neuron, fault tolerance, reliabilities, fault injection, stuck-at faults, computer simulation, learning algorithm, feedforward neural networks, feedforward neural nets, recognition rate, learning methods, internal structure
27	Takaki Yoshida, Reisuke Shimoda, Takashi Mizokawa, Katsuhiro Hirayama	An effective fault simulation method for core based LSI.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	effective fault simulation, core based LSI, handling time, random sampling method, distributed fault simulation, FPP, faults per pass, hyper faults, mask patterns, random processes, DFS, yield analysis
27	James Jacob, Vishwani D. Agrawal	Multiple fault detection in two-level multi-output circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	checkpoint faults, crosspoint faults, multi-output combinational circuits, fault modeling
27	Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi	Fault simulation for general FCMOS ICs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	fault simulation, bridging faults, CMOS circuits, stuck-open faults, critical path analysis
26	Umberto Ferraro Petrillo, Irene Finocchi, Giuseppe F. Italiano	The Price of Resiliency: a Case Study on Sorting with Memory Faults.	Algorithmica	2009	DBLP DOI BibTeX RDF	Memory faults, Computing with unreliable information, Sorting, Fault injection, Memory models, Experimental algorithmics
26	Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor	Opens and Delay Faults in CMOS RAM Address Decoders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects
26	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker 0001	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
26	Kai Chen 0009, Fan Jiang 0005, Chuan-dong Huang	A new method of generating synchronizable test sequences that detect output-shifting faults based on multiple UIO sequences.	SAC	2006	DBLP DOI BibTeX RDF	output-shifting faults, synchronization problems, distributed system, conformance testing, FSM
26	Zeng Shuiping, Li Jinhong	Diagnosis System of the Anode Faults for Alumina Reduction Cell.	ISDA (1)	2006	DBLP DOI BibTeX RDF	Aluminum production, diagnosis system, Anode effect, Anode faults, Fuzzy relation
26	Stefan Dobrev	Communication-Efficient Broadcasting in Complete Networks with Dynamic Faults.	Theory Comput. Syst.	2003	DBLP DOI BibTeX RDF	Sense of Direction, Fault Tolerance, Distributed Computing, Broadcasting, Dynamic Faults, Complete Networks
26	Ad J. van de Goor, Magdy S. Abadir, Alan Carlin	Minimal Test for Coupling Faults in Word-Oriented Memories.	DATE	2002	DBLP DOI BibTeX RDF	State coupling faults, word-oriented memories, tests, data backgrounds, m-out-of-n codes
26	Said Hamdioui, Ad J. van de Goor, Mike Rodgers	March SS: A Test for All Static Simple RAM Faults.	MTDT	2002	DBLP DOI BibTeX RDF	simple/linked faults, fault models, fault coverage, Memory testing, march test
26	Andrea Bondavalli, Silvano Chiaradonna, Felicita Di Giandomenico, Fabrizio Grandoni 0002	Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Fault discrimination, threshold-based identification, transient and intermittent faults, fault diagnosis, modeling and evaluation
26	Mohammad H. Azadmanesh, Roger M. Kieckhafer	Exploiting Omissive Faults in Synchronous Approximate Agreement.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Approximate agreement, convergent voting algorithms, hybrid faults, clock synchronization, fault-tolerant distributed systems
26	Andrzej Krasniewski	Self-Testing of FPGA Delay Faults in the System Environment.	IOLTW	2000	DBLP DOI BibTeX RDF	FPGA, BIST, random testing, delay faults
26	Chul Young Lee, D. M. H. Walker	PROBE: A PPSFP Simulator for Resistive Bridging Faults.	VTS	2000	DBLP DOI BibTeX RDF	PPSFP, fault model, fault simulation, bridging fault, resistive bridging faults
26	Klaus Echtle	Avoiding Malicious Byzantine Faults by a New Signature Generation Technique.	EDCC	1999	DBLP DOI BibTeX RDF	Malicious Byzantine Faults, Digital Signatures for Fault Tolerance, Agreement Protocols
26	Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya	Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.	VLSI Design	1998	DBLP DOI BibTeX RDF	Built-in self-test, TPG, delay faults, robust testing, two-pattern tests
26	Ankan K. Pramanick, Sudhakar M. Reddy	Efficient multiple path propagating tests for delay faults.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	delay testing, path delay faults, robust tests, test efficiency
26	Irith Pomeranz, Sudhakar M. Reddy	Functional test generation for delay faults in combinational circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	gate-level realizations, logic testing, delays, test generation, test generators, combinational circuits, fault simulated, logic CAD, delay faults, functional fault model, functional test generation
26	Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee	Diagnosis of realistic bridging faults with single stuck-at information.	ICCAD	1995	DBLP DOI BibTeX RDF	match requirement, match restriction, realistic bridging faults diagnosis, single stuck-at dictionaries, single stuck-at information, stuck-at diagnosis, stuck-at methods, fault diagnosis, logic testing, fault location, failure analysis, failure recovery
26	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
26	Sreejit Chakravarty, Yiming Gong	Voting model based diagnosis of bridging faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure
26	Michele Favalli, Piero Olivo, Bruno Riccò	Dynamic effects in the detection of bridging faults in CMOS ICs.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	test invalidation, fault models, fault simulation, Bridging faults
26	Yoshihiro Tohma, Kenshin Tokunaga, Shinji Nagase, Yukihisa Murata	Structural Approach to the Estimation of the Number of Residual Software Faults Based on the Hyper-Geometric Distribution.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	residual software faults, hyper-geometric distribution, segmentation technique, composite estimation, growth curve, debugging, software reliability, software reliability, statistical analysis, programming theory, program debugging, hypergeometric distribution
26	Sousuke Amasaki, Takashi Yoshitomi, Osamu Mizuno, Tohru Kikuno, Yasunari Takagi	Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	software testing, software quality, statistical analysis
25	Y. C. Tay, X. R. Zong	A page fault equation for dynamic heap sizing.	WOSP/SIPEW	2010	DBLP DOI BibTeX RDF	dynamic tuning, heap size, garbage collection, page faults
25	Liting Han, James F. Peters	Rough Neural Fault Classification of Power System Signals.	Trans. Rough Sets	2008	DBLP DOI BibTeX RDF	Power system faults, knowledge-based fault recognition, rough membership, rough neuron, rough neural network, classification, classify fusion
25	Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luís Rolíndez	Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Analogue fault simulation, Catastrophic and parametric faults, Process deviations, Analogue test, Statistical modeling
25	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	address decoders, memory testing, dynamic faults
25	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
25	Rim Belhassine-Cherif, Abderrazak Ghedamsi	Multiple Fault Diagnostics for Communicating Nondeterministic Finite State Machines.	ISCC	2001	DBLP DOI BibTeX RDF	Communicating Nondetermistic Finite State Machine, Multiple faults, Diagnostic, Symptom
25	Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya	Isomorph-Redundancy in Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines
25	Eric Rotenberg	AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.	FTCS	1999	DBLP DOI BibTeX RDF	branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy
25	Ad J. van de Goor, Issam B. S. Tlili	Disturb Neighborhood Pattern Sensitive Fault.	VTS	1997	DBLP DOI BibTeX RDF	Memory fault models, disturb coupling fault model, neighborhood pattern sensitive faults, test algorithms
25	Janusz A. Brzozowski, Kaamran Raahemifar	Testing C-elements is not elementary.	ASYNC	1995	DBLP DOI BibTeX RDF	C-elements testing, gate circuits, C-element, CMOS implementations, logic testing, logic tests, asynchronous circuits, fault location, stuck-at faults, speed-independence
25	Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira 0001	Test preparation for high coverage of physical defects in CMOS digital ICs.	VTS	1995	DBLP DOI BibTeX RDF	high defect coverage, CMOS digital ICs, pseudo realistic faults generation, test quality assessment, tabloid, iceTgen, I/sub DDQ/ test generation, test preparation, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, CMOS digital integrated circuits, physical defects
25	Dhamin Al-Khalili, Côme Rozon, B. Stewart	Testability analysis and fault modeling of BiCMOS circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	modeling, testability, faults, defects, BiCMOS
24	Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Effective BIST for crosstalk faults in interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
24	Dennis Jeffrey, Neelam Gupta, Rajiv Gupta 0001	Effective and efficient localization of multiple faults using value replacement.	ICSM	2009	DBLP DOI BibTeX RDF
24	Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li	Diagnosis of Multiple Scan Chain Timing Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
24	Sunghun Kim 0001, Thomas Zimmermann 0001, E. James Whitehead Jr., Andreas Zeller	Predicting faults from cached history.	ISEC	2008	DBLP DOI BibTeX RDF	cache, locality, prediction, fault, bug
24	Khaled El-Fakih, Anton Kolomeez, Svetlana Prokopenko, Nina Yevtushenko 0001	Extended Finite State Machine Based Test Derivation Driven by User Defined Faults.	ICST	2008	DBLP DOI BibTeX RDF
24	Ilinca Ciupa, Bertrand Meyer 0001, Manuel Oriol, Alexander Pretschner	Finding Faults: Manual Testing vs. Random+ Testing vs. User Reports.	ISSRE	2008	DBLP DOI BibTeX RDF
24	Frances Perry, David Walker	Reasoning about Control Flow in the Presence of Transient Faults.	SAS	2008	DBLP DOI BibTeX RDF
24	Zhaoxiang Yi, Xiaodong Mu, Li Zhang, Xiongmei Zhang	Interactive Software and Hardware Faults Diagnosis Based on Negative Selection Algorithm.	ICNSC	2008	DBLP DOI BibTeX RDF
24	Alexandre Peixoto Ferreira, Daniel Mossé, Jae C. Oh	Thermal Faults Modeling Using a RC Model with an Application to Web Farms.	ECRTS	2007	DBLP DOI BibTeX RDF
24	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	Performance of Graceful Degradation for Cache Faults.	ISVLSI	2007	DBLP DOI BibTeX RDF
24	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz	Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.	ASP-DAC	2007	DBLP DOI BibTeX RDF
24	Peter Nabende, Tom Wanyama	An Expert System for Diagnosing Heavy-Duty Diesel Engine faults.	SCSS (1)	2007	DBLP DOI BibTeX RDF	Uncertainty, Diagnosis, Bayesian Belief Networks
24	Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou	Handling Pattern-Dependent Delay Faults in Diagnosis.	VTS	2007	DBLP DOI BibTeX RDF
24	Sunghun Kim 0001, Thomas Zimmermann 0001, E. James Whitehead Jr., Andreas Zeller	Predicting Faults from Cached History.	ICSE	2007	DBLP DOI BibTeX RDF
24	Irith Pomeranz, Sudhakar M. Reddy	Generation of Functional Broadside Tests for Transition Faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	Automatic march tests generations for static linked faults in SRAMs.	DATE	2006	DBLP DOI BibTeX RDF