Search results for "VLSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Yuzo Hirai	Recent VLSI neural networks in Japan.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
31	Giuseppe Alia, Enrico Martinelli	A VLSI structure forX(modm) operation.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
30	Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, Çetin Kaya Koç	Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation.	ISVLSI	2002	DBLP DOI BibTeX RDF	VLSI Application-Specific inversion systems, Modular inversion hardware, Almost Montgomery inverse, Cryptography, Montgomery multiplication, Scalable architecture, Modular arithmetic, Extended Euclidean algorithm
30	Shiuh-Rong Huang, Lan-Rong Dung	VLSI Implementation for MAC-Level DWT Architecture.	ISVLSI	2002	DBLP DOI BibTeX RDF	FSFG, limited-resource (LR), MAC-level, scheduling, VLSI, DWT
30	Charles S. Wilson, Tonia G. Morris, Stephen P. DeWeerth	A Two-Dimensional, Object-Based Analog VLSI Visual Attention System.	ARVLSI	1999	DBLP DOI BibTeX RDF	attention, analog VLSI, neuromorphic, focal plane
30	P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
30	Witold A. Pleskacz	Yield Estimation of VLSI Circuits with Downscaled Layouts.	DFT	1999	DBLP DOI BibTeX RDF	IC layout scaling, VLSI circuits, critical area, spot defects, manufacturing yield
30	Chouki Aktouf, Ghassan Al Hayek, Chantal Robach	Concurrent testing of VLSI digital signal processors using mutation based testing.	DFT	1997	DBLP DOI BibTeX RDF	VLSI digital signal processor, software technique, hardware device, fault latency, computation, DSP, fault coverage, Mutation testing, digital signal processing chips, concurrent testing
30	Yuanbin Guo, Joseph R. Cavallaro	A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	adaptive, VLSI, low power, SoC, CDMA, interference cancellation
30	David R. Martinez, Tyler J. Moeller, Ken Teitelbaum	Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	VLSI rader signal processor, front end high performance filtering, digital filtering mapped to reconfigurable computing, commercial FPGA hardware, reconfigurable hardware
30	Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee	SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation.	VTS	1997	DBLP DOI BibTeX RDF	SPITFIRE, scalable parallel algorithms, test set partitioned fault simulation, synchronous parallel algorithms, sequential VLSI circuits, VLSI, fault coverage
30	Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai	A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects.	ICCAD	1996	DBLP DOI BibTeX RDF	3D VLSI interconnects, DRT, Dimension Reduction Technique, FastCap, SPICELINK, dielectric layers, parallel signal lines, VLSI, capacitance extraction
30	Robert H. Klenke, James H. Aylor, Joseph M. Wolf	An analysis of fault partitioning algorithms for fault partitioned ATPG.	VTS	1996	DBLP DOI BibTeX RDF	fault partitioning algorithm, VLSI device, detected fault broadcasting, preprocessing time, parallel processing, parallel processing, VLSI, fault diagnosis, integrated circuit testing, ATPG, automatic testing, dynamic load balancing, NP complete problem, digital system, test vector generation
30	M. P. Kluth, François Simon, Jean-Yves Le Gall, E. Müller	Design of a fault tolerant 100 Gbits solid-state mass memory for satellite.	VTS	1996	DBLP DOI BibTeX RDF	semiconductor storage, fault tolerant solid-state mass memory, satellite applications, VLSI components, 100 Gbit, VLSI, testing, fault tolerant computing, integrated circuit testing, error detection, error detection, special purpose computers, aerospace computing, space applications
30	Steffen Müller	A new programmable VLSI architecture for histogram and statistics computation in different windows.	ICIP	1995	DBLP DOI BibTeX RDF	programmable VLSI architecture, histogram computation, grey-scale histogram, image preprocessing methods, inhomogeneous illumination elimination, simple increment operations, histogrammer, window handling, arithmetic unit configuration, memory configuration, equalisation, simulation, image segmentation, VLSI, segmentation, data compression, data compression, statistics, image enhancement, image enhancement, texture analysis, image texture, digital signal processing chips, CMOS technology, binary images, CMOS digital integrated circuits, co-occurrence-matrix, statistics computation
30	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
30	Andrew M. Bailey, Mark B. Josephs	Sequencer circuits for VLSI programming.	ASYNC	1995	DBLP DOI BibTeX RDF	VLSI programming language, Tangram, sequencer circuits, SI-algebra framework, count-decode architecture, VLSI, high level synthesis
30	Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai	A prototype router for the massively parallel computer RWC-1.	ICCD	1995	DBLP DOI BibTeX RDF	prototype router, massively parallel computer RWC-1, multi-threaded architecture, high communication performance, direct interconnection networks, small degree, operating system support features, CMOS gate array, VLSI, parallel architectures, multiprocessor interconnection networks, CMOS integrated circuits, high throughput, low latency, hardware cost, VLSI chip
30	Hosahalli R. Srinivas, Keshab K. Parhi	A floating point radix 2 shared division/square root chip.	ICCD	1995	DBLP DOI BibTeX RDF	floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm
30	Glenn Holt, Akhilesh Tyagi	EPNR: an energy-efficient automated layout synthesis package.	ICCD	1995	DBLP DOI BibTeX RDF	EPNR, energy-efficient automated layout synthesis package, MCNC Logic Synthesis '93 benchmarks, VPNR, VLSI energy minimization problems, VLSI, logic testing, placement, logic CAD, circuit layout CAD, global routing, logic arrays, standard cells, channel routing
30	Kala Srivatsan, Chaitali Chakrabarti, Lori Lucke	Low power data format converter design using semi-static register allocation.	ICCD	1995	DBLP DOI BibTeX RDF	code convertors, low power data format converter design, semi-static register allocation, processing modules, VLSI, linear programming, integer programming, signal processing, digital signal processing, power consumption, integer linear programming, heuristic programming, heuristic programming, VLSI implementations
30	Hyesook Lim, Earl E. Swartzlander Jr.	An efficient systolic array for the discrete cosine transform based on prime-factor decomposition .	ICCD	1995	DBLP DOI BibTeX RDF	prime-factor decomposition, index mappings, VLSI, discrete cosine transforms, discrete cosine transform, systolic arrays, systolic array, VLSI implementation, array signal processing
30	Jean Paul Calvez, Olivier Pasquier	Performance assessment of embedded Hw/Sw systems.	ICCD	1995	DBLP DOI BibTeX RDF	embedded Hw/Sw systems, VLSI components, heterogeneous multiprocessor architectures, complex real-time applications, performance indexes, real-time event occurrences, software tasks, hardware functions, real-time performance analyzer, MCSE methodology, performance evaluation, real-time systems, VLSI, systems analysis, application specific integrated circuits, ASIC, performance assessment, event trace
30	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
30	Stan Y. Liao, Srinivas Devadas, Kurt Keutzer	Code density optimization for embedded DSP processors using data compression techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	code density optimization, embedded DSP processors, code size minimization, text compression algorithms, TMS320C25 code generator, VLSI, data compression, data compression, skeleton, minimisation, dictionary, digital signal processing chips, VLSI systems, production cost
30	Scott Hauck, Gaetano Borriello	An evaluation of bipartitioning techniques.	ARVLSI	1995	DBLP DOI BibTeX RDF	bipartitioning techniques, VLSI, logic CAD, integrated circuit design, circuit CAD, logic partitioning, logic partitioning, VLSI CAD
30	Michael Bolotski, Thomas Simon, Carlin Vieri, Rajeevan Amirtharajah, Thomas F. Knight Jr.	Abacus: a 1024 processor 8 ns SIMD array.	ARVLSI	1995	DBLP DOI BibTeX RDF	bit-slice computers, Abacus, SIMD array, reconfigurable bit-parallel array, system-level design issues, real-time early vision processing, bit-slice processing element, 8 ns, real-time systems, computer vision, VLSI, parallel architectures, reconfigurable architectures, microarchitecture, VLSI implementation, communication primitives
30	Khaled Saab 0001, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski	Frequency-based BIST for analog circuit testin.	VTS	1995	DBLP DOI BibTeX RDF	waveform generators, frequency-based BIST, analog circuit testing, sine wave generator, sinusoidal input signals, variable frequency input stimulus, frequency input signal, T-BIST approach, frequency-counter BIST approach, VLSI, VLSI, built-in self test, integrated circuit testing, analogue integrated circuits
30	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
30	Emilio L. Zapata, Francisco Argüello	A VLSI Constant Geometry Architecture for the Fast Hartley and Fourier Transforms.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	fast Hartley transform, VLSI constant geometryarchitecture, parallel calculation, constant geometry algorithm, perfect unshuffle permutation, processormemory, systolic data flow, multiplexing operations, hardwired control, parallel algorithms, VLSI, parallel architecture, parallel architectures, fast Fourier transform, fast Fourier transforms, butterflies, FIFO queues, application-specific architecture, computationalcomplexity
30	F. Matthew Rhodes, Joseph J. Dituri, Glenn H. Chapman, Bruce E. Emerson, Antonio M. Soares, Jack I. Raffel	A Monolithic Hough Transform Processor Based on Restructurable VLSI.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	pixel grouping, WSI technology, monolithic Hough transform processor, restructurable VLSI, wafer-scale-integration technology, PC board, monolithic integrated circuits, image processing, VLSI, transforms, computerised pattern recognition, digital arithmetic, circuit CAD, microprocessor chips, CAD tools, PCB, linear feature extraction
30	Pey-Chang Kent Lin, Sunil P. Khatri	VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	NLFSR, stream cipher, pseudo-random sequence
30	Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	Kaleem Fatima, Rameshwar Rao 0001	A New Hardware Routing Accelerator for Multi-Terminal Nets.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	Tuhina Samanta, Hafizur Rahaman 0001, Prasun Ghosal, Parthasarathi Dasgupta	A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind	An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
30	J. V. R. Ravindra, M. B. Srinivas	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	krylov subspace techniques, monte-carlo simulation, model order reduction, rlc
30	Jeff Mueller, Resve A. Saleh	Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy 0001	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Sukumar Jairam, Navakanta Bhat	GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	D. Dhanasekaran, K. Boopathy Bagan	Fault Tolerant Dynamic Antenna Array in Smart Antenna System Using Evolved Virtual Reconfigurable Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF	Virtual Reconfigurable circuit, element validation, Evolvable hardware
30	Charbel J. Akl, Magdy A. Bayoumi	Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Naoki Yamaguchi, Minoru Watanabe	An Optical Reconfiguration System with Four Contexts.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Charbel J. Akl, Magdy A. Bayoumi	Self-Sleep Buffer for Distributed MTCMOS Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Minoru Watanabe, Naoki Yamaguchi	An Acceleration and Optimization Method for Optical Reconfiguration.	VLSI Design	2008	DBLP DOI BibTeX RDF
30	Dimitrios N. Serpanos, Wayne H. Wolf	VLSI models of network-on-chip interconnect.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
30	Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou 0001, Kip Killpack	NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	modeling, crosstalk, static timing analysis
30	Gautam Hazari, Madhav P. Desai, H. Kasture	On the Impact of Address Space Assignment on Performance in Systems-on-Chip.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Ganesh Venkataraman, Jiang Hu	A Placement Methodology for Robust Clocking.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Jacob A. Abraham, Daniel G. Saab	Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava 0001	Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Ahmad Bahai	Where Analog meets Digital and Beyond.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Jiajin Tu, Jian Chen 0030, Lizy K. John	Hardware Efficient Piecewise Linear Branch Predictor.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan	Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Qiang Qiang, Daniel G. Saab, Jacob A. Abraham	Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Sandip Aine, P. P. Chakrabarti 0001, Rajeev Kumar 0004	Improving the Performance of CAD Optimization Algorithms Using On-Line Meta-Level Control.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee	Real Time Dynamic Receive Apodization for an Ultrasound Imaging System.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Narender Hanchate, Nagarajan Ranganathan	A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Jayashree Sridharan, Tom Chen 0001	Gate Delay Modeling with Multiple Input Switching for Static (Statistical) Timing Analysis.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Debasis Mitra 0002, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu	Test Pattern Generation for Power Supply Droop Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Parthasarathi Dasgupta, Prashant Yadava	Linear Required-Arrival-Time Trees and their Construction.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	An Efficient Scan Tree Design for Compact Test Pattern Set.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Kavish Seth, K. N. Viswajith, S. Srinivasan 0001, V. Kamakoti 0001	Ultra Folded High-Speed Architectures for Reed-Solomon Decoders.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Mark P. Tennant, Ahmet T. Erdogan, Tughrul Arslan, John S. Thompson	A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters.	VLSI Design	2006	DBLP DOI BibTeX RDF
30	Hamidreza Hashempour, Luca Schiano, Fabrizio Lombardi	Enhancing error resilience for reliable compression of VLSI test data.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	reliable compression, ATE, test data compression
30	Nagendran Rangan, Karam S. Chatha	A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.	VLSI Design	2005	DBLP DOI BibTeX RDF
30	Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das	Cellular Automata Based Test Structures with Logic Folding.	VLSI Design	2005	DBLP DOI BibTeX RDF
30	Yibo Wang, Yici Cai, Xianlong Hong	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.	VLSI Design	2005	DBLP DOI BibTeX RDF	accurate delay model, obstacle-aware routing, buffer insertion, interconnect optimization
30	Marong Phadoongsidhi, Kewal K. Saluja	SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
30	Kameshwar Chandrasekar, Michael S. Hsiao	Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs.	VLSI Design	2005	DBLP DOI BibTeX RDF
30	R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti 0001, D. Bhatia	Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines.	VLSI Design	2005	DBLP DOI BibTeX RDF	Three-Dimensional FPGA, Reinforcement Learning (RL), Two-opt algorithm, Support Vector Machines (SVMs), Placement and Routing
30	Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan	Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.	VLSI Design	2005	DBLP DOI BibTeX RDF
30	Denis Deschacht, Alain Lopez	Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation.	VLSI Design	2005	DBLP DOI BibTeX RDF
30	Soroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer	TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	elmore, threshold-based filtering algorithm, static timing analysis, moments, AWE
30	Roghoyeh Salmeh, Brent Maundy	VLSI implementation of an automatic Q tuning system.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	lowpass/highpass filters, quality factor tuning, OTA
30	Vani Prasad, Madhav P. Desai	On Buffering Schemes for Long Multi-Layer Nets.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	C. P. Ravikumar	Multiprocessor Architectures for Embedded System-on-chip Applications.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Srinjoy Mitra, A. N. Chandorkar	Design of Amplifier with Rail-to-Rail CMR with 1V Power Supply.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Subrangshu Das, Subash Chandar G., Ashutosh Tiwari	Reset Careabouts in a SoC Design.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Pranav Anbalagan, Jeffrey A. Davis	Maximum Multiplicity Distributions for Length Prediction Driven Placement.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Li Ding 0002, Pinaki Mazumder	Dynamic Noise Margin: Definitions and Model.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Minoru Watanabe, Fuminori Kobayashi	An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Tun Li, Yang Guo 0003, Sikun Li	Design and Implementation of a Parallel Verilog Simulator: PVSim.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Marong Phadoongsidhi, Kewal K. Saluja	Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults.	VLSI Design	2004	DBLP DOI BibTeX RDF
30	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
30	Zhibin Dai, Dilip K. Banerji	Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.	VLSI Design	2003	DBLP DOI BibTeX RDF
30	Debasis Samanta, Ajit Pal	Synthesis of Dual-VT Dynamic CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF	nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT
30	J. Veerendra Kumar, K. Radhakrishna Rao	A Low-Voltage Low Power CMOS Companding Filter.	VLSI Design	2003	DBLP DOI BibTeX RDF
30	C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra	Mutual Testing based on Wavelet Transforms.	VLSI Design	2003	DBLP DOI BibTeX RDF	Mutual Testing, Discrete Wavelet Transform, At-Speed Testing
30	Vani Prasad, Madhav P. Desai	Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy.	VLSI Design	2003	DBLP DOI BibTeX RDF
30	Chunhong Chen	Probabilistic Analysis of Rectilinear Steiner Trees.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti 0001	Open Computation Tree Logic for Formal Verification of Modules.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	Debasis Samanta, Nishant Sinha 0001, Ajit Pal	Synthesis of High Performance Low Power Dynamic CMOS Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	Ashok K. Murugavel, N. Ranganathan	A Real Delay Switching Activity Simulator Based on Petri Net Modeling.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	Sandeep Koranne	On Test Scheduling for Core-Based SOCs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	Sanjeev Patel	Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
30	Wolfgang Günther 0001, Rolf Drechsler	Implementation of Read- k-times BDDs on Top of Standard BDD Packages.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali	Average Power in Digital CMOS Circuits using Least Square Estimation.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy	On Improving Static Test Compaction for Sequential Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
30	Vineet Sahula, C. P. Ravikumar	The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.	VLSI Design	2001	DBLP DOI BibTeX RDF