Search results for "microprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev	MPTLsim: a simulator for X86 multicore processors.	DAC	2009	DBLP DOI BibTeX RDF	simulator, microprocessor, coherent cache
13	Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design
13	Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos	Hybrid-SBST Methodology for Efficient Testing of Processor Cores.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test
13	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
13	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
13	Daeik D. Kim, Choongyeun Cho, Jonghae Kim	Analog parallelism in ring-based VCOs.	DAC	2008	DBLP DOI BibTeX RDF	analog parallelism, clock period jitter, process-induced variation, ring-based voltage-controlled oscillator, microprocessor, phase-locked loop, phase noise
13	Fariza Sabrina, Salil S. Kanhere, Sanjay K. Jha	Design, Analysis and Implementation of a Novel Multiple Resource Scheduler.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, scheduling and synchronization, Packet-Switched Networks
13	Fariza Sabrina, Salil S. Kanhere, Sanjay K. Jha	Design, Analysis, and Implementation of a Novel Low Complexity Scheduler for Joint Resource Allocation.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	microprocessor/microcomputer applications, scheduling, distributed applications, Packet-switched networks
13	Heather Hanson, Stephen W. Keckler, Soraya Ghiasi, Karthick Rajamani, Freeman L. Rawson III, Juan Rubio 0001	Thermal response to DVFS: analysis with an Intel Pentium M.	ISLPED	2007	DBLP DOI BibTeX RDF	thermal measurement, microprocessor, temperature, DVFS, thermal management
13	Timothy Daryl Stanley, George Embrey, Daniel Prigmore, Leslie D. Fife, Scott Mikolyski, Don Colton	Pedagogic value in understanding computer architecture of implementing the marie computer from null and lobur in the logic emulation software, multimedia logic.	WCAE	2007	DBLP DOI BibTeX RDF	education, computer architecture, microprocessor design, logic emulation
13	Aashish Phansalkar, Ajay Joshi, Lizy Kurian John	Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite.	ISCA	2007	DBLP DOI BibTeX RDF	microprocessor performance counters, clustering, benchmark, SPEC
13	Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang	High Performance General-Purpose Microprocessors: Past and Future.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism
13	Christophe Lécuyer, David C. Brock	Biographies.	IEEE Ann. Hist. Comput.	2006	DBLP DOI BibTeX RDF	Gordon Moore, semiconductor industry, silicon technology, silicon device manufacture, Fairchild Semiconductor, Shockley Semiconductor, microprocessor, integrated circuit, DRAM, personal computer, chemistry, Moore's law, Intel
13	Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, David J. Lilja	The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools.	ICS	2006	DBLP DOI BibTeX RDF	benchmark drift, compiler drift, microprocessor design
13	William Lloyd Bircher, Lizy K. John	Power phase variation in a commercial server workload.	ISLPED	2006	DBLP DOI BibTeX RDF	chipset, commercial workload characterization, memory, power, microprocessor, disk, program phase
13	Josef Goette, Marcel Jacomet, Markus Hager	Using Dither to Improve the Performance of Lossy Sigma-Delta Modulators.	DELTA	2006	DBLP DOI BibTeX RDF	Lossy sumvartriangle modulator, Ad con- Fpga-and microprocessor implementations, dither
13	Wei Wu 0024, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan	A systematic method for functional unit power estimation in microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	microprocessor, power estimation, performance counter
13	Pradip Bose	Designing microprocessors with robust functionality and performance.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability-aware microarchitecture, power-efficient design, microprocessor design
13	Shailender Chaudhry, Paul Caprioli, Sherman Yip, Marc Tremblay	High-Performance Throughput Computing.	IEEE Micro	2005	DBLP DOI BibTeX RDF	hardware scout, CMP, multithreading, multicore, microprocessor, CMT
13	Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer	An Experimental Study of Soft Errors in Microprocessors.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture
13	Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari	Bridging the Processor-Memory Performance Gapwith 3D IC Technology.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	three-dimensional integration 3-D ICs microprocessor cache design stream prefetching embedded DRAM
13	Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw	A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.	CASES	2005	DBLP DOI BibTeX RDF	sensor network, energy efficiency, microprocessor, memory organization
13	Tohru Ishihara, Farzan Fallah	A non-uniform cache architecture for low power system design.	ISLPED	2005	DBLP DOI BibTeX RDF	embedded systems, compiler, microprocessor, cache memory
13	Matthias Pfeffer, Theo Ungerer, Stephan Fuhrmann, Jochen Kreuzinger, Uwe Brinkschulte	Real-Time Garbage Collection for a Multithreaded Java Microcontroller.	Real Time Syst.	2004	DBLP DOI BibTeX RDF	Java microprocessor, real-time, garbage collection, multithreading, microcontroller
13	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
13	Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno	Design methodology for semi custom processor cores.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	design, methodology, synthesis, microprocessor, ASIC, core
13	Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal B. Wijeratne	Low voltage swing logic circuits for a Pentium 4 processor integer core.	DAC	2004	DBLP DOI BibTeX RDF	LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder
13	Joydeep Ray, James C. Hoe	High-level modeling and FPGA prototyping of microprocessors.	FPGA	2003	DBLP DOI BibTeX RDF	operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture
13	John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft	3D direct vertical interconnect microprocessors test vehicle.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic
13	Li Chen, Srivaths Ravi 0001, Anand Raghunathan, Sujit Dey	A scalable software-based self-test methodology for programmable processors.	DAC	2003	DBLP DOI BibTeX RDF	scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test
13	Francisco Barat, Rudy Lauwereins, Geert Deconinck	Reconfigurable Instruction Set Processors from a Hardware/Software Perspective.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	Reconfigurable instruction set processor overview, compiler, microprocessor, reconfigurable logic
13	Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec	Tarantula: A Vector Extension to the Alpha Architecture.	ISCA	2002	DBLP DOI BibTeX RDF	Power, Microprocessor, Bandwidth, High Performance, Cache Coherency, Virtual Memory, Instruction Set Architecture, Vector Processor
13	Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey	Embedded software-based self-testing for SoC design.	DAC	2002	DBLP DOI BibTeX RDF	functional test, SoC test, VLSI test, microprocessor test
13	Li Chen, Sujit Dey	Software-based diagnosis for processors.	DAC	2002	DBLP DOI BibTeX RDF	microprocessor, self-test, instruction, diagnostics
13	Brian W. Amick, Claude R. Gauthier, Dean Liu	Macro-modeling concepts for the chip electrical interface.	DAC	2002	DBLP DOI BibTeX RDF	VLSI power distribution, analog and I/O power delivery, high speed microprocessor design, inductance
13	Deependra Talla, Lizy Kurian John	MediaBreeze: a decoupled architecture for accelerating multimedia applications.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	access and execute mechanisms, multimedia, prefetching, SIMD, hardware accelerators, decoupling, microprocessor design, general-purpose processors
13	Seppo Virtanen, Johan Lilius	The TACO protocol processor simulation environment.	CODES	2001	DBLP DOI BibTeX RDF	simulation, protocol, microprocessor, codesign
13	Israel Koren, Zahava Koren	Incorporating Yield Enhancement into the Floorplanning Process.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
13	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
13	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
13	Prasad N. Golla, Eric C. Lin	A Dynamic Scheduling Logic for Exploiting Multiple Functional Units in Single Ship Multithreaded Architectures.	SAC	1999	DBLP DOI BibTeX RDF	Tomasulo's algorithm, threaded architectures, computer architecture, multithreading, microprocessor
13	Vivek De, Shekhar Borkar	Technology and design challenges for low power and high performance.	ISLPED	1999	DBLP DOI BibTeX RDF	low-power design, memory, microprocessor, VLSI design
13	P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose	Interconnect-Dominated VLSI Design.	ARVLSI	1999	DBLP DOI BibTeX RDF	Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion
13	Shannon V. Morton	On-Chip Inductance Issues in Multiconductor Systems.	DAC	1999	DBLP DOI BibTeX RDF	alpha microprocessor, cross-talk, interconnect, noise, inductance, transmission line, capacitance, resistance, buses, semiconductor, RLC
13	Miroslav N. Velev, Randal E. Bryant	Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation.	ACSD	1998	DBLP DOI BibTeX RDF	pipelined microprocessor verification, memory shadowing, Efficient Memory Model (EMM), circuit correspondence checking, symbolic simulation
13	Sebastián Sánchez 0001, Daniel Meziat, Melquiades Carbajo, Julio L. Medina, Enrique Bronchalo, Javier Rodríguez-Pacheco, Luis del Peral	Control System for a Low Energy Particle Detector.	EUROMICRO	1998	DBLP DOI BibTeX RDF	Special microprocessor applications, space electronics, calibration test, space physics, solar energetic particles, real-time system
13	Yossi Malka, Avi Ziv	Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data.	DAC	1998	DBLP DOI BibTeX RDF	21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha
13	Hans Eisenmann, Frank M. Johannes	Generic Global Placement and Floorplanning.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
13	Alper Demir 0001, Amit Mehrotra, Jaijeet S. Roychowdhury	Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
13	Gustavo de Veciana, Margarida F. Jacome, Jian-Huei Guo	Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
13	Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001	Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
13	Asawaree Kalavade, Pratyush Moghé	A Tool for Performance Estimation of Networked Embedded End-systems.	DAC	1998	DBLP DOI BibTeX RDF	verification, timing, design methodology, microprocessor
13	Johnson Kin, Munish Gupta, William H. Mangione-Smith	The Filter Cache: An Energy Efficient Memory Structure.	MICRO	1997	DBLP DOI BibTeX RDF	direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache
13	Olin Sibert, Phillip A. Porras, Robert Lindell	An Analysis of the Intel 80x86 Security Architecture and Implementations.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF	Hardware security architecture, hardware implementation error, computer security, microprocessor, covert channels, penetration testing
13	Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung	Register renaming for x86 superscalar design.	ICPADS	1996	DBLP DOI BibTeX RDF	Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming
13	Janusz Sosnowski, A. Kusmierczyk	Pseudorandom versus Deterministic Testing of Intel 80x86 Processors.	EUROMICRO	1996	DBLP DOI BibTeX RDF	Intel 80/spl times/86 processors, computer testing, pseudorandom testing, microprocessor testing, deterministic testing
13	Santanu Chattopadhyay, S. Mitra 0001, Parimal Pal Chaudhuri	Cellular automata based architecture of a database query processor.	VLSI Design	1996	DBLP DOI BibTeX RDF	cellular automata based architecture, database query processor, programmable query processor chip, fast database access, multiple attractor cellular automata, class-relation storage, true/false classifier, classification, VLSI, query processing, relational databases, relational database, cellular automata, microprocessor chips, database machines
13	Preeti Ranjan Panda, Nikil D. Dutt	1995 high level synthesis design repository.	ISSS	1995	DBLP DOI BibTeX RDF	1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units
13	Guido Araujo, Sharad Malik	Optimal code generation for embedded memory non-homogeneous register architectures.	ISSS	1995	DBLP DOI BibTeX RDF	TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation
13	Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller	Emulation verification of the Motorola 68060.	ICCD	1995	DBLP DOI BibTeX RDF	emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level
13	Chuan-Yu Wang, Kaushik Roy 0001	Control unit synthesis targeting low-power processors.	ICCD	1995	DBLP DOI BibTeX RDF	control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming
13	Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor	Incas: a cycle accurate model of UltraSPARC.	ICCD	1995	DBLP DOI BibTeX RDF	cycle accurate model, UltraSPARC, Incas, message-passing mechanism, simulating concurrent modules, performance evaluation, C++, virtual machines, logic testing, microprocessor chips, performance estimates, diagnostics, tuning, RTL simulations, processor verification
13	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
13	John D. Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
13	Goutam Debnath, Kathy Debnath, Roshan Fernando	The Pentium processor-90/100, microarchitecture and low power circuit design.	VLSI Design	1995	DBLP DOI BibTeX RDF	BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz
13	Giuseppe Ascia, Vincenzo Catania	Design of a VLSI parallel processor for fuzzy computing.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit
13	Venkatesh Akella, Ganesh Gopalakrishnan	Specification and Validation of Control-Intensive IC's in hopCP.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations
13	Vitit Kantabutra	A Recursive Carry-Lookahead/Carry-Select Hybrid Adder.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
13	Jeffrey O. Smith, Kliffton M. Black, Farhad Kamangar, Jack Fitzer	The University of Texas at Arlington Autonomous Aerial Vehicle - An overview.	Appl. Intell.	1992	DBLP DOI BibTeX RDF	microprocessor control, optimal control, robust control, Autonomous vehicle, inertial navigation
13	Israel Koren, Ofra Zinaty	Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	high-precision floating-point numbers, extended double precision format, IEEE standard P754, floating-point numeric coprocessor, fast adder, digital arithmetic, execution time, microprocessor chips, approximation theory, elementary functions, function evaluation, rational approximations, silicon area, fast multiplier
13	Arvin Park, Matthew K. Farrens	Address compression through base register caching.	MICRO	1990	DBLP BibTeX RDF	CPU performance, microprocessor systems, locality, bandwidth
13	Fred J. Taylor, Rabinder Gill, Jim Joseph, Jeff Radke	A 20 Bit Logarithmic Number System Processor.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	logarithmic number system processor, arithmetic processor, partitioned memory, integrated Schottky logic, 20 bit, satellite computers, performance evaluation, performance evaluation, architecture, computer architecture, digital arithmetic, PLA, microprocessor chips, table lookup, table lookup, ROM, field effect integrated circuits
13	Takashi Nanya, Toshiaki Kawamura	Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	error-secure interfaces, totally self-checking systems, Intel 8080, strongly fault-secure processors, error-propagating interfaces, fault tolerant computing, computer architecture, automatic testing, microprocessor chips, digital system, computer interfaces, 8 bit
13	Li Shen, Stephen Y. H. Su	A Functional Testing Method for Microprocessors.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	functional testing method, control fault model, register transfer language, k-out-of-m codes, test generation time, microprocessors, microprocessor chips, computer testing, testing requirements
13	F. Matthew Rhodes, Joseph J. Dituri, Glenn H. Chapman, Bruce E. Emerson, Antonio M. Soares, Jack I. Raffel	A Monolithic Hough Transform Processor Based on Restructurable VLSI.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	pixel grouping, WSI technology, monolithic Hough transform processor, restructurable VLSI, wafer-scale-integration technology, PC board, monolithic integrated circuits, image processing, VLSI, transforms, computerised pattern recognition, digital arithmetic, circuit CAD, microprocessor chips, CAD tools, PCB, linear feature extraction
13	Lorenz A. Schmitt, Stephen S. Wilson	The AIS-5000 Parallel Processor.	IEEE Trans. Pattern Anal. Mach. Intell.	1988	DBLP DOI BibTeX RDF	AIS-5000, parallel memory organization, image-based algorithms, computer vision, computer vision, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, microprocessor chips, parallel processor, SIMD architecture
13	Satish M. Thatte, Jacob A. Abraham	Test Generation for Microprocessors.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	complexity of tests, functional level fault models, Architecture models, test programs, microprocessor architecture
13	Gerard G. L. Meyer, Gerald M. Masson	An Efficient Fault Diagnosis Algorithm for Symmetric Multiple Processor Architectures.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	modular networks, fault syndromes, microprocessor, Diagnosis algorithm
13	Kilnam Chon	Information processing in electricity distribution systems.	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF	Distribution system, Reliability, Control, Redundancy, Automation, Microprocessor, Information processing, Decentralization, Data base, Electricity
13	Richard G. Cooper	The Distributed Pipeline.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Array of computers, distributed pipeline (DP), multiple-instruction multiple-data-stream (MIMD) computer, distributed computer, multiprocessor, pipeline, computer network, computer architecture, microprocessor, microcomputer
13	Samuel H. Fuller, Victor R. Lesser, Gordon Bell, Charles H. Kaman	The Effects of Emerging Technology and Emulation Requirements on Microprogramming.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	semiconductor technology, microprocessor, interpretation, Emulation, microprogramming
12	Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh	Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dynamic inspection, reconfigurable microprocessors, fpga
12	Xiaochen Guo, Engin Ipek, Tolga Soyata	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.	ISCA	2010	DBLP DOI BibTeX RDF	STT-MRAM, power-efficiency
12	Kypros Constantinides, Todd M. Austin	Using introspective software-based testing for post-silicon debug and repair.	DAC	2010	DBLP DOI BibTeX RDF
12	Peter M. Chen	Transistors to toys: teaching systems to freshmen.	VEE	2010	DBLP DOI BibTeX RDF	education
12	Shlomi Dolev, Yinnon A. Haviv, Mooly Sagiv	Self-stabilization preserving compiler.	ACM Trans. Program. Lang. Syst.	2009	DBLP DOI BibTeX RDF	Compilers, self-stabilization, abstract state machines
12	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
12	Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith 0001, David M. Brooks	Voltage emergency prediction: Using signatures to reduce operating margins.	HPCA	2009	DBLP DOI BibTeX RDF
12	Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar	Circuit techniques for dynamic variation tolerance.	DAC	2009	DBLP DOI BibTeX RDF	dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors
12	Dilip D. Kandlur, Tom W. Keller	Green data centers and hot chips.	DAC	2009	DBLP DOI BibTeX RDF	architecture, data centers, energy management
12	Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha	Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.	DAC	2009	DBLP DOI BibTeX RDF	variability-aware design, robustness, micro-architecture
12	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
12	John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichý, Zdenek Pohl, Antonin Hermanek, Nico F. Benschop	The European Logarithmic Microprocesor.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	General, High-Speed Arithmetic
12	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
12	Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle	Radio frequency identification prototyping.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low-power, RFID, prototyping, Design automation
12	Uwe Brinkschulte, Mathias Pacher	A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors.	ISORC	2008	DBLP DOI BibTeX RDF	Control theory in high-end microprocessors, real-time microprocessors, IPC rate
12	Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W. Kellington, John Schumann, Pia N. Sanda	Statistical Fault Injection.	DSN	2008	DBLP DOI BibTeX RDF
12	Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David M. Brooks	System level analysis of fast, per-core DVFS using on-chip switching regulators.	HPCA	2008	DBLP DOI BibTeX RDF
12	Duo Li, Sheldon X.-D. Tan, Murli Tirumala	Architecture-level thermal behavioral characterization for multi-core microprocessors.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Sebastian Rohde, Thomas Eisenbarth 0001, Erik Dahmen, Johannes Buchmann 0001, Christof Paar	Fast Hash-Based Signatures on Constrained Devices.	CARDIS	2008	DBLP DOI BibTeX RDF	hash based cryptography, Merkle signature scheme, digital signatures, Embedded security