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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2784 occurrences of 1319 keywords
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Results
Found 4097 publication records. Showing 4097 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Hui Zeng, Matt T. Yourst, Kanad Ghose, Dmitry V. Ponomarev |
MPTLsim: a simulator for X86 multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 226-231, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
simulator, microprocessor, coherent cache |
13 | Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli |
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(5), pp. 672-685, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design |
13 | Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos |
Hybrid-SBST Methodology for Efficient Testing of Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 64-75, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test |
13 | Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez 0001, Matteo Sonza Reorda |
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 224-234, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
microprocessor, BDD, MOEA, path-delay testing |
13 | Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez 0001, Matteo Sonza Reorda |
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 389-394, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SBST, path-delay faults, microprocessor test |
13 | Daeik D. Kim, Choongyeun Cho, Jonghae Kim |
Analog parallelism in ring-based VCOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 341-342, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
analog parallelism, clock period jitter, process-induced variation, ring-based voltage-controlled oscillator, microprocessor, phase-locked loop, phase noise |
13 | Fariza Sabrina, Salil S. Kanhere, Sanjay K. Jha |
Design, Analysis and Implementation of a Novel Multiple Resource Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(8), pp. 1071-1086, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Microprocessor/microcomputer applications, scheduling and synchronization, Packet-Switched Networks |
13 | Fariza Sabrina, Salil S. Kanhere, Sanjay K. Jha |
Design, Analysis, and Implementation of a Novel Low Complexity Scheduler for Joint Resource Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(6), pp. 749-762, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
microprocessor/microcomputer applications, scheduling, distributed applications, Packet-switched networks |
13 | Heather Hanson, Stephen W. Keckler, Soraya Ghiasi, Karthick Rajamani, Freeman L. Rawson III, Juan Rubio 0001 |
Thermal response to DVFS: analysis with an Intel Pentium M. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 219-224, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
thermal measurement, microprocessor, temperature, DVFS, thermal management |
13 | Timothy Daryl Stanley, George Embrey, Daniel Prigmore, Leslie D. Fife, Scott Mikolyski, Don Colton |
Pedagogic value in understanding computer architecture of implementing the marie computer from null and lobur in the logic emulation software, multimedia logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE 2007, San Diego, California, USA, Saturday, June 9, 2007, pp. 66-71, 2007, ACM, 978-1-59593-797-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
education, computer architecture, microprocessor design, logic emulation |
13 | Aashish Phansalkar, Ajay Joshi, Lizy Kurian John |
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 412-423, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
microprocessor performance counters, clustering, benchmark, SPEC |
13 | Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang |
High Performance General-Purpose Microprocessors: Past and Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 21(5), pp. 631-640, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high performance general-purpose microprocessor, Godson processor, chip multiprocessors, instruction level parallelism, thread level parallelism, data level parallelism |
13 | Christophe Lécuyer, David C. Brock |
Biographies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 28(3), pp. 89-95, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gordon Moore, semiconductor industry, silicon technology, silicon device manufacture, Fairchild Semiconductor, Shockley Semiconductor, microprocessor, integrated circuit, DRAM, personal computer, chemistry, Moore's law, Intel |
13 | Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, David J. Lilja |
The exigency of benchmark and compiler drift: designing tomorrow's processors with yesterday's tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 20th Annual International Conference on Supercomputing, ICS 2006, Cairns, Queensland, Australia, June 28 - July 01, 2006, pp. 75-86, 2006, ACM, 1-59593-282-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
benchmark drift, compiler drift, microprocessor design |
13 | William Lloyd Bircher, Lizy K. John |
Power phase variation in a commercial server workload. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 350-353, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chipset, commercial workload characterization, memory, power, microprocessor, disk, program phase |
13 | Josef Goette, Marcel Jacomet, Markus Hager |
Using Dither to Improve the Performance of Lossy Sigma-Delta Modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 11-16, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Lossy sumvartriangle modulator, Ad con- Fpga-and microprocessor implementations, dither |
13 | Wei Wu 0024, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan |
A systematic method for functional unit power estimation in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 554-557, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
microprocessor, power estimation, performance counter |
13 | Pradip Bose |
Designing microprocessors with robust functionality and performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(6), pp. 5, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Reliability-aware microarchitecture, power-efficient design, microprocessor design |
13 | Shailender Chaudhry, Paul Caprioli, Sherman Yip, Marc Tremblay |
High-Performance Throughput Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(3), pp. 32-45, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hardware scout, CMP, multithreading, multicore, microprocessor, CMT |
13 | Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer |
An Experimental Study of Soft Errors in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(6), pp. 30-39, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture |
13 | Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari |
Bridging the Processor-Memory Performance Gapwith 3D IC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 556-564, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
three-dimensional integration 3-D ICs microprocessor cache design stream prefetching embedded DRAM |
13 | Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw |
A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 249-256, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
sensor network, energy efficiency, microprocessor, memory organization |
13 | Tohru Ishihara, Farzan Fallah |
A non-uniform cache architecture for low power system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 363-368, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, compiler, microprocessor, cache memory |
13 | Matthias Pfeffer, Theo Ungerer, Stephan Fuhrmann, Jochen Kreuzinger, Uwe Brinkschulte |
Real-Time Garbage Collection for a Multithreaded Java Microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 26(1), pp. 89-106, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Java microprocessor, real-time, garbage collection, multithreading, microcontroller |
13 | Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin |
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(2), pp. 155-168, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test |
13 | Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno |
Design methodology for semi custom processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 448-452, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design, methodology, synthesis, microprocessor, ASIC, core |
13 | Daniel J. Deleganes, Micah Barany, George L. Geannopoulos, Kurt Kreitzer, Anant P. Singh, Sapumal B. Wijeratne |
Low voltage swing logic circuits for a Pentium 4 processor integer core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 678-680, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
LVS, Pentium® 4 processor, integer core, low voltage swing, sense-amp, microprocessor, rotator, adder |
13 | Joydeep Ray, James C. Hoe |
High-level modeling and FPGA prototyping of microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 100-107, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture |
13 | John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft |
3D direct vertical interconnect microprocessors test vehicle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 141-146, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic |
13 | Li Chen, Srivaths Ravi 0001, Anand Raghunathan, Sujit Dey |
A scalable software-based self-test methodology for programmable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 548-553, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test |
13 | Francisco Barat, Rudy Lauwereins, Geert Deconinck |
Reconfigurable Instruction Set Processors from a Hardware/Software Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 28(9), pp. 847-862, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Reconfigurable instruction set processor overview, compiler, microprocessor, reconfigurable logic |
13 | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec |
Tarantula: A Vector Extension to the Alpha Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 281-292, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Power, Microprocessor, Bandwidth, High Performance, Cache Coherency, Virtual Memory, Instruction Set Architecture, Vector Processor |
13 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded software-based self-testing for SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 355-360, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
functional test, SoC test, VLSI test, microprocessor test |
13 | Li Chen, Sujit Dey |
Software-based diagnosis for processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 259-262, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
microprocessor, self-test, instruction, diagnostics |
13 | Brian W. Amick, Claude R. Gauthier, Dean Liu |
Macro-modeling concepts for the chip electrical interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 391-394, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VLSI power distribution, analog and I/O power delivery, high speed microprocessor design, inductance |
13 | Deependra Talla, Lizy Kurian John |
MediaBreeze: a decoupled architecture for accelerating multimedia applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(5), pp. 62-67, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
access and execute mechanisms, multimedia, prefetching, SIMD, hardware accelerators, decoupling, microprocessor design, general-purpose processors |
13 | Seppo Virtanen, Johan Lilius |
The TACO protocol processor simulation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, CODES 2001, Copenhagen, Denmark, 2001, pp. 201-206, 2001, ACM, 1-58113-364-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
simulation, protocol, microprocessor, codesign |
13 | Israel Koren, Zahava Koren |
Incorporating Yield Enhancement into the Floorplanning Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(6), pp. 532-541, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield |
13 | Paul Chang, Brion L. Keller, Sarala Paliwal |
Effective parallel processing techniques for the generation of test data for a logic built-in self test system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 374-379, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data |
13 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 384-393, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
13 | Prasad N. Golla, Eric C. Lin |
A Dynamic Scheduling Logic for Exploiting Multiple Functional Units in Single Ship Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1999 ACM Symposium on Applied Computing, SAC'99, San Antonio, Texas, USA, February 28 - March 2, 1999, pp. 466-473, 1999, ACM, 1-58113-086-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Tomasulo's algorithm, threaded architectures, computer architecture, multithreading, microprocessor |
13 | Vivek De, Shekhar Borkar |
Technology and design challenges for low power and high performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999, pp. 163-168, 1999, ACM, 1-58113-133-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
low-power design, memory, microprocessor, VLSI design |
13 | P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose |
Interconnect-Dominated VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 114-122, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion |
13 | Shannon V. Morton |
On-Chip Inductance Issues in Multiconductor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 921-926, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
alpha microprocessor, cross-talk, interconnect, noise, inductance, transmission line, capacitance, resistance, buses, semiconductor, RLC |
13 | Miroslav N. Velev, Randal E. Bryant |
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 200-212, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pipelined microprocessor verification, memory shadowing, Efficient Memory Model (EMM), circuit correspondence checking, symbolic simulation |
13 | Sebastián Sánchez 0001, Daniel Meziat, Melquiades Carbajo, Julio L. Medina, Enrique Bronchalo, Javier Rodríguez-Pacheco, Luis del Peral |
Control System for a Low Energy Particle Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10216-10220, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Special microprocessor applications, space electronics, calibration test, space physics, solar energetic particles, real-time system |
13 | Yossi Malka, Avi Ziv |
Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 644-649, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
21264, coverage anaysis, verification, architecture, validation, microprocessor, PowerPC, pseudo-random, Alpha |
13 | Hans Eisenmann, Frank M. Johannes |
Generic Global Placement and Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 269-274, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
13 | Alper Demir 0001, Amit Mehrotra, Jaijeet S. Roychowdhury |
Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 26-31, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
13 | Gustavo de Veciana, Margarida F. Jacome, Jian-Huei Guo |
Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 251-256, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
13 | Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta 0001 |
Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 263-268, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
13 | Asawaree Kalavade, Pratyush Moghé |
A Tool for Performance Estimation of Networked Embedded End-systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 257-262, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
verification, timing, design methodology, microprocessor |
13 | Johnson Kin, Munish Gupta, William H. Mangione-Smith |
The Filter Cache: An Energy Efficient Memory Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 184-193, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache |
13 | Olin Sibert, Phillip A. Porras, Robert Lindell |
An Analysis of the Intel 80x86 Security Architecture and Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 22(5), pp. 283-293, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Hardware security architecture, hardware implementation error, computer security, microprocessor, covert channels, penetration testing |
13 | Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung |
Register renaming for x86 superscalar design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 336-343, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Intel x86 superscalar design, storage conflicts, data lengths, register write, register read, hardware renaming schemes, aggressive superscalar machine model, parallel architectures, instruction level parallelism, simulation results, microprocessor chips, register renaming |
13 | Janusz Sosnowski, A. Kusmierczyk |
Pseudorandom versus Deterministic Testing of Intel 80x86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 329-336, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Intel 80/spl times/86 processors, computer testing, pseudorandom testing, microprocessor testing, deterministic testing |
13 | Santanu Chattopadhyay, S. Mitra 0001, Parimal Pal Chaudhuri |
Cellular automata based architecture of a database query processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 320-321, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
cellular automata based architecture, database query processor, programmable query processor chip, fast database access, multiple attractor cellular automata, class-relation storage, true/false classifier, classification, VLSI, query processing, relational databases, relational database, cellular automata, microprocessor chips, database machines |
13 | Preeti Ranjan Panda, Nikil D. Dutt |
1995 high level synthesis design repository. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 170-174, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
1995 high level synthesis design repository, VHDL language, behavioral finite state machines, behavioral level, computational complexity, high level synthesis, finite state machines, VHDL, microprocessors, hardware description languages, microprocessor chips, floating point units |
13 | Guido Araujo, Sharad Malik |
Optimal code generation for embedded memory non-homogeneous register architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 36-41, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation |
13 | Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller |
Emulation verification of the Motorola 68060. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 150-158, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
emulation verification, Motorola 68060, hardware logic emulation, configurable hardware, circuit verification, pseudo-random verification vectors, software application programs, formal verification, microprocessors, reconfigurable architectures, logic CAD, digital simulation, circuit analysis computing, RTL, hardware description languages, hardware description language, microprocessor chips, HDL, gate-level |
13 | Chuan-Yu Wang, Kaushik Roy 0001 |
Control unit synthesis targeting low-power processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 454-459, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
control unit synthesis, low-power processors, low-power decoding scheme, microprogrammed architecture, nanoprogrammed architecture, 8086 instruction set, instruction opcodes, computer architecture, logic design, encoding, decoding, microprocessor chips, graph embedding, instruction sets, microprogramming, CMOS circuits, logic minimization, system reliability, switching activity, minimisation of switching nets, pseudo-Boolean programming |
13 | Guillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O'Connor |
Incas: a cycle accurate model of UltraSPARC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 130-137, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cycle accurate model, UltraSPARC, Incas, message-passing mechanism, simulating concurrent modules, performance evaluation, C++, virtual machines, logic testing, microprocessor chips, performance estimates, diagnostics, tuning, RTL simulations, processor verification |
13 | Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter |
Combined DRAM and logic chip for massively parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 4-16, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits |
13 | John D. Bunda, Donald S. Fussell, William C. Athas |
Energy-efficient instruction set architecture for CMOS microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 298-305, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density |
13 | Goutam Debnath, Kathy Debnath, Roshan Fernando |
The Pentium processor-90/100, microarchitecture and low power circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 185-190, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIMOS integrated circuits, Pentium processor-90/100, low power circuit design, BiNMOS process, power consumption reduction, symmetric dual processing feature, multithreaded operating systems, 0.6 micron, 3.3 V, computer architecture, microarchitecture, integrated circuit design, microprocessor chips, 100 MHz |
13 | Giuseppe Ascia, Vincenzo Catania |
Design of a VLSI parallel processor for fuzzy computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 315-320, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit |
13 | Venkatesh Akella, Ganesh Gopalakrishnan |
Specification and Validation of Control-Intensive IC's in hopCP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 20(6), pp. 405-423, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations |
13 | Vitit Kantabutra |
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(12), pp. 1495-1499, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders |
13 | Jeffrey O. Smith, Kliffton M. Black, Farhad Kamangar, Jack Fitzer |
The University of Texas at Arlington Autonomous Aerial Vehicle - An overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 2(3), pp. 299-320, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
microprocessor control, optimal control, robust control, Autonomous vehicle, inertial navigation |
13 | Israel Koren, Ofra Zinaty |
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(8), pp. 1030-1037, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
high-precision floating-point numbers, extended double precision format, IEEE standard P754, floating-point numeric coprocessor, fast adder, digital arithmetic, execution time, microprocessor chips, approximation theory, elementary functions, function evaluation, rational approximations, silicon area, fast multiplier |
13 | Arvin Park, Matthew K. Farrens |
Address compression through base register caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 193-199, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
CPU performance, microprocessor systems, locality, bandwidth |
13 | Fred J. Taylor, Rabinder Gill, Jim Joseph, Jeff Radke |
A 20 Bit Logarithmic Number System Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(2), pp. 190-200, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
logarithmic number system processor, arithmetic processor, partitioned memory, integrated Schottky logic, 20 bit, satellite computers, performance evaluation, performance evaluation, architecture, computer architecture, digital arithmetic, PLA, microprocessor chips, table lookup, table lookup, ROM, field effect integrated circuits |
13 | Takashi Nanya, Toshiaki Kawamura |
Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(1), pp. 14-24, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
error-secure interfaces, totally self-checking systems, Intel 8080, strongly fault-secure processors, error-propagating interfaces, fault tolerant computing, computer architecture, automatic testing, microprocessor chips, digital system, computer interfaces, 8 bit |
13 | Li Shen, Stephen Y. H. Su |
A Functional Testing Method for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(10), pp. 1288-1293, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
functional testing method, control fault model, register transfer language, k-out-of-m codes, test generation time, microprocessors, microprocessor chips, computer testing, testing requirements |
13 | F. Matthew Rhodes, Joseph J. Dituri, Glenn H. Chapman, Bruce E. Emerson, Antonio M. Soares, Jack I. Raffel |
A Monolithic Hough Transform Processor Based on Restructurable VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 10(1), pp. 106-110, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
pixel grouping, WSI technology, monolithic Hough transform processor, restructurable VLSI, wafer-scale-integration technology, PC board, monolithic integrated circuits, image processing, VLSI, transforms, computerised pattern recognition, digital arithmetic, circuit CAD, microprocessor chips, CAD tools, PCB, linear feature extraction |
13 | Lorenz A. Schmitt, Stephen S. Wilson |
The AIS-5000 Parallel Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 10(3), pp. 320-330, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
AIS-5000, parallel memory organization, image-based algorithms, computer vision, computer vision, parallel architecture, parallel architectures, computerised picture processing, computerised picture processing, microprocessor chips, parallel processor, SIMD architecture |
13 | Satish M. Thatte, Jacob A. Abraham |
Test Generation for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 29(6), pp. 429-441, 1980. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
complexity of tests, functional level fault models, Architecture models, test programs, microprocessor architecture |
13 | Gerard G. L. Meyer, Gerald M. Masson |
An Efficient Fault Diagnosis Algorithm for Symmetric Multiple Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(11), pp. 1059-1063, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
modular networks, fault syndromes, microprocessor, Diagnosis algorithm |
13 | Kilnam Chon |
Information processing in electricity distribution systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Annual Conference (2) ![In: Proceedings 1978 ACM Annual Conference, Washington, DC, USA, December 4-6, 1978, Volume II, pp. 980-984, 1978, ACM, 978-0-89791-000-2. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
Distribution system, Reliability, Control, Redundancy, Automation, Microprocessor, Information processing, Decentralization, Data base, Electricity |
13 | Richard G. Cooper |
The Distributed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(11), pp. 1123-1132, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
Array of computers, distributed pipeline (DP), multiple-instruction multiple-data-stream (MIMD) computer, distributed computer, multiprocessor, pipeline, computer network, computer architecture, microprocessor, microcomputer |
13 | Samuel H. Fuller, Victor R. Lesser, Gordon Bell, Charles H. Kaman |
The Effects of Emerging Technology and Emulation Requirements on Microprogramming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(10), pp. 1000-1009, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
semiconductor technology, microprocessor, interpretation, Emulation, microprogramming |
12 | Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh |
Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 285, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic inspection, reconfigurable microprocessors, fpga |
12 | Xiaochen Guo, Engin Ipek, Tolga Soyata |
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 371-382, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
STT-MRAM, power-efficiency |
12 | Kypros Constantinides, Todd M. Austin |
Using introspective software-based testing for post-silicon debug and repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 537-542, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
12 | Peter M. Chen |
Transistors to toys: teaching systems to freshmen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 6th International Conference on Virtual Execution Environments, VEE 2010, Pittsburgh, Pennsylvania, USA, March 17-19, 2010, pp. 1-2, 2010, ACM, 978-1-60558-910-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
education |
12 | Shlomi Dolev, Yinnon A. Haviv, Mooly Sagiv |
Self-stabilization preserving compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 31(6), pp. 22:1-22:42, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Compilers, self-stabilization, abstract state machines |
12 | George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 6(2), pp. 124-134, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith 0001, David M. Brooks |
Voltage emergency prediction: Using signatures to reduce operating margins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 18-29, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
12 | Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar |
Circuit techniques for dynamic variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 4-7, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors |
12 | Dilip D. Kandlur, Tom W. Keller |
Green data centers and hot chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 888-890, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
architecture, data centers, energy management |
12 | Thomas Baumann, Doris Schmitt-Landsiedel, Christian Pacha |
Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 947-950, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
variability-aware design, robustness, micro-architecture |
12 | Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow |
A Desktop Computer with a Reconfigurable Pentium®. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 5:1-5:15, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor |
12 | John N. Coleman, Christopher I. Softley, Jiri Kadlec, Rudolf Matousek, Milan Tichý, Zdenek Pohl, Antonin Hermanek, Nico F. Benschop |
The European Logarithmic Microprocesor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(4), pp. 532-546, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
General, High-Speed Arithmetic |
12 | Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh |
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1788-1797, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle |
Radio frequency identification prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 29:1-29:22, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low-power, RFID, prototyping, Design automation |
12 | Uwe Brinkschulte, Mathias Pacher |
A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 5-7 May 2008, Orlando, Florida, USA, pp. 399-404, 2008, IEEE Computer Society, 978-0-7695-3132-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Control theory in high-end microprocessors, real-time microprocessors, IPC rate |
12 | Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W. Kellington, John Schumann, Pia N. Sanda |
Statistical Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 122-127, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David M. Brooks |
System level analysis of fast, per-core DVFS using on-chip switching regulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 123-134, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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12 | Duo Li, Sheldon X.-D. Tan, Murli Tirumala |
Architecture-level thermal behavioral characterization for multi-core microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 456-461, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Sebastian Rohde, Thomas Eisenbarth 0001, Erik Dahmen, Johannes Buchmann 0001, Christof Paar |
Fast Hash-Based Signatures on Constrained Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CARDIS ![In: Smart Card Research and Advanced Applications, 8th IFIP WG 8.8/11.2 International Conference, CARDIS 2008, London, UK, September 8-11, 2008. Proceedings, pp. 104-117, 2008, Springer, 978-3-540-85892-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
hash based cryptography, Merkle signature scheme, digital signatures, Embedded security |
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