Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
14	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
14	Irith Pomeranz, Sudhakar M. Reddy	Static compaction for two-pattern test sets.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	two-pattern test sets, static compaction procedure, test set size reduction, redundant tests removal, redundant patterns removal, CMOS stuck open faults, reordering of tests, digital logic circuits, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, combinational circuits, combinational circuits, automatic testing, fault coverage, CMOS logic circuits, delay faults
14	Jacob Savir	Generator choices for delay test.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test
14	Manfred Henftling, Hannes C. Wittmann, Kurt Antreich	A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization.	ICCAD	1995	DBLP DOI BibTeX RDF	test generation, ATPG, propagation
14	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
14	Arno Kunzmann, Frank Böhland	Self-test of sequential circuits with deterministic test pattern sequences.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Deterministic Test Pattern Sequences, Field-Programmable Gate-Arrays (FPGAs), Design-for-Testability, Sequential Circuits, Automatic Test Pattern Generation (ATPG), Self-Test
9	S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay	Customizing pattern set for test power reduction via improved X-identification and reordering.	ISLPED	2010	DBLP DOI BibTeX RDF	don't care bits, runtime leakage power, vector reordering, x-fill, dynamic power
9	Yung-Chih Chen, Chun-Yao Wang	Node addition and removal in the presence of don't cares.	DAC	2010	DBLP DOI BibTeX RDF	node addition and removal, node merging, observability don't care, logic implication
9	Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico	Markov source based test length optimized SCAN-BIST architecture.	ISQED	2009	DBLP DOI BibTeX RDF
9	Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur	Proactive management of X's in scan chains for compression.	ISQED	2009	DBLP DOI BibTeX RDF
9	Alejandro Czutro, Ilia Polian, Matthew Lewis 0004, Piet Engelke, Sudhakar M. Reddy, Bernd Becker 0001	TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.	VLSI Design	2009	DBLP DOI BibTeX RDF
9	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	Defect Aware to Power Conscious Tests - The New DFT Landscape.	VLSI Design	2009	DBLP DOI BibTeX RDF
9	Da Wang, Yu Hu 0001, Huawei Li 0001, Xiaowei Li 0001	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
9	Roberto Gómez 0001, Alejandro Girón, Víctor H. Champac	A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Interconnection opens, Boolean testing, Favorable logic conditions, Test generation methodology, Coupling capacitances
9	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
9	Anshuman Chandra, Felix Ng, Rohit Kapur	Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction.	DATE	2008	DBLP DOI BibTeX RDF
9	Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty	Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme.	DATE	2008	DBLP DOI BibTeX RDF
9	Wei-Min Wu, Min-Chuan Chen	USAT: An Integrated Platform for Satisfiability Solving and Model Checking.	CSSE (4)	2008	DBLP DOI BibTeX RDF
9	Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi	Enhancing the Testability of RTL Designs Using Efficiently Synthesized Assertions.	ISQED	2008	DBLP DOI BibTeX RDF	Assertion Synthesis, Assertion Unification, Online Testing
9	Hui Liu, Huawei Li 0001, Yu Hu 0001, Xiaowei Li 0001	A Scan-Based Delay Test Method for Reduction of Overtesting.	DELTA	2008	DBLP DOI BibTeX RDF	overtesting, SeBoS, delay test, IR drop
9	Yinlei Yu, Cameron Brien, Sharad Malik	Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.	VLSI Design	2008	DBLP DOI BibTeX RDF
9	Ilia Polian, Hideo Fujiwara	Functional Constraints vs. Test Compression in Scan-Based Delay Testing.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Overtesting prevention, Scan-based delay test, Test compression, Functional constraints
9	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
9	Ozgur Sinanoglu, Philip Schremmer	Diagnosis, modeling and tolerance of scan chain hold-time violations.	DATE	2007	DBLP DOI BibTeX RDF
9	Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer	Reduction of detected acceptable faults for yield improvement via error-tolerance.	DATE	2007	DBLP DOI BibTeX RDF
9	Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab	Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.	ETS	2007	DBLP DOI BibTeX RDF
9	Stefan Holst, Hans-Joachim Wunderlich	Adaptive Debug and Diagnosis without Fault Dictionaries.	ETS	2007	DBLP DOI BibTeX RDF	VLSI, Test, Debug, Diagnosis
9	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Systematic Scan Reconfiguration.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic scan reconfiguration, test data compression technique, single-stuck fault test sets, transition fault test sets, scan chains
9	Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo	Estimation of delay test quality and its application to test generation.	ICCAD	2007	DBLP DOI BibTeX RDF
9	Sanjiv Taneja	Accelerating Yield Ramp through Real-Time Testing.	IOLTS	2007	DBLP DOI BibTeX RDF
9	Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham	Reducing verification overhead with RTL slicing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	verification, test, CAD
9	Nagesh Nagapalli	DFT and Test: Ensuring Product Quality.	ISQED	2007	DBLP DOI BibTeX RDF
9	Jennifer Dworak	An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting.	VTS	2007	DBLP DOI BibTeX RDF
9	Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
9	Jacob A. Abraham, Daniel G. Saab	Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.	VLSI Design	2007	DBLP DOI BibTeX RDF
9	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan	Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m).	VLSI Design	2007	DBLP DOI BibTeX RDF
9	Nitin Yogi, Vishwani D. Agrawal	Spectral RTL Test Generation for Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
9	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
9	Gang Zeng, Hideo Ito	Concurrent core test for SOC using shared test set and scan chain disable.	DATE	2006	DBLP DOI BibTeX RDF
9	Ilia Polian, Hideo Fujiwara	Functional constraints vs. test compression in scan-based delay testing.	DATE	2006	DBLP DOI BibTeX RDF	overtesting prevention, scan-based delay test, test compression, functional constraints
9	Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus	Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes.	DSD	2006	DBLP DOI BibTeX RDF
9	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.	ETS	2006	DBLP DOI BibTeX RDF
9	Gennette Gill, Ankur Agiwal, Montek Singh, Feng Shi 0010, Yiorgos Makris	Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines.	ASYNC	2006	DBLP DOI BibTeX RDF
9	Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki	FCSCAN: an efficient multiscan-based test compression technique for test cost reduction.	ASP-DAC	2006	DBLP DOI BibTeX RDF
9	Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski	Using a software testing technique to identify registers for partial scan implementation.	SBCCI	2006	DBLP DOI BibTeX RDF	hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
9	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	A novel framework for faster-than-at-speed delay test considering IR-drop effects.	ICCAD	2006	DBLP DOI BibTeX RDF
9	Zhaohui Fu, Sharad Malik	Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search.	ICCAD	2006	DBLP DOI BibTeX RDF	MinCostSAT, optimization, branch-and-bound, Boolean satisfiability
9	Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen	A broadcast-based test scheme for reducing test size and application time.	ISCAS	2006	DBLP DOI BibTeX RDF
9	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding.	IOLTS	2006	DBLP DOI BibTeX RDF
9	Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya	On finding the minimum test set of a BDD-based circuit.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	binary decision diagram (BDD), multiplexors, network flow, stuck-at faults, VLSI testing
9	Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty	An Approach to Minimizing Functional Constraints.	DFT	2006	DBLP DOI BibTeX RDF
9	Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz	Test Generation for Open Defects in CMOS Circuits.	DFT	2006	DBLP DOI BibTeX RDF
9	Richard Putman, Rahul Gawde	Enhanced Timing-Based Transition Delay Testing for Small Delay Defects.	VTS	2006	DBLP DOI BibTeX RDF
9	Xijiang Lin, Janusz Rajski	The Impacts of Untestable Defects on Transition Fault Testing.	VTS	2006	DBLP DOI BibTeX RDF
9	Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty	Silicon Evaluation of Logic Proximity Bridge Patterns.	VTS	2006	DBLP DOI BibTeX RDF
9	Debasis Mitra 0002, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu	Test Pattern Generation for Power Supply Droop Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
9	Loganathan Lingappan, Niraj K. Jha	Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
9	Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu	A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
9	Maria K. Michael, Spyros Tragoudas	Function-based compact test pattern generation for path delay faults.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
9	Hamidreza Hashempour, Fabrizio Lombardi	Application of Arithmetic Coding to Compression of VLSI Test Data.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Golomb coding, SoC, ATE, arithmetic coding, Huffman coding, Test data compression
9	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
9	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Efficient techniques for transition testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test chain, test data volume reduction, transition faults, Test application time reduction, yield loss
9	Jonathan R. Carter, Sule Ozev, Daniel J. Sorin	Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown.	DATE	2005	DBLP DOI BibTeX RDF
9	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.	DATE	2005	DBLP DOI BibTeX RDF
9	Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho	Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits.	DATE	2005	DBLP DOI BibTeX RDF
9	René Krenz, Elena Dubrova	A fast algorithm for finding common multiple-vertex dominators in circuit graphs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
9	René Krenz, Elena Dubrova	Improved Boolean function hashing based on multiple-vertex dominators.	ASP-DAC	2005	DBLP DOI BibTeX RDF
9	Yung-Chieh Lin, Feng Lu 0002, Kai Yang, Kwang-Ting Cheng	Constraint extraction for pseudo-functional scan-based delay testing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
9	Sameer Goel, Rubin A. Parekhji	Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	delay fault simulation, N-detect coverage metrics, Delay fault test, test optimizations
9	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
9	Zhigang Jiang, Sandeep K. Gupta 0001	Threshold testing: Covering bridging and other realistic faults.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
9	Vishwani D. Agrawal, Alok S. Doshi	Concurrent Test Generation.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
9	Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay	Flip-flop chaining architecture for power-efficient scan during test application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
9	Katherine Shu-Min Li, Chung-Len Lee 0001, Tagin Jiang, Chauchin Su, Jwu E. Chen	Finite State Machine Synthesis for At-Speed Oscillation Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
9	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi	Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
9	Ondrej Novák, Jirí Zahrádka, Zdenek Plíva	COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits.	EDCC	2005	DBLP DOI BibTeX RDF
9	Maria K. Michael, Kyriakos Christou, Spyros Tragoudas	Towards finding path delay fault tests with high test efficiency using ZBDDs.	ICCD	2005	DBLP DOI BibTeX RDF
9	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-based delay fault self-testing of pipelined processor cores.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
9	René Krenz	Efficient computation of dominators in multiple-output circuit graphs.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
9	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz	On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.	DFT	2005	DBLP DOI BibTeX RDF
9	Roberto Gómez 0001, Alejandro Girón, Víctor H. Champac	Test of Interconnection Opens Considering Coupling Signals.	DFT	2005	DBLP DOI BibTeX RDF
9	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda	Should Illinois-Scan Based Architectures be Centralized or Distributed?	DFT	2005	DBLP DOI BibTeX RDF
9	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On Low-Capture-Power Test Generation for Scan Testing.	VTS	2005	DBLP DOI BibTeX RDF
9	Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed	Pattern Generation and Estimation for Power Supply Noise Analysis.	VTS	2005	DBLP DOI BibTeX RDF
9	Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew	Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.	VTS	2005	DBLP DOI BibTeX RDF
9	Aniket, Ravishankar Arunachalam	Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
9	Ramaprasath Vilangudipitchai, Poras T. Balsara	Power Switch Network Design for MTCMOS.	VLSI Design	2005	DBLP DOI BibTeX RDF
9	Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer	Structural search for RTL with predicate learning.	DAC	2005	DBLP DOI BibTeX RDF	learning, satisfiability, interval arithmetic, predicate abstraction
9	Kohei Miyase, Seiji Kajihara	XID: Don't care identification of test patterns for combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
9	Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee 0001	Embedded deterministic test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
9	Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.	MTV	2004	DBLP DOI BibTeX RDF
9	Paolo Bernardi, Guido Masera, Federico Quaglio, Matteo Sonza Reorda	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study.	DATE	2004	DBLP DOI BibTeX RDF
9	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	Designing Self Test Programs for Embedded DSP Cores.	DATE	2004	DBLP DOI BibTeX RDF
9	Wu-Tung Cheng, Kun-Han Tsai, Yu Huang 0005, Nagesh Tamarapalli, Janusz Rajski	Compactor Independent Direct Diagnosis.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
9	Melvin A. Breuer, Sandeep K. Gupta 0001, Shahin Nazarian	Efficient Identification of Crosstalk Induced Slowdown Targets.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	required time, slow-down effect, filters, Crosstalk, static timing analysis, extractors
9	Melvin A. Breuer	Intelligible Test Techniques to Support Error-Tolerance.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
9	Petr Fiser, Hana Kubátová	Survey of the Algorithms in the Column-Matching BIST Method.	IOLTS	2004	DBLP DOI BibTeX RDF
9	Saravanan Padmanaban, Spyros Tragoudas	An Adaptive Path Delay Fault Diagnosis Methodology.	ISQED	2004	DBLP DOI BibTeX RDF
9	Abhishek Singh 0001, Chintan Patel, Jim Plusquellic	Fault Simulation Model for i{DDT} Testing: An Investigation.	VTS	2004	DBLP DOI BibTeX RDF