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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18369 occurrences of 5291 keywords
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Results
Found 50014 publication records. Showing 49999 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Gregg N. Hoyer, Gin Yee, Carl Sechen |
Locally clocked pipelines and dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(1), pp. 58-62, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9), pp. 803-818, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Manjit Borah, Robert Michael Owens, Mary Jane Irwin |
Recent Developments in Performance Driven Steiner Routing: An Overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 137-142, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Hannah Honghua Yang, D. F. Wong 0001 |
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 150-155, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | A. Khanna, John A. Zinky |
The Revised ARPANET Routing Metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM Symposium on Communications Architectures & Protocols, SIGCOMM 1989, Austin, TX, USA, September 19-22, 1989, pp. 45-56, 1989, ACM, 0-89791-332-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
ARPANET |
18 | Tommaso Rizzo, József Stéger, Péter Pollner, István Csabai, Gábor Vattay |
High quality queueing information from accelerated active network tomography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TRIDENTCOM ![In: 4th International Conference on Testbeds & Research Infrastructures for the DEvelopment of NeTworks & COMmunities (TRIDENTCOM 2008), March 18-20, 2008, Innsbruck, Austria, pp. 22, 2008, ICST, 978-963-9799-24-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
oneway delay measurement, queueing delay tomography |
18 | Wafa Berrayana, Ryad Ben-El-Kezadri, Farouk Kamoun, Guy Pujolle |
DelayEDD-HCCA and RT-HCCA: two new IEEE 802.11 e schemes based HCCA supporting real-time applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiMedia ![In: Proceedings of the 2nd International Conference on Mobile Multimedia Communications, MobiMedia 2006, Alghero, Italy, September 18-20, 2006, pp. 10, 2006, ACM, 1-59593-517-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay EDD, simulation, QoS, real-time applications, IEEE 802.11e, delay bound, HCCA |
18 | Sameer Goel, Rubin A. Parekhji |
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 330-336, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay fault simulation, N-detect coverage metrics, Delay fault test, test optimizations |
18 | Muhammad Nummer, Manoj Sachdev |
Testing high-performance pipelined circuits with slow-speed testers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 506-521, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
high-performance testing, Delay-fault testing, design for delay testability |
18 | Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan |
Global interconnect sizing and spacing with consideration of coupling capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 628-633, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance |
18 | Tianxiong Xue, Ernest S. Kuh |
Post routing performance optimization via multi-link insertion and non-uniform wiresizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 575-580, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
post routing performance optimization, link insertion and wiresizing, delay skew, routing area, delay |
18 | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
A single chip, pipelined, cascadable, multichannel, signal processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 150-155, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron |
18 | Tahir Nawaz Minhas, Markus Fiedler, Patrik Arlos |
Quantification of packet delay variation through the coefficient of throughput variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the 6th International Wireless Communications and Mobile Computing Conference, IWCMC 2010, Caen, France, June 28 - July 2, 2010, pp. 336-340, 2010, ACM, 978-1-4503-0062-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
coefficient of throughput variation, network measurement traffice shapping, packet delay variation, traffic shaper, performance analysis, throughput |
18 | Jin-Tai Yan, Zhi-Wei Chen |
Resource-constrained timing-driven link insertion for critical delay reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 119-122, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
critical delay, link insertion, non-tree |
18 | Emre Salman, Eby G. Friedman |
Methodology to achieve higher tolerance to delay variations in synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 447-452, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
delay uncertainty, environmental variation, robust circuit, process variation, tolerance |
18 | Fotis N. Koumboulis, Nikolaos D. Kouvakas, Paraskevas N. Paraskevopoulos |
Dynamic disturbance rejection controllers for neutral time delay systems with application to a central heating system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 52(7), pp. 1084-1094, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
neutral time delay, disturbance rejection, measurable disturbances, central heating, linearization |
18 | Wei Gao 0006, Qinghua Li, Bo Zhao 0009, Guohong Cao |
Multicasting in delay tolerant networks: a social network perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiHoc ![In: Proceedings of the 10th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, MobiHoc 2009, New Orleans, LA, USA, May 18-21, 2009, pp. 299-308, 2009, ACM, 978-1-60558-531-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
community, social network, multicast, delay tolerant network, centrality |
18 | Huimin Xiao |
Stability of Hopfield Neural Networks with Time-Varying Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 375-382, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
neural networks, Stability, time-delay, Lyapunov functions |
18 | Valentina Martina, Michele Garetto, Emilio Leonardi |
Delay-throughput performance in mobile ad-hoc networks with heterogeneous nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSWiM ![In: Proceedings of the 12th International Symposium on Modeling Analysis and Simulation of Wireless and Mobile Systems, MSWiM 2009, Tenerife, Canary Islands, Spain, October 26-19, 2009, pp. 63-72, 2009, ACM, 978-1-60558-616-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
delay-throughput trade-offs, scaling laws |
18 | Eun Cheol Kim, Jin Young Kim 0001 |
Performance Evaluation of PN Code Acquisition with Delay Diversity Receiver for TH-UWB System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2009, International Conference, Seoul, Korea, June 29-July 2, 2009, Proceedings, Part II, pp. 226-236, 2009, Springer, 978-3-642-02456-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Delay diversity receiver, equal gain combining (EGC), mean acquisition time, pseudo-noise (PN) code acquisition, time hopping-ultra wideband (TH-UWB) system |
18 | N. Pete Sedcole, Peter Y. K. Cheung |
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(2), pp. 10:1-10:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield |
18 | S. V. Narasimhan, Nandini Basumallick, Ratana Chaitanya |
Improved phase estimation based on complete bispectrum and modified group delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Image Video Process. ![In: Signal Image Video Process. 2(3), pp. 261-274, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bispectrum, Modified group delay, Non-minimum phase system identification, Phase estimation |
18 | Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl |
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(2), pp. 251-261, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
substitution box (S-box), inversion in the finite field GF($28$), standard cell implementation, Advanced Encryption Standard (AES), power consumption, silicon area, critical path delay |
18 | Najet Boughanmi, Yeqiong Song |
A New Routing Metric for Satisfying Both Energy and Delay Constraints in Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(2), pp. 137-143, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
delivery rate, wireless sensor network, routing, real-time, delay, energy, lifetime |
18 | Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 71-78, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
energy-delay, out-of-order embedded processor, resource resizing, performance, architecture |
18 | Marcus Brenner, Armin Zimmermann |
Analysis of Delay Time Distributions in Multistage Interconnection Networks Considering Multicast Traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: Proceedings of The Seventh IEEE International Symposium on Networking Computing and Applications, NCA 2008, July 10-12, 2008, Cambridge, Massachusetts, USA, pp. 236-239, 2008, IEEE Computer Society, 978-0-7695-3192-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Quality of Service, performance analysis, multicasting, Multistage interconnection networks, delay distributions |
18 | Jyh-Horng Wen, Hsi-Chou Hsu |
Adaptive Filter for Delay Line Combination (DLC) Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CNSR ![In: Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 5-8 May 2008, Halifax, Nova Scotia, Canada, pp. 410-414, 2008, IEEE Computer Society, 978-0-7695-3135-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
impulse radio (IR), delay line combination (DLC) receivers, ultra-wideband (UWB) |
18 | Antonios Skordylis, Niki Trigoni |
Delay-bounded routing in vehicular ad-hoc networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiHoc ![In: Proceedings of the 9th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, MobiHoc 2008, Hong Kong, China, May 26-30, 2008, pp. 341-350, 2008, ACM, 978-1-60558-073-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
minimum cost forwarding, routing, ad hoc network, delay, VANET, vehicular network, inter-vehicle communication |
18 | György Dán, Viktória Fodor |
Delay Bounds and Scalability for Overlay Multicast. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Networking ![In: NETWORKING 2008, Ad Hoc and Sensor Networks, Wireless Networks, Next Generation Internet , 7th International IFIP-TC6 Networking Conference, Singapore, May 5-9, 2008, Proceedings, pp. 227-239, 2008, Springer, 978-3-540-79548-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Scalability, Delay, Overlay multicast, Large-deviation theory |
18 | Mirco Musolesi, Cecilia Mascolo |
A framework for multi-region delay tolerant networking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wireless Networks and Systems for Developing Regions ![In: Proceedings of the 2008 ACM Workshop on Wireless Networks and Systems for Developing Regions, San Francisco, California, USA, September 19, 2007, pp. 37-42, 2008, ACM, 978-1-60558-190-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
communication paradigms, multi-region protocols, persistent caching, push/pull architecture, delay tolerant networking, data replication |
18 | Joris Walraevens, Dieter Fiems, Herwig Bruneel |
Analysis of the Transient Delay in a Discrete-Time Buffer with Batch Arrivals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Fifth International Conference on Information Technology: New Generations (ITNG 2008), 7-8 April 2008, Las Vegas, Nevada, USA, pp. 1208-1209, 2008, IEEE Computer Society, 978-0-7695-3099-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
delay characteristics, performance, Queueing theory, generating functions |
18 | Geng Ji 0002 |
Disturbance Attenuating Controller Design for a Class of Nonlinear Systems with Unknown Time-Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2008, 5th International Symposium on Neural Networks, ISNN 2008, Beijing, China, September 24-28, 2008, Proceedings, Part I, pp. 319-329, 2008, Springer, 978-3-540-87731-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Disturbance attenuation, input-to-state practically stable, adaptive neural network control, nonlinear time-delay systems |
18 | Zhi-Ting Lin, Yugui Qu, Qing-Hua Wang, Baohua Zhao |
E-Scheme in Delay-Tolerant Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APNOMS ![In: Challenges for Next Generation Network Operations and Service Management, 11th Asia-Pacific Network Operations and Management Symposium, APNOMS 2008, Beijing, China, October 22-24, 2008. Proceedings, pp. 1-10, 2008, Springer, 978-3-540-88622-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
E-Scheme, routing approach, Delay-Tolerant Network |
18 | Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan |
On efficient generation of instruction sequences to test for delay defects in a processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 279-284, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
native-mode self-test, delay test, software based self-test |
18 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De |
Analytical Model for the Propagation Delay of Through Silicon Vias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 553-556, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D integrated circuits, propagation delay model, dimensional analysis, TSV |
18 | Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
Timing-Aware Multiple-Delay-Fault Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 246-253, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
defect-diagnosis, diagnosis, ATPG, DFT, delay-testing |
18 | Hidetoshi Kobayashi, Kazumasa Takami |
Algorithm for Selecting either an Overlay or Flat Route Based on the Amount of the Delay Measurement Load on the Home Agent in a Hierarchical Mobile IPv6 Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEW2AN ![In: Next Generation Teletraffic and Wired/Wireless Advanced Networking, 8th International Conference, NEW2AN and 1st Russian Conference on Smart Spaces, ruSMART 2008, St. Petersburg, Russia, September 3-5, 2008. Proceedings, pp. 234-245, 2008, Springer, 978-3-540-85499-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Packet delay, Route Selection, Hierarchical Mobile IPv6 |
18 | Igor Keller, King Ho Tam, Vinod Kariat |
Challenges in gate level modeling for delay and SI at 65nm and below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 468-473, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
delay calculation, gate characterization, gate modeling |
18 | Wanqing Tu, Cormac J. Sreenan, Weijia Jia 0001 |
Worst-Case Delay Control in Multigroup Overlay Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(10), pp. 1407-1419, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Worst-case delay control, multiple groups, overlay multicast, traffic control |
18 | Hiroki Arimura, Takeaki Uno |
An efficient polynomial space and polynomial delay algorithm for enumeration of maximal motifs in a sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 13(3), pp. 243-262, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Maximal motif, Data mining, Algorithm, Delay, Polynomial time, Pattern discovery, Enumeration, Motif, Sequence mining, Closed pattern, Closed itemset |
18 | Cong Liu 0001, Jie Wu 0001 |
Scalable routing in delay tolerant networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiHoc ![In: Proceedings of the 8th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, MobiHoc 2007, Montreal, Quebec, Canada, September 9-14, 2007, pp. 51-60, 2007, ACM, 978-1-59593-684-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
motion cycle, simulation, scalability, delay tolerant networks (DTNs), contact, hierarchical routing, delivery |
18 | Kazuyoshi Murata, Megumi Nakamura, Yu Shibuya, Itaru Kuramoto, Yoshihiro Tsujino |
Visual Feedback to Reduce the Negative Effects of Message Transfer Delay on Voice Chatting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (9) ![In: Human Interface and the Management of Information. Interacting in Information Environments, Symposium on Human Interface 2007, Held as Part of HCI International 2007, Beijing, China, July 22-27, 2007, Proceedings, Part II, pp. 95-101, 2007, Springer, 978-3-540-73353-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Message Transfer Delay, Unintentional Interruption, Status Monitor, Voice Chatting |
18 | N. Pete Sedcole, Peter Y. K. Cheung |
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 178-187, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield |
18 | Jun-Zhao Sun |
Query optimization based on user-specified delay item for wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2007, Honolulu, Hawaii, USA, August 12-16, 2007, pp. 493-498, 2007, ACM, 978-1-59593-695-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sensor networks, delay, query optimization |
18 | Hamidou Tembine, Eitan Altman, Rachid El Azouzi |
Asymmetric delay in evolutionary games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VALUETOOLS ![In: Proceedings of the 2nd International Conference on Performance Evaluation Methodolgies and Tools, VALUETOOLS 2007, Nantes, France, October 22-27, 2007, pp. 36, 2007, ICST/ACM, 978-963-9799-00-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hawk and dove game, multiple access game, delay differential equation, replicator dynamics, evolutionary stable strategy |
18 | Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda |
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 411-416, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault-emulation, software-based testing, FPGA, path-delay |
18 | Daniel A. Vivanco, Anura P. Jayasumana |
A Measurement-Based Modeling Approach for Network-Induced Packet Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 32nd Annual IEEE Conference on Local Computer Networks (LCN 2007), 15-18 October 2007, Clontarf Castle, Dublin, Ireland, Proceedings, pp. 175-182, 2007, IEEE Computer Society, 0-7695-3000-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Inter-packet gaps, Delay, Internet Measurments |
18 | Stephen Farrell, Vinny Cahill, Dermot Geraghty, Ivor Humphreys, Paul McDonald |
When TCP Breaks: Delay- and Disruption- Tolerant Networking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Comput. ![In: IEEE Internet Comput. 10(4), pp. 72-78, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
TCP, delay-tolerant networking, disruption-tolerant networking |
18 | Mihaela van der Schaar, Yiannis Andreopoulos, Zhiping Hu |
Optimized Scalable Video Streaming over IEEE 802.11a/e HCCA Wireless Networks under Delay Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 5(6), pp. 755-768, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IEEE 802.11e WLANs, delay-constrained video streaming, QoS-enabled MAC scheduling, token rate adaptation, cross-layer optimization, link adaptation |
18 | José Niño-Mora |
Marginal productivity index policies for scheduling a multiclass delay-/loss-sensitive queue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Queueing Syst. Theory Appl. ![In: Queueing Syst. Theory Appl. 54(4), pp. 281-312, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Multiclass queue, Multi-queue switch, Delay-sensitive, Loss-sensitive, Restless bandits, Work-cost analysis, Index policies, Bias optimality, Scheduling, Conservation laws, Finite buffers |
18 | Zhizhong Zhang, Fang Cheng, Jiangtao Luo, Qijian Mao, Jun Wang, Shaofeng Qiu |
Preemptive and non-preemptive scheduling of optical switches with configuration delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 49(5), pp. 653-664, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
configuration delay, scheduling, optical switches |
18 | Bipul C. Paul, Kaushik Roy 0001 |
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 115-124, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive body bias design, statistical analysis, process variation, delay fault testing |
18 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(2), pp. 125-142, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
universal tests, stuck-at fault, path-delay fault, synthesis-for-testability, unate function, symmetric boolean function |
18 | Yassine Boujelben, André Girard, Jean-Charles Grégoire |
A Sequential Algorithm for Constructing Delay-Constrained Multirings for Multipoint-to-Multipoint Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Telecommun. Syst. ![In: Telecommun. Syst. 31(1), pp. 43-59, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Multipoint-to-multipoint, Stability, Delay bounds, Multiring, Lagrangean relaxation |
18 | József Sziray |
Test Calculation for Logic and Delay Faults in Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 20-32, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic |
18 | Olivier Dousse, Christina Tavoularis, Patrick Thiran |
Delay of intrusion detection in wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiHoc ![In: Proceedings of the 7th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, MobiHoc 2006, Florence, Italy, May 22-25, 2006, pp. 155-165, 2006, ACM, 1-59593-368-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
sensor networks, intrusion detection, delay, percolation |
18 | Xunqi Yu, James W. Modestino, Dian Fan |
Evaluation of the residual packet-loss rate using packet-level FEC for delay-constrained media network transport. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiMedia ![In: Proceedings of the 2nd International Conference on Mobile Multimedia Communications, MobiMedia 2006, Alghero, Italy, September 18-20, 2006, pp. 2, 2006, ACM, 1-59593-517-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay-constrained media, packet-level FEC, residual packet-loss rate, autoregressive model |
18 | Shao Liu, Tamer Basar, R. Srikant 0001 |
TCP-Illinois: a loss and delay-based congestion control algorithm for high-speed networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VALUETOOLS ![In: Proceedings of the 1st International Conference on Performance Evaluation Methodolgies and Tools, VALUETOOLS 2006, Pisa, Italy, October 11-13, 2006, pp. 55, 2006, ACM, 1-59593-504-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
NewReno, stability, congestion control, TCP, fairness, throughput, packet loss, AIMD, SACK, queueing delay, Reno |
18 | Feng Shi 0010, Yiorgos Makris |
Testing delay faults in asynchronous handshake circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 193-197, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
test generation, asynchronous circuits, delay faults, handshake circuits |
18 | Dianlin Du, Chongguang Wu, Xionglin Luo, Xin Zuo |
Delay Time Identification and Dynamic Characteristics Study on ANN Soft Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDA (1) ![In: Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), October 16-18, 2006, Jinan, China, pp. 42-45, 2006, IEEE Computer Society, 0-7695-2528-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
artificial neural network, dynamic system, delay time, soft sensor |
18 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Dynamic thermal clock skew compensation using tunable delay buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 162-167, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
temperature aware design methodology, tunable delay buffers, clock skew, clock tree |
18 | Adit D. Singh, Gefu Xu |
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 349-357, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Hazard-Free, Test, Delay, Transition |
18 | Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro 0001 |
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 669-674, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multiple constant multiplication, multiplierless digital filter design, delay optimization, area optimization |
18 | Joonhwan Yi, John P. Hayes |
The Coupling Model for Function and Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 631-649, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test generation, fault modeling, delay faults, functional faults |
18 | Wei Zheng 0009, Sheng Zhang 0004, Yi Ouyang 0001, Fillia Makedon, James Ford |
Node clustering based on link delay in P2P networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), Santa Fe, New Mexico, USA, March 13-17, 2005, pp. 744-749, 2005, ACM, 1-58113-964-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
link delay, node clustering, peer-to-peer, hierarchical clustering |
18 | Laura Sánchez-Miquel, Natalia Vesselinova-Vassileva, Francisco Barceló 0001, Patricia Carbajo-Flores |
Energy and delay-constrained routing in mobile ad hoc networks: an initial approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PE-WASUN ![In: Proceedings of the 2nd ACM International Workshop on Performance Evaluation of Wireless Ad Hoc, Sensor, and Ubiquitous Networks, PE-WASUN 2005, Montreal, Quebec, Canada, October 10-13, 2005, pp. 262-263, 2005, ACM, 1-59593-182-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ad hoc networks, energy efficiency, delay, routing protocols |
18 | Eduardo Parente Ribeiro, Victor C. M. Leung |
Asymmetric path delay optimization in mobile multi-homed SCTP multimedia transport. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMuNeP ![In: WMuNeP'05 - Proceedings of the First ACM Workshop on Wireless Multimedia Networking and Performance Modeling, Montreal, Quebec, Canada, October 13, 2005, pp. 70-75, 2005, ACM, 1-59593-183-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asymmetric path, multimedia, delay, mobile network, SCTP, multi-homing |
18 | Vasilis F. Pavlidis, Eby G. Friedman |
Interconnect delay minimization through interlayer via placement in 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 20-25, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RC interconnects, elmore delay, 3-D ICs |
18 | Haihua Yan, Gefu Xu, Adit D. Singh |
Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 316-320, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
delay test, defect, ATE, low voltage test |
18 | Paal Engelstad, Olav N. Østerbø |
Delay and Throughput Analysis of IEEE 802.11e EDCA with Starvation Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 15-17 November 2005, Sydney, Australia, Proceedings, pp. 647-655, 2005, IEEE Computer Society, 0-7695-2421-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Z-transform of the Delay, Virtual Collision, Performance Analysis, EDCA, Starvation, Non-Saturation, AIFS |
18 | Nick G. Duffield, Francesco Lo Presti |
Network tomography from measured end-to-end delay covariance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 12(6), pp. 978-992, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multicast, statistical inference, packet delay, topology discovery, end-to-end measurement |
18 | Ahmed M. Mahdy, Jitender S. Deogun, Shashank K. Mehta |
End-to-End Delay Heuristics for Adaptive Optical Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 12th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2004), 4-8 October 2004, Vollendam, The Netherlands, pp. 383-390, 2004, IEEE Computer Society, 0-7695-2251-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Optical Wireless Networks, Link Flexibility, NP-Hardness, Spanning Trees, Transmission Delay |
18 | Ho Fai Ko, Nicola Nicolici |
Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 454-459, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
High-level DFT, Delay-fault testing |
18 | Samuli Aalto, Urtzi Ayesta, Eeva Nyberg-Oksanen |
Two-level processor-sharing scheduling disciplines: mean delay analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2004, June 10-14, 2004, New York, NY, USA, pp. 97-105, 2004, ACM, 1-58113-873-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FB, MLPS, unfinished truncated work, scheduling, M/G/1, LAS, PS, mean delay |
18 | Robert S. Allison, James E. Zacher, David W. L. Wang, Joseph Shu |
Effects of network delay on a collaborative motor task with telehaptic and televisual feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VRCAI ![In: Proceedings VRCAI 2004, ACM SIGGRAPH International Conference on Virtual Reality Continuum and its Applications in Industry, Nanyang Technological University, Singapore, June 16-18, 2004, pp. 375-381, 2004, ACM, 1-58113-884-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
virtual environments, haptics, delay, collaborative virtual environments, teleoperation |
18 | Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham |
On-chip delay measurement for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 145-148, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design for testability, delay fault testing, silicon debug |
18 | Yarallah Koolivand, Ali Zahabi, Nasser Masoumi |
Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 149-153, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
polysilicide gate resistance, short circuit power, performance degradation, propagation delay |
18 | S.-H. Gary Chan, Fouad A. Tobagi |
Modeling and Dimensioning Hierarchical Storage Systems for Low-Delay Video Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(7), pp. 907-919, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Hierarchical storage systems, tertiary and secondary levels, staging and replacement policies, user delay goal, distributed storage systems, video services |
18 | Miron Abramovici, Charles E. Stroud |
BIST-Based Delay-Fault Testing in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(5), pp. 549-558, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Field Programmable Gate Arrays, Built-In Self-Test, delay faults |
18 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Delay budgeting in sequential circuit with application on FPGA placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 202-207, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay budgeting, FPGA, placement, sequential circuits |
18 | Koen Engelborghs, Tatyana Luzyanina, Dirk Roose |
Numerical bifurcation analysis of delay differential equations using DDE-BIFTOOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Math. Softw. ![In: ACM Trans. Math. Softw. 28(1), pp. 1-21, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
numerical stability and bifurcation analysis, Continuation, software package, delay differential equations |
18 | Chor Ping Low, Xueyan Song |
On Finding Feasible Solutions for the Delay Constrained Group Multicast Routing Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(5), pp. 581-588, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Delay constrained group multicast routing, feasible solutions, NP-completeness, heuristic algorithm |
18 | Lauren Hui Chen, Malgorzata Marek-Sadowska |
Efficient Closed-Form Crosstalk Delay Metrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 431-436, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interconnect coupling, coupling direction, delay, crosstalk |
18 | Hiroshi Saito, Alex Kondratyev, Takashi Nanya |
Design of Asynchronous Controllers with Delay Insensitive Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 93-98, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay insensitive interface, gate-level transformation, behavioral transformation, asynchronous circuits, hazards |
18 | Boris S. Mordukhovich, Ruth Trubnik |
Stability of Discrete Approximations and Necessary Optimality Conditions for Delay-Differential Inclusions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 101(1-4), pp. 149-170, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
delay-differential inclusions, finite-difference perturbations, generalized differentiation, stability, dynamic optimization, variational analysis, necessary optimality conditions |
18 | Ramesh C. Tekumalla, Premachandran R. Menon |
On Redundant Path Delay Faults in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 277-282, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
functional sensitizability, sequential circuits, testability, Path delay faults, redundant faults |
18 | Jacob Savir |
Distributed BIST Architecture to Combat Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 369-380, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
BIST, LFSR, delay test, MISR, LSSD, SRL |
18 | Andrzej Krasniewski |
Self-Testing of FPGA Delay Faults in the System Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 40-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, BIST, random testing, delay faults |
18 | Satoshi Fujita, Tadanori Nakagawa |
Lower Bounding Techniques for the Multiprocessor Scheduling Problem with Communication Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 212-220, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
inevitable communication delay, lower bound, Multiprocessor scheduling problem |
18 | Jacob Savir |
Design for Testability to Combat Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 407-411, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
BIST, LFSR, Delay Test, MISR, LSSD, SRL |
18 | Jean Michel Daga, E. Ottaviano, Daniel Auvergne |
Temperature Effect on Delay for Low Voltage Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 680-685, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
temperature effect, derating, Low power, delay, Low voltage |
18 | Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya |
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 262-273, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit |
18 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
18 | Ada Wai-Chee Fu |
Delay-Optimal Quorum Consensus for Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 8(1), pp. 59-69, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
replicated database systems, distributed systems, network topology, Mutual exclusion, wide-area networks, communication delay, coteries, quorum consensus |
18 | Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min |
Memory Efficient ATPG for Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 326-331, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Delay Testing, Automatic Test Generation, IC Testing, Path Sensitization |
18 | S. Crepaux-Motte, Mireille Jacomino, Rene David |
An algebraic method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 308-315, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method |
18 | Imtiaz P. Shaik, Michael L. Bushnell |
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 393-399, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions |
18 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
18 | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
The optimistic update theorem for path delay testing in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(3), pp. 285-290, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
test generation, Fault simulation, timing analysis, path delay faults |
17 | Haixia Wu, Wei Zhang, Wei Feng 0012, Jun Peng |
Delay-dependent stability for static recurrent neural networks via a piecewise delay approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE ICCI ![In: Proceedings of the 8th IEEE International Conference on Cognitive Informatics, ICCI 2009, June 15-17, 2009, Hong Kong, China, pp. 492-495, 2009, IEEE Computer Society, 978-1-4244-4642-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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