Search results for "flip-flops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
17	Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai	A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	public-key crypto-system, systolic array, modular-multiplication, pipeline architecture, modular-exponentiation
17	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Fine-Grain Phased Logic CPU.	ISVLSI	2003	DBLP DOI BibTeX RDF
17	Fatih Kocan	Reconfigurable randomized K-way graph partitioning.	FPGA	2003	DBLP DOI BibTeX RDF
17	Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev	STG Optimisation in the Direct Mapping of Asynchronous Circuits .	DATE	2003	DBLP DOI BibTeX RDF
17	Fatih Kocan	Reconfigurable Randomized K-way Graph Partitioning.	DSD	2003	DBLP DOI BibTeX RDF
17	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	ASYNC	2003	DBLP DOI BibTeX RDF
17	Yaron Semiat, Ran Ginosar	Timing Measurements of Synchronization Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
17	Kohei Miyase, Seiji Kajihara	Optimal Scan Tree Construction with Test Vector Modification for Test Compression.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
17	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
17	Soonhak Kwon	A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
17	Nataraj Akkiraju, Mosur Mohan	Spec Based Flip-Flop And Buffer Insertion.	ICCD	2003	DBLP DOI BibTeX RDF
17	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
17	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
17	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.	ITC	2003	DBLP DOI BibTeX RDF
17	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Delay budgeting in sequential circuit with application on FPGA placement.	DAC	2003	DBLP DOI BibTeX RDF	delay budgeting, FPGA, placement, sequential circuits
17	Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
17	Yih-Chih Chou, Youn-Long Lin	Effective enforcement of path-delay constraints inperformance-driven placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
17	Paul Amblard, Fabienne Lagnier, Michel Lévy	Using Formal Tools to Study Complex Circuits Behaviour.	DSD	2002	DBLP DOI BibTeX RDF
17	Shi-Yu Huang	Diagnosis Of Byzantine Open-Segment Faults.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
17	Chunhong Chen	Physical design with multiple on-chip voltages.	ISPD	2002	DBLP DOI BibTeX RDF
17	Pasquale Cocchini	Concurrent flip-flop and repeater insertion for high performance integrated circuits.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Ilia Polian, Piet Engelke, Bernd Becker 0001	Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.	ISMVL	2002	DBLP DOI BibTeX RDF	Voting models, Fault simulation, Bridging faults
17	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Comparative analysis of double-edge versus single-edge triggered clocked storage elements.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
17	Anzhela Yu. Matrosova, Valentina Andreeva, Yu. Sedov	Survivable Discrete Circuits Design.	IOLTW	2002	DBLP DOI BibTeX RDF
17	Ozgur Sinanoglu, Alex Orailoglu	Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.	DFT	2002	DBLP DOI BibTeX RDF
17	Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan	Optimal Sequencing Energy Allocation for CMOS Integrated Systems.	ISQED	2002	DBLP DOI BibTeX RDF	Energy Allocation, Clocked Storage Elements, Clock Distribution
17	Sandeep Kumar Goel, Bart Vermeulen	Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	ITC	2002	DBLP DOI BibTeX RDF
17	Abdel Ejnioui, N. Ranganathan	A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
17	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
17	François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer	Optimal design of synchronous circuits using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	software pipelining, retiming, Resynthesis
17	Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski	Practical Aspects of Logic Synthesis Based on Functional Decomposition.	DSD	2001	DBLP DOI BibTeX RDF
17	Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta	Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times.	ASP-DAC	2001	DBLP DOI BibTeX RDF
17	Yih-Chih Chou, Youn-Long Lin	A performance-driven standard-cell placer based on a modified force-directed algorithm.	ISPD	2001	DBLP DOI BibTeX RDF	placement, timing closure, force-directed
17	Subhasish Mitra, Edward J. McCluskey	Design of Redundant Systems Protected Against Common-Mode Failures.	VTS	2001	DBLP DOI BibTeX RDF
17	Ranganathan Sankaralingam, Nur A. Touba, Bahram Pouya	Reducing Power Dissipation during Test Using Scan Chain Disable.	VTS	2001	DBLP DOI BibTeX RDF
17	Egor S. Sogomonyan, Andrej A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh	Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.	VTS	2001	DBLP DOI BibTeX RDF
17	Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal	Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model.	VLSI Design	2001	DBLP DOI BibTeX RDF
17	Palash Sarkar 0001, Subhamoy Maitra	Efficient Implementation of "Large" Stream Cipher Systems.	CHES	2001	DBLP DOI BibTeX RDF	Boolean functions, Stream Ciphers, Cellular Automata, Linear Feedback Shift Registers, Reconfigurable Hardware, Pipelined Architecture
17	Uming Ko, Poras T. Balsara	High-performance energy-efficient D-flip-flop circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar	Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell	Improving path delay testability of sequential circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	Testing and testable designs for one-time programmable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
17	Claude Arm, Jean-Marc Masgonty, Christian Piguet	Double-Latch Clocking Scheme for Low-Power I.P. Cores.	PATMOS	2000	DBLP DOI BibTeX RDF
17	Elias Ahmed, Jonathan Rose	The effect of LUT and cluster size on deep-submicron FPGA performance and density.	FPGA	2000	DBLP DOI BibTeX RDF
17	Abdel Ejnioui, N. Ranganathan	Design Partitioning on Single-Chip Emulation Systems.	VLSI Design	2000	DBLP DOI BibTeX RDF	FPGA partitioning, integer programming, FPGA architecture, schedule optimization
17	David L. Harris, Mark Horowitz, Dean Liu	Timing analysis including clock skew.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Yuejian Wu, Saman Adham	Scan-based BIST fault diagnosis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Jason Cong, Chang Wu	Optimal FPGA mapping and retiming with efficient initial state computation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Srimat T. Chakradhar, Sujit Dey	Resynthesis and retiming for optimum partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Vikram Iyengar, Krishnendu Chakrabarty, Brian T. Murray	Deterministic Built-in Pattern Generation for Sequential Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	Comma coding, pattern decoding, statistical encoding, BIST, Huffman coding, run-length encoding, embedded-core testing, sequential circuit testing
17	Egor S. Sogomonyan, Adit D. Singh, Michael Gössel	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	design-for-testability, BIST, scan design
17	Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao	Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries
17	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms.	DATE	1999	DBLP DOI BibTeX RDF
17	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
17	Jerzy W. Greblicki, Stanislaw J. Piestrak	Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits.	EDCC	1999	DBLP DOI BibTeX RDF
17	Ondrej Novák	Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata.	EDCC	1999	DBLP DOI BibTeX RDF	linear cyclic codes, hardware test pattern generators, weighted random testing, Cellular automata, BIST, linear feedback shift registers, pseudoexhaustive testing
17	Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar	Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.	VTS	1999	DBLP DOI BibTeX RDF
17	Albrecht P. Stroele, Steffen Tarnick	Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code.	VTS	1999	DBLP DOI BibTeX RDF
17	Robert C. Aitken	Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.	VTS	1999	DBLP DOI BibTeX RDF
17	Nithya Raghavan, Venkatesh Akella, Smita Bakshi	Automatic Insertion of Gated Clocks at Register Transfer Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
17	Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa	Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis.	VLSI Design	1999	DBLP DOI BibTeX RDF
17	Wei-Kang Huang, Fred J. Meyer, Xiao-Tao Chen, Fabrizio Lombardi	Testing configurable LUT-based FPGA's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
17	Naresh Maheshwari, Sachin S. Sapatnekar	Efficient retiming of large circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
17	Dave Johnson 0003, Venkatesh Akella, Bret Stott	Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
17	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
17	Peichen Pan, Arvind K. Karandikar, C. L. Liu 0001	Optimal clock period clustering for sequential circuits with retiming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
17	Sujit Dey, Vijay Gangaram, Miodrag Potkonjak	A controller redesign technique to enhance testability of controller-data path circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
17	Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee	Test-point insertion: scan paths through functional logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
17	Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel	Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
17	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
17	Peichen Pan, C. L. Liu 0001	Optimal clock period FPGA technology mapping for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, retiming, technology mapping, look-up tables, logic replication, clock period, sequential synthesis
17	Vaughn Betz, Jonathan Rose	How Much Logic Should Go in an FPGA Logic Block?	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
17	Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee	Functional Scan Chain Testing.	DATE	1998	DBLP DOI BibTeX RDF	functional scan chain, alternating sequence, scan chain testing, design for testability, test point insertion
17	Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth	Synthesis of Sequential Circuits with Clock Control to Improve Testability.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
17	Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch	A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs.	FPL	1998	DBLP DOI BibTeX RDF
17	Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa	Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis.	EUROMICRO	1998	DBLP DOI BibTeX RDF
17	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicit state enumeration.	ITC	1998	DBLP DOI BibTeX RDF
17	Joep Aerts, Erik Jan Marinissen	Scan chain design for test time reduction in core-based ICs.	ITC	1998	DBLP DOI BibTeX RDF
17	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	MIX: A Test Generation System for Synchronous Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits
17	Sujit Dey, Miodrag Potkonjak	Nonscan design-for-testability techniques using RT-level design information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Peter A. Walker, Sumit Ghosh	On the nature and inadequacies of transport timing delay constructs in VHDL descriptions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III	Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
17	Yoshinobu Higami, Kozo Kinoshita	Design of partially parallel scan chain.	ED&TC	1997	DBLP DOI BibTeX RDF
17	Andre Hertwig, Hans-Joachim Wunderlich	Fast controllers for data dominated applications.	ED&TC	1997	DBLP DOI BibTeX RDF
17	Prasoon Surti, Liang-Fang Chao, Akhilesh Tyagi	Low power FSM design using Huffman-style encoding.	ED&TC	1997	DBLP DOI BibTeX RDF
17	Irith Pomeranz, Sudhakar M. Reddy	Built-in test generation for synchronous sequential circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	comparison units, built-in self-test, synchronous sequential circuits, at-speed test
17	Naresh Maheshwari, Sachin S. Sapatnekar	Minimum area retiming with equivalent initial states.	ICCAD	1997	DBLP DOI BibTeX RDF	VLSI, Sequential Circuits, Retiming, Design Automation, Timing Optimization, Area Optimization
17	Itsuo Takanami, Tadayoshi Horita	Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.	DFT	1997	DBLP DOI BibTeX RDF	self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
17	Huy Nguyen 0001, Abhijit Chatterjee, Rabindra K. Roy	Impact of Partial Reset on Fault Independent Testing and BIST.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel	Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	Madhavi Vootukuru, Ranga Vemuri, Nand Kumar	Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Valid clock frequencies and their computation in wavepipelined circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
17	Kanji Hirabayashi	Hazard simulation of sequential circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	hazard checking, seven-valued logic, logic simulation
17	Xinghao Chen 0003, Michael L. Bushnell	Sequential circuit test generation using dynamic justification equivalence.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	search decision spaces, test generation efficiency, automatic test pattern generation, stuck-at faults, justification
17	Kwang-Ting Cheng, A. S. Krishnakumar	Automatic generation of functional vectors using the extended finite state machine model.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	functional testing, automatic test generation, design verification, extended finite state machines
17	Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Circular Self-Test Path for FSMs.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
17	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	On Verifying the Correctness of Retimed Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	3-valued equivalence, delay-compensation, sequential ATPG, formal verification, retiming, equivalence-Checking
17	Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal	Improving Circuit Testability by Clock Control.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
17	C. P. Ravikumar, Rajamani Rajarajan	Genetic Algorithms for Scan Path Design.	VLSI Design	1996	DBLP DOI BibTeX RDF