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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3674 occurrences of 1433 keywords
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Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas |
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Brian R. Wilkins, B. S. Suparjo |
A structure for interconnect testing on mixed-signal boards. |
J. Electron. Test. |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Håkon Ording Bugge |
An evaluation of Intel's core i7 architecture using a comparative approach. |
Comput. Sci. Res. Dev. |
2009 |
DBLP DOI BibTeX RDF |
SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks |
17 | Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer |
Power-delay optimization in VLSI microprocessors by wire spacing. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Wire spacing, power optimization, interconnect optimization, delay-optimization |
17 | Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli |
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. |
NanoNet |
2009 |
DBLP DOI BibTeX RDF |
timing optimization, on-chip interconnect, repeater insertion, 3-D ICs |
17 | Hongbo Zhang 0001, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng |
Wire shaping is practical. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
manufacturing for design, wire tapering, interconnect, opc, power minimization |
17 | Sudeep Pasricha |
Exploring serial vertical interconnects for 3D ICs. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
serial interconnect, VLSI, networks on chip, 3D ICs |
17 | Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle |
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
Network Co-processor, SoC Interconnect, Run-Time Reconfiguration |
17 | Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal |
Metal filling impact on standard cells: definition of the metal fill corner concept. |
SBCCI |
2008 |
DBLP DOI BibTeX RDF |
metal filling, modelization, interconnect, design of experiment, dispersion, standard cells, capacitance, corners, ring oscillators |
17 | Michel N. Victor, Aris K. Silzars, Edward S. Davidson |
A freespace crossbar for multi-core processors. |
ICS |
2008 |
DBLP DOI BibTeX RDF |
freespace crossbar, interconnect |
17 | Jingye Xu, Pervez Khaled, Masud H. Chowdhury |
Fast bus waveform estimation at the presence of coupling noise. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
coupling noise, global interconnect |
17 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
Full Open Defects in Nanometric CMOS. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
interconnect open, gate leakage current, CMOS |
17 | Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller |
Multicore design is the challenge! what is the solution? |
DAC |
2008 |
DBLP DOI BibTeX RDF |
heterogeneous/homogenous multicore, symmetric/asymmetric multicore, multiprocessors, interconnect, multi-core, MPSoC, programming model, virtual prototyping, ESL, virtual platforms |
17 | Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood |
3D Integration for Introspection. |
IEEE Micro |
2007 |
DBLP DOI BibTeX RDF |
3D interconnect, 3D stacking, performance evaluation, testing, debugging, profiling |
17 | Yi Zou, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Sheldon X.-D. Tan, Le Kang |
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
stochastic parameterized model order reduction, Hermite polynomial chaos, stochastic model order reduction algorithm, stochastic Hermite polynomials, stochastic interconnect analysis, nonGaussian input variations, implicit system representation, block matrix structure, Monte Carlo methods, linear equations |
17 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David |
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip |
17 | Daniel Jiménez-González, Xavier Martorell, Alex Ramírez |
Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed |
17 | J. V. R. Ravindra, Srinivas Bala Mandalika |
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
RC, distributed RLC, interconnect, SPICE, circuit, RL |
17 | Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos |
A buffered crossbar-based chip interconnection framework supporting quality of service. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar |
17 | Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin |
Architectural implications of brick and mortar silicon manufacturing. |
ISCA |
2007 |
DBLP DOI BibTeX RDF |
chip assembly, design re-use, interconnect design |
17 | Xiangyuan Liu, Shuming Chen |
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
low-swing interconnect, delay, power, estimation model |
17 | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001 |
Steiner network construction for timing critical nets. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
Steiner network, routing, redundancy, interconnect |
17 | Dian Zhou, Ruiming Li |
Design and Verification of High-Speed VLSI Physical Design. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
floorplanning and placement, order reduction, parameter extraction, VLSI, delay, interconnect, power, physical design, buffer insertion, power grid, clock distribution, wire sizing |
17 | Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng |
Integrated algorithmic logical and physical design of integer multiplier. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
booth, interconnect, partial product, TDM |
17 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
interconnect sharing, time division, wave-pipelining |
17 | Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin |
Exploring technology alternatives for nano-scale FPGA interconnects. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, nanotechnology, nanoelectronics |
17 | N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill |
BEOL variability and impact on RC extraction. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
interconnect, process variation, extraction |
17 | Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak |
Flexible ASIC: shared masking for multiple media processors. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
optimization, interconnect, ASIC |
17 | Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar |
Net weighting to reduce repeater counts during placement. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
interconnect, placement, scaling, buffering, repeater, force-directed placement, net weighting |
17 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Distributed Diagnosis of Interconnections in SoC and MCM Designs. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
interconnect test and diagnosis, performance fault diagnosis, design for testability for SOCs and MCMs, MISR reconfiguration |
17 | Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano |
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
Network-on-a-Chip, table-lookup routing, interconnection networks, Systems-on-a-Chip, streaming processing, on-chip interconnect, deterministic routing |
17 | Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson |
Mitigating static power in current-sensed interconnects. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
interconnect circuits, static power, self-timed systems |
17 | Kyu-won Choi, Abhijit Chatterjee |
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
device and interconnect co-optimization, nanometer design, time slack distribution, low-power design |
17 | Nadine Gergel, Shana Craft, John C. Lach |
Modeling QCA for area minimization in logic synthesis. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
CAD, interconnect, logic synthesis, nanotechnology, QCA |
17 | Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy 0001 |
An adaptive window-based susceptance extraction and its efficient implementation. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
interconnect, inductance, susceptance |
17 | Zhenhai Zhu, Ben Song, Jacob White 0001 |
Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
fast integral equation solver, impedance extraction, interconnect, iterative methods, preconditioning |
17 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
floorplanning, routability, interconnect estimation |
17 | Aneesh Aggarwal, Manoj Franklin |
Hierarchical Interconnects for On-Chip Clustering. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
on-chip clustering, instruction distribution algo-rithms, Scalability, on-chip interconnect, Instruction-level parallelism (ILP) |
17 | Falah R. Awwad, Mohamed Nekili |
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
parallel regeneration, VLSI, repeater, RLC interconnect |
17 | Jun Chen 0008, Lei He 0001 |
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
interconnect design |
17 | Terry Tao Ye, Giovanni De Micheli, Luca Benini |
Analysis of power consumption on switch fabrics in network routers. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
interconnect networks, systems on chip, networks on chip, power consumption |
17 | Hemant Mahawar, Vivek Sarin, Weiping Shi |
A solenoidal basis method for efficient inductance extraction. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
inductance extraction, solenoidal basis, interconnect, iterative methods, preconditioning |
17 | Chris C. N. Chu, D. F. Wong 0001 |
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing |
17 | Xiaoliang Bai, Sujit Dey |
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
System-on-Chip, Crosstalk, Interconnect test, Defect simulation, High level |
17 | Kristian Sandström, Christer Norström, Magnus Ahlmark |
Frame packing in real-time communication. |
RTCSA |
2000 |
DBLP DOI BibTeX RDF |
frame packing, common computational model, signal exchange, physical device, signal size, deadline requirement, broadcast bus, variable sized frames, resource perspective, periodic frames, network bandwidth requirement, simple heuristics, signal sets, CAN based system, Local Interconnect Network, cost sensitive embedded systems, car control systems, real-time systems, computational complexity, distributed processing, NP-hard, communication networks, bandwidth allocation, real time communication, microcontrollers, microcontrollers, controller area networks, distributed embedded systems, objective function, automobiles, automotive applications, production cost |
17 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
17 | Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi |
Structural diagnosis of interconnects by coloring. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
interconnect, diagnosis, graph coloring, syndrome, balanced code |
17 | Eric Kusse, Jan M. Rabaey |
Low-energy embedded FPGA structures. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
dual voltage, pass-transistors, FPGAs, interconnect network, embedded, power, low energy, low swing |
17 | Madhavan Swaminathan, Bruce C. Kim, Abhijit Chatterjee |
A Survey of Test Techniques for MCM Substrates. |
J. Electron. Test. |
1997 |
DBLP DOI BibTeX RDF |
multi-chip module, MCM substrates, known-good-die, interconnect test |
17 | Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes |
Datapath Design for a VLIW Video Signal Processor. |
HPCA |
1997 |
DBLP DOI BibTeX RDF |
datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design |
17 | Salil Raje, Reinaldo A. Bergamaschi |
Generalized resource sharing. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
clique-partitioning-based algorithms, generalized resource sharing, global clique partitioning based framework, interconnect cost estimation, merging cost estimation, sharing possibilities, high level synthesis, high-level synthesis, functional unit, functional units |
17 | Craig S. Steele, Jeffrey T. Draper, Jeff Koller, C. LaCour |
A Bus-Efficient Low-Latency Network Interface for the PDSS Multicomputer. |
HPDC |
1997 |
DBLP DOI BibTeX RDF |
bus-efficient low-latency network interface, PDSS multicomputer, unprivileged code, cache-to-cache communications, distributed barrier-synchronization mechanism, single-chip implementation, commodity processor, routing, multiprocessor interconnection networks, interconnect, cache coherence protocols |
17 | Roland W. Freund, Peter Feldmann |
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
passive networks, Pade approximations, Lanczos algorithm, symmetric formulation, interconnect, network synthesis, reduced-order modeling |
17 | Xiao-Tao Chen, Fabrizio Lombardi |
A coloring approach to the structural diagnosis of interconnects. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
interconnect, Diagnosis, graph coloring, syndrome |
17 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
17 | Daksh Lehther, Sachin S. Sapatnekar |
Clock tree synthesis for multi-chip modules. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Pade' approximants, Interconnect optimization |
17 | Haluk Konuk, F. Joel Ferguson |
An unexpected factor in testing for CMOS opens: the die surface. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model |
17 | Lizy Kurian John |
VaWiRAM: a variable width random access memory module. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
17 | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
Representation and Synthesis of Interface of a Circuit for its Reuse. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
17 | Jason Cong, Lei He 0001 |
Optimal wiresizing for interconnects with multiple sources. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
performance driven layout, optimal wiresizing, interconnect optimization, VLSI routing |
17 | Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan |
PEPPER - a timing driven early floorplanner. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay |
17 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Efficient retiming under a general delay model. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays |
17 | S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy |
Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects |
16 | Xue Feng, Shengling Geng, Banghe Han |
The Ordinal Consistency of a Hesitant Fuzzy Preference Relation. |
J. Interconnect. Networks |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Xiao Xu, Zhuoma Gao, Lei Meng, Qinghe Tong |
Tight Toughness, Isolated Toughness and Binding Number Bounds for the [1,n]-Factors and the {K2,Ci≥4}-Factors. |
J. Interconnect. Networks |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Zhao Wang, Hongfang Liu, Yuhu Liu |
Nordhaus-Gaddum-Type Results for the k-Independent Number of Graphs. |
J. Interconnect. Networks |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Sheena Mohammed, Rangu Sridevi |
To Secure the Cloud Application Using a Novel Efficient Deep Learning-Based Forensic Framework. |
J. Interconnect. Networks |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Zhiwei Guo |
Nordhaus-Gaddum-Type Results for the Strong Equitable Vertex k-Arboricity of Graphs. |
J. Interconnect. Networks |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Yingbin Ma, Hui Zhang |
The k-Total-Proper Index of Graphs. |
J. Interconnect. Networks |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Ramya Thirunavukkarasu, Ramachandran Balasubramanian |
An Enhanced Probabilistic-Shaped SCMA NOMA for Wireless Networks. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hengzhe Li, Jiajia Wang, Rong-Xia Hao |
The λ4-Connectivity of the Cartesian Product of Trees. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Mallanagouda Biradar, Basavaraj Mathapathi |
Security and Energy Aware Clustering-Based Routing in Wireless Sensor Network: Hybrid Nature-Inspired Algorithm for Optimal Cluster Head Selection. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Maravarman Manoharan, S. Babu, R. Pitchai |
Wireless Sensor Network Security Analysis for Data and Aggregation. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Merlin Thomas Ellumkalayil, Libin Chacko Samuel, Sudev Naduvath |
Some New Results on δ(k)-Coloring of Graphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Saber Gholami, Hovhannes A. Harutyunyan, Edward Maraachlian |
Optimal Broadcasting in Fully Connected Trees. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Huixian Xu, Jinqiu Zhou |
A Note on Connectivity of Regular Graphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | J. J. Sumesh, C. P. Maheswaran |
Energy Efficient Secure-Trust-Based Ring Cluster Routing in Wireless Sensor Network. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Johan Kok, Sudev Naduvath, Vivian Mukungunugwa |
A Study on Ornated Graphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xueli Sun, Jianxi Fan, Baolei Cheng, Yan Wang 0078, Jingya Zhou |
Reliability of Augmented 3-Ary n-Cubes with Extra Faults. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Lulu Yang, Xiaohui Hua |
Hyper Star Fault Tolerance of Hierarchical Star Networks. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yingbin Ma, Wenhan Zhu |
The 3-Vertex-Rainbow Index of 2-(Edge) Connected Graphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Gunaganti Sravanthi, Nageswara Rao Moparthi |
An Efficient and Multi-Tier Node Deployment Strategy Using Variable Tangent Search in an IOT-Fog Environment. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yiling Dong |
Precise Values for the Strong Subgraph 3-Arc-Connectivity of Cartesian Products of Some Digraph Classes. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Driss Ait Omar, Hamid Garmani, Mohamed El Amrani, Es-Said Azougaghe, Mohamed Baslam, Mostafa Jourhmane |
Towards Intelligent Control of Beaconing Power and Beaconing Rate in Vehicular Ad Hoc Networks. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Wenjun Liu |
Reliability of DQcube Networks Under the Condition of r-Component. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Junran Yu |
Directed Tree Connectivity of Symmetric Digraphs and Complete Bipartite Digraphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yingbin Ma, Yanfeng Xue, Xiaoxue Zhang |
Proper (Strong) Rainbow Connection and Proper (Strong) Rainbow Vertex Connection of Some Special Graphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Kavita K. Patil, T. Senthil Kumaran, A. Y. Prasad |
Improved Congestion Control in Wireless Sensor Networks Using Clustering with Metaheuristic Approach. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shreedhar Yadawad, S. M. Joshi |
Energy-Efficient Data Aggregation and Cluster-Based Routing in Wireless Sensor Networks Using Tasmanian Fully Recurrent Deep Learning Network with Pelican Variable Marine Predators Algorithm. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Sanjay Sudhir Kulkarni, Arjav A. Bavarva |
Crow Sun Flower Optimization-Based Handover Modules in 5G Networks. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Gang Yang, Changxiang He |
Distance-Edge-Monitoring Sets in Hierarchical and Corona Graphs. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Zhengqin Yu, Shuming Zhou, Hong Zhang, Xiaoqing Liu |
Distance Optimally Edge Connectedness of Arrangement Graph Based on Subgraph Fault Pattern. |
J. Interconnect. Networks |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shuai Ren |
Computer Vision for Facial Analysis Using Human-Computer Interaction Models. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Xufei Liu, Jinting Liu, Youlong Gong |
Low Delay Transmission Model of Internet of Things Based on Data Spectrum. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Guiyun Liu, Adhiyaman Manickam |
The Capture and Evaluation System of Student Actions in Physical Education Classroom Based on Deep Learning. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Shuzhe Guo, Xiaolei Zhu, Yang Liu, Jianwei Han |
Personalized Recommendation Method of Entrepreneurial Service Information Based on Blockchain. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Li Liu, Rama Subbareddy, C. G. Raghavendra |
AI Intelligence Chatbot to Improve Students Learning in the Higher Education Platform. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
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16 | Dongqin Cheng |
Hamiltonian Cycles Passing Through Prescribed Edges in Locally Twisted Cubes. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
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16 | Mingyong He |
Predictive Group Learning Behavior Approach and Inquiry Learning For Higher Education. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
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16 | Shuo Li, Jianjun Li, Priyan Malarvizhi Kumar, Ashish Kr. Luhach |
Fish Swarm Optimized Deep Hopfield Neural Network-Assisted HCI System for Augmentative Communication Using a Visual Feedback System. |
J. Interconnect. Networks |
2022 |
DBLP DOI BibTeX RDF |
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