|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3674 occurrences of 1433 keywords
|
|
|
Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas |
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7), pp. 988-996, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Brian R. Wilkins, B. S. Suparjo |
A structure for interconnect testing on mixed-signal boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(4), pp. 369-374, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Håkon Ording Bugge |
An evaluation of Intel's core i7 architecture using a comparative approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Sci. Res. Dev. ![In: Comput. Sci. Res. Dev. 23(3-4), pp. 203-209, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SPEC MPI2007, Nehalem, iCore7, Harpertown, Quad-Core, QuickPath Interconnect, Moore’s Law, Benchmarking, Stream, Micro-benchmarks |
17 | Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer |
Power-delay optimization in VLSI microprocessors by wire spacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 55:1-55:28, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Wire spacing, power optimization, interconnect optimization, delay-optimization |
17 | Hu Xu 0002, Vasilis F. Pavlidis, Giovanni De Micheli |
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 141-150, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
timing optimization, on-chip interconnect, repeater insertion, 3-D ICs |
17 | Hongbo Zhang 0001, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng |
Wire shaping is practical. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 131-138, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
manufacturing for design, wire tapering, interconnect, opc, power minimization |
17 | Sudeep Pasricha |
Exploring serial vertical interconnects for 3D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 581-586, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
serial interconnect, VLSI, networks on chip, 3D ICs |
17 | Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle |
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 200-205, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Network Co-processor, SoC Interconnect, Run-Time Reconfiguration |
17 | Laurent Remy, Philippe Coll, Fabrice Picot, Philippe Mico, Jean-Michel Portal |
Metal filling impact on standard cells: definition of the metal fill corner concept. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 16-21, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
metal filling, modelization, interconnect, design of experiment, dispersion, standard cells, capacitance, corners, ring oscillators |
17 | Michel N. Victor, Aris K. Silzars, Edward S. Davidson |
A freespace crossbar for multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 56-62, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
freespace crossbar, interconnect |
17 | Jingye Xu, Pervez Khaled, Masud H. Chowdhury |
Fast bus waveform estimation at the presence of coupling noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 339-342, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
coupling noise, global interconnect |
17 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
Full Open Defects in Nanometric CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 119-124, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect open, gate leakage current, CMOS |
17 | Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne H. Wolf, Achim Nohl, Drew Wingard, Mike Muller |
Multicore design is the challenge! what is the solution? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 128-130, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
heterogeneous/homogenous multicore, symmetric/asymmetric multicore, multiprocessors, interconnect, multi-core, MPSoC, programming model, virtual prototyping, ESL, virtual platforms |
17 | Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood |
3D Integration for Introspection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(1), pp. 77-83, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
3D interconnect, 3D stacking, performance evaluation, testing, debugging, profiling |
17 | Yi Zou, Yici Cai, Qiang Zhou 0001, Xianlong Hong, Sheldon X.-D. Tan, Le Kang |
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 367-372, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
stochastic parameterized model order reduction, Hermite polynomial chaos, stochastic model order reduction algorithm, stochastic Hermite polynomials, stochastic interconnect analysis, nonGaussian input variations, implicit system representation, block matrix structure, Monte Carlo methods, linear equations |
17 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David |
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 94-104, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip |
17 | Daniel Jiménez-González, Xavier Martorell, Alex Ramírez |
Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 210-219, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed |
17 | J. V. R. Ravindra, Srinivas Bala Mandalika |
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 207-211, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RC, distributed RLC, interconnect, SPICE, circuit, RL |
17 | Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos |
A buffered crossbar-based chip interconnection framework supporting quality of service. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 90-95, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar |
17 | Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, Todd M. Austin |
Architectural implications of brick and mortar silicon manufacturing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 244-253, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip assembly, design re-use, interconnect design |
17 | Xiangyuan Liu, Shuming Chen |
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 91-94, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-swing interconnect, delay, power, estimation model |
17 | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001 |
Steiner network construction for timing critical nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 379-384, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Steiner network, routing, redundancy, interconnect |
17 | Dian Zhou, Ruiming Li |
Design and Verification of High-Speed VLSI Physical Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 20(2), pp. 147-165, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
floorplanning and placement, order reduction, parameter extraction, VLSI, delay, interconnect, power, physical design, buffer insertion, power grid, clock distribution, wire sizing |
17 | Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng |
Integrated algorithmic logical and physical design of integer multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1014-1017, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
booth, interconnect, partial product, TDM |
17 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 446-451, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect sharing, time division, wave-pipelining |
17 | Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin |
Exploring technology alternatives for nano-scale FPGA interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 921-926, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, nanotechnology, nanoelectronics |
17 | N. S. Nagaraj, Tom Bonifield, Abha Singh, Clive Bittlestone, Usha Narasimha, Viet Le, Anthony M. Hill |
BEOL variability and impact on RC extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 758-759, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect, process variation, extraction |
17 | Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak |
Flexible ASIC: shared masking for multiple media processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 909-914, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
optimization, interconnect, ASIC |
17 | Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar |
Net weighting to reduce repeater counts during placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 503-508, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect, placement, scaling, buffering, repeater, force-directed placement, net weighting |
17 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Distributed Diagnosis of Interconnections in SoC and MCM Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 291-307, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect test and diagnosis, performance fault diagnosis, design for testability for SOCs and MCMs, MISR reconfiguration |
17 | Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano |
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Network-on-a-Chip, table-lookup routing, interconnection networks, Systems-on-a-Chip, streaming processing, on-chip interconnect, deterministic routing |
17 | Vishak Venkatraman, Atul Maheshwari, Wayne P. Burleson |
Mitigating static power in current-sensed interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 224-229, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect circuits, static power, self-timed systems |
17 | Kyu-won Choi, Abhijit Chatterjee |
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 72-77, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
device and interconnect co-optimization, nanometer design, time slack distribution, low-power design |
17 | Nadine Gergel, Shana Craft, John C. Lach |
Modeling QCA for area minimization in logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 60-63, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CAD, interconnect, logic synthesis, nanotechnology, QCA |
17 | Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy 0001 |
An adaptive window-based susceptance extraction and its efficient implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 728-731, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnect, inductance, susceptance |
17 | Zhenhai Zhu, Ben Song, Jacob White 0001 |
Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 712-717, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fast integral equation solver, impedance extraction, interconnect, iterative methods, preconditioning |
17 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 56-61, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
floorplanning, routability, interconnect estimation |
17 | Aneesh Aggarwal, Manoj Franklin |
Hierarchical Interconnects for On-Chip Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
on-chip clustering, instruction distribution algo-rithms, Scalability, on-chip interconnect, Instruction-level parallelism (ILP) |
17 | Falah R. Awwad, Mohamed Nekili |
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 118-123, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
parallel regeneration, VLSI, repeater, RLC interconnect |
17 | Jun Chen 0008, Lei He 0001 |
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 92-97, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interconnect design |
17 | Terry Tao Ye, Giovanni De Micheli, Luca Benini |
Analysis of power consumption on switch fabrics in network routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 524-529, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interconnect networks, systems on chip, networks on chip, power consumption |
17 | Hemant Mahawar, Vivek Sarin, Weiping Shi |
A solenoidal basis method for efficient inductance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 751-756, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
inductance extraction, solenoidal basis, interconnect, iterative methods, preconditioning |
17 | Chris C. N. Chu, D. F. Wong 0001 |
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(3), pp. 343-371, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing |
17 | Xiaoliang Bai, Sujit Dey |
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 169-177, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
System-on-Chip, Crosstalk, Interconnect test, Defect simulation, High level |
17 | Kristian Sandström, Christer Norström, Magnus Ahlmark |
Frame packing in real-time communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 399-403, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
frame packing, common computational model, signal exchange, physical device, signal size, deadline requirement, broadcast bus, variable sized frames, resource perspective, periodic frames, network bandwidth requirement, simple heuristics, signal sets, CAN based system, Local Interconnect Network, cost sensitive embedded systems, car control systems, real-time systems, computational complexity, distributed processing, NP-hard, communication networks, bandwidth allocation, real time communication, microcontrollers, microcontrollers, controller area networks, distributed embedded systems, objective function, automobiles, automotive applications, production cost |
17 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 49-54, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
17 | Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi |
Structural diagnosis of interconnects by coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(2), pp. 249-271, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
interconnect, diagnosis, graph coloring, syndrome, balanced code |
17 | Eric Kusse, Jan M. Rabaey |
Low-energy embedded FPGA structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 155-160, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
dual voltage, pass-transistors, FPGAs, interconnect network, embedded, power, low energy, low swing |
17 | Madhavan Swaminathan, Bruce C. Kim, Abhijit Chatterjee |
A Survey of Test Techniques for MCM Substrates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(1-2), pp. 27-38, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multi-chip module, MCM substrates, known-good-die, interconnect test |
17 | Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes |
Datapath Design for a VLIW Video Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 24-35, 1997, IEEE Computer Society, 0-8186-7764-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design |
17 | Salil Raje, Reinaldo A. Bergamaschi |
Generalized resource sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 326-332, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clique-partitioning-based algorithms, generalized resource sharing, global clique partitioning based framework, interconnect cost estimation, merging cost estimation, sharing possibilities, high level synthesis, high-level synthesis, functional unit, functional units |
17 | Craig S. Steele, Jeffrey T. Draper, Jeff Koller, C. LaCour |
A Bus-Efficient Low-Latency Network Interface for the PDSS Multicomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 6th International Symposium on High Performance Distributed Computing, HPDC '97, Portland, OR, USA, August 5-8, 1997., pp. 213-222, 1997, IEEE Computer Society, 0-8186-8117-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
bus-efficient low-latency network interface, PDSS multicomputer, unprivileged code, cache-to-cache communications, distributed barrier-synchronization mechanism, single-chip implementation, commodity processor, routing, multiprocessor interconnection networks, interconnect, cache coherence protocols |
17 | Roland W. Freund, Peter Feldmann |
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 280-287, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
passive networks, Pade approximations, Lanczos algorithm, symmetric formulation, interconnect, network synthesis, reduced-order modeling |
17 | Xiao-Tao Chen, Fabrizio Lombardi |
A coloring approach to the structural diagnosis of interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 676-680, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
interconnect, Diagnosis, graph coloring, syndrome |
17 | Kanad Chakraborty, Pinaki Mazumder |
An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 685-688, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
bus-layout, bussed driver shorts, early diagnosis, field survivability, interconnect shorts, production yield, printed circuit boards, printed circuit testing |
17 | Daksh Lehther, Sachin S. Sapatnekar |
Clock tree synthesis for multi-chip modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 50-53, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Pade' approximants, Interconnect optimization |
17 | Haluk Konuk, F. Joel Ferguson |
An unexpected factor in testing for CMOS opens: the die surface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 422-429, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model |
17 | Lizy Kurian John |
VaWiRAM: a variable width random access memory module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 219-224, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
17 | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
Representation and Synthesis of Interface of a Circuit for its Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 140-145, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
17 | Jason Cong, Lei He 0001 |
Optimal wiresizing for interconnects with multiple sources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 568-574, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
performance driven layout, optimal wiresizing, interconnect optimization, VLSI routing |
17 | Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan |
PEPPER - a timing driven early floorplanner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 230-235, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay |
17 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Efficient retiming under a general delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 368-382, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays |
17 | S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy |
Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 260-263, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects |
16 | Xue Feng, Shengling Geng, Banghe Han |
The Ordinal Consistency of a Hesitant Fuzzy Preference Relation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 24(1), pp. 2350009:1-2350009:17, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Xiao Xu, Zhuoma Gao, Lei Meng, Qinghe Tong |
Tight Toughness, Isolated Toughness and Binding Number Bounds for the [1,n]-Factors and the {K2,Ci≥4}-Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 24(1), pp. 2350010:1-2350010:12, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Zhao Wang, Hongfang Liu, Yuhu Liu |
Nordhaus-Gaddum-Type Results for the k-Independent Number of Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 24(1), pp. 2350007:1-2350007:9, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Sheena Mohammed, Rangu Sridevi |
To Secure the Cloud Application Using a Novel Efficient Deep Learning-Based Forensic Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 24(1), pp. 2350008:1-2350008:26, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Zhiwei Guo |
Nordhaus-Gaddum-Type Results for the Strong Equitable Vertex k-Arboricity of Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 24(1), pp. 2350006:1-2350006:13, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Yingbin Ma, Hui Zhang |
The k-Total-Proper Index of Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 24(1), pp. 2350011:1-2350011:17, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Ramya Thirunavukkarasu, Ramachandran Balasubramanian |
An Enhanced Probabilistic-Shaped SCMA NOMA for Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(4), pp. 2350003:1-2350003:13, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hengzhe Li, Jiajia Wang, Rong-Xia Hao |
The λ4-Connectivity of the Cartesian Product of Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(3), pp. 2250007:1-2250007:22, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Mallanagouda Biradar, Basavaraj Mathapathi |
Security and Energy Aware Clustering-Based Routing in Wireless Sensor Network: Hybrid Nature-Inspired Algorithm for Optimal Cluster Head Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150039:1-2150039:24, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Maravarman Manoharan, S. Babu, R. Pitchai |
Wireless Sensor Network Security Analysis for Data and Aggregation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(2), pp. 2250002:1-2250002:28, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Merlin Thomas Ellumkalayil, Libin Chacko Samuel, Sudev Naduvath |
Some New Results on δ(k)-Coloring of Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(3), pp. 2250010:1-2250010:15, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Saber Gholami, Hovhannes A. Harutyunyan, Edward Maraachlian |
Optimal Broadcasting in Fully Connected Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150037:1-2150037:20, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Huixian Xu, Jinqiu Zhou |
A Note on Connectivity of Regular Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(4), pp. 2350002:1-2350002:6, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | J. J. Sumesh, C. P. Maheswaran |
Energy Efficient Secure-Trust-Based Ring Cluster Routing in Wireless Sensor Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(2), pp. 2250004:1-2250004:26, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Johan Kok, Sudev Naduvath, Vivian Mukungunugwa |
A Study on Ornated Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150035:1-2150035:14, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Xueli Sun, Jianxi Fan, Baolei Cheng, Yan Wang 0078, Jingya Zhou |
Reliability of Augmented 3-Ary n-Cubes with Extra Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(2), pp. 2150040:1-2150040:20, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Lulu Yang, Xiaohui Hua |
Hyper Star Fault Tolerance of Hierarchical Star Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(4), pp. 2350001:1-2350001:11, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yingbin Ma, Wenhan Zhu |
The 3-Vertex-Rainbow Index of 2-(Edge) Connected Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150034:1-2150034:15, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Gunaganti Sravanthi, Nageswara Rao Moparthi |
An Efficient and Multi-Tier Node Deployment Strategy Using Variable Tangent Search in an IOT-Fog Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(4), pp. 2350004:1-2350004:29, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yiling Dong |
Precise Values for the Strong Subgraph 3-Arc-Connectivity of Cartesian Products of Some Digraph Classes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150036:1-2150036:17, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Driss Ait Omar, Hamid Garmani, Mohamed El Amrani, Es-Said Azougaghe, Mohamed Baslam, Mostafa Jourhmane |
Towards Intelligent Control of Beaconing Power and Beaconing Rate in Vehicular Ad Hoc Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(2), pp. 2250001:1-2250001:29, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Wenjun Liu |
Reliability of DQcube Networks Under the Condition of r-Component. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150033:1-2150033:13, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Junran Yu |
Directed Tree Connectivity of Symmetric Digraphs and Complete Bipartite Digraphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(3), pp. 2250008:1-2250008:11, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Yingbin Ma, Yanfeng Xue, Xiaoxue Zhang |
Proper (Strong) Rainbow Connection and Proper (Strong) Rainbow Vertex Connection of Some Special Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(3), pp. 2250006:1-2250006:19, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Kavita K. Patil, T. Senthil Kumaran, A. Y. Prasad |
Improved Congestion Control in Wireless Sensor Networks Using Clustering with Metaheuristic Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(2), pp. 2250005:1-2250005:19, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shreedhar Yadawad, S. M. Joshi |
Energy-Efficient Data Aggregation and Cluster-Based Routing in Wireless Sensor Networks Using Tasmanian Fully Recurrent Deep Learning Network with Pelican Variable Marine Predators Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(4), pp. 2350005:1-2350005:21, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Sanjay Sudhir Kulkarni, Arjav A. Bavarva |
Crow Sun Flower Optimization-Based Handover Modules in 5G Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(3), pp. 2250009:1-2250009:22, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Gang Yang, Changxiang He |
Distance-Edge-Monitoring Sets in Hierarchical and Corona Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(2), pp. 2250003:1-2250003:9, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Zhengqin Yu, Shuming Zhou, Hong Zhang, Xiaoqing Liu |
Distance Optimally Edge Connectedness of Arrangement Graph Based on Subgraph Fault Pattern. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 23(1), pp. 2150038:1-2150038:21, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Shuai Ren |
Computer Vision for Facial Analysis Using Human-Computer Interaction Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(Supp-03), pp. 2144005:1-2144005:19, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Xufei Liu, Jinting Liu, Youlong Gong |
Low Delay Transmission Model of Internet of Things Based on Data Spectrum. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(Supp-02), pp. 2143034:1-2143034:15, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Guiyun Liu, Adhiyaman Manickam |
The Capture and Evaluation System of Student Actions in Physical Education Classroom Based on Deep Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(Supp-05), pp. 2147029:1-2147029:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Shuzhe Guo, Xiaolei Zhu, Yang Liu, Jianwei Han |
Personalized Recommendation Method of Entrepreneurial Service Information Based on Blockchain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(3), pp. 2145010:1-2145010:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Li Liu, Rama Subbareddy, C. G. Raghavendra |
AI Intelligence Chatbot to Improve Students Learning in the Higher Education Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(Supp-02), pp. 2143032:1-2143032:17, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Dongqin Cheng |
Hamiltonian Cycles Passing Through Prescribed Edges in Locally Twisted Cubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(2), pp. 2150020:1-2150020:13, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Mingyong He |
Predictive Group Learning Behavior Approach and Inquiry Learning For Higher Education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(Supp-04), pp. 2146004:1-2146004:22, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
16 | Shuo Li, Jianjun Li, Priyan Malarvizhi Kumar, Ashish Kr. Luhach |
Fish Swarm Optimized Deep Hopfield Neural Network-Assisted HCI System for Augmentative Communication Using a Visual Feedback System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Interconnect. Networks ![In: J. Interconnect. Networks 22(Supp-02), pp. 2143012:1-2143012:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
|
|