Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
150	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
145	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	Asynchronous Scan-Latch controller for Low Area Overhead DFT.	ICCD	2004	DBLP DOI BibTeX RDF
97	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Latch Susceptibility to Transient Faults and New Hardening Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design
91	Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan	Latch Modeling for Statistical Timing Analysis.	DATE	2008	DBLP DOI BibTeX RDF
91	Tomohiro Yoshihara, Dai Kobayashi, Haruo Yokota	A concurrency control protocol for parallel B-tree structures without latch-coupling for explosively growing digital content.	EDBT	2008	DBLP DOI BibTeX RDF
91	Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali	Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.	DSN	2007	DBLP DOI BibTeX RDF
89	Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg	Latch-to-Latch Timing Rules.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	latch-to-latch timing rules, consecutive latch pairs, multiple skew levels, data propagation delays, multiple clock pulse widths, clock phases, logic design, synchronous systems, combinational logic, propagation delay
83	K. Wayne Current	Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.	ISMVL	2000	DBLP DOI BibTeX RDF	quaternary, memory, circuit, latch
81	Tzu-Yuan Kuo, Jinn-Shyan Wang	A low-voltage latch-adder based tree multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
81	Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron	Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.	ISLPED	2005	DBLP DOI BibTeX RDF	architecture, power, temperature, clock gating
75	Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel	A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.	ISLPED	2006	DBLP DOI BibTeX RDF	pulse latch, low-power, latch
67	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-latch aware placement for timing-integrity optimization.	DAC	2010	DBLP DOI BibTeX RDF	pulsed latch, placement, physical design
67	Martin Saint-Laurent, Baker Mohammad, Paul Bassett	A 65-nm pulsed latch with a single clocked transistor.	ISLPED	2007	DBLP DOI BibTeX RDF	low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
67	Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain	Solving the latch mapping problem in an industrial setting.	DAC	2003	DBLP DOI BibTeX RDF	latch mapping, combinational equivalence checking
67	Jacob Savir	Reduced Latch Count Shift Registers.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	shift register latch, scan register, shifting clocks, STUMPS architecture, LSSD
64	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
64	Sanjoy Kumar Dey, Swapna Banerjee	An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC.	VLSI Design	2006	DBLP DOI BibTeX RDF
62	Srivathsan Krishnamohan, Nihar R. Mahapatra	Analysis and design of soft-error hardened latches.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	multiple-upset, single-event, soft errors, single-event upset, latch, radiation hardening
59	Flavio Carbognani, Luca Henzen	Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking.	ISLPED	2009	DBLP DOI BibTeX RDF	flipflops, low power design, clock, digital circuits, adiabatic
59	Shweta Srivastava, Jaijeet S. Roychowdhury	Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
59	Saihua Lin, Huazhong Yang, Rong Luo	High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.	ISVLSI	2007	DBLP DOI BibTeX RDF
59	Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu	Static statistical timing analysis for latch-based pipeline designs.	ICCAD	2004	DBLP DOI BibTeX RDF
59	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
59	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
56	Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz	An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists.	Formal Methods Syst. Des.	2003	DBLP DOI BibTeX RDF	phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction
56	Shaz Qadeer, Robert K. Brayton, Vigyan Singhal	Latch Redundancy Removal Without Global Reset.	ICCD	1996	DBLP DOI BibTeX RDF	global reset assumption, latch redundancy, safe replacement, delayed replacement, Finite state machine, core, strongly connected components
54	Mahdi Fazeli, Seyed Ghassem Miremadi	A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.	DFT	2008	DBLP DOI BibTeX RDF
54	Mustafa Emre Karagozler, Jason Campbell, Gary K. Fedder, Seth Copen Goldstein, Michael Philetus Weller, Byung Woo Yoon	Electrostatic latching for inter-module adhesion, power transfer, and communication in modular robots.	IROS	2007	DBLP DOI BibTeX RDF
48	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
48	Shweta Srivastava, Jaijeet S. Roychowdhury	Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations.	DAC	2007	DBLP DOI BibTeX RDF
48	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Novel Transient Fault Hardened Static Latch.	ITC	2003	DBLP DOI BibTeX RDF
48	Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.	ASP-DAC	2001	DBLP DOI BibTeX RDF
48	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
48	Victor V. Zyuban, Peter M. Kogge	Application of STD to latch-power estimation.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
48	Paul Day, John V. Woods	Investigation into micropipeline latch design styles.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
46	Amit M. Sheth, Jacob Savir	Scan Latch Design for Test Applications.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	shift register latch, scan design, hardware overhead, LSSD
46	Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing
43	Dana May Latch	NSF Announcements: Theory of Computing Program.	SIGACT News	1995	DBLP DOI BibTeX RDF
43	Dana May Latch	NSF Announcements: Theory of Computing Program.	SIGACT News	1995	DBLP DOI BibTeX RDF
43	Dana May Latch	NSF Announcements: Theory of Computing Program.	SIGACT News	1995	DBLP DOI BibTeX RDF
43	Dana May Latch, Ron Sigal	A Local Termination Property for Term Rewriting Systems.	RTA	1989	DBLP DOI BibTeX RDF
43	R. Bumby, E. Cooper, D. Latch	Interactive Computation of Homology of Finite Partially Ordered Sets.	SIAM J. Comput.	1975	DBLP DOI BibTeX RDF
43	HeungJun Jeon, Yong-Bin Kim	A low-offset high-speed double-tail dual-rail dynamic latched comparator.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	clocked comparator, dynamic latched comparator, low-offset low-power high-speed, voltage sense amplifier (sa)
43	Kim T. Le, Dong Hyun Baik, Kewal K. Saluja	Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.	VLSI Design	2007	DBLP DOI BibTeX RDF
43	Karen J. Cassidy, Kenny C. Gross, Amir Malekpour	Advanced Pattern Recognition for Detection of Complex Software Aging Phenomena in Online Transaction Processing Servers.	DSN	2002	DBLP DOI BibTeX RDF
43	Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi	Automatic state space decomposition for approximate FSM traversal based on circuit analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
40	Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev	Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment.	ISQED	2005	DBLP DOI BibTeX RDF	Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in
38	Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
38	Shweta Srivastava, Jaijeet S. Roychowdhury	Rapid and accurate latch characterization via direct Newton solution of setup/hold times.	DATE	2007	DBLP DOI BibTeX RDF
38	Holly Pekau, Lee Hartley, James W. Haslett	A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications].	ISCAS (6)	2005	DBLP DOI BibTeX RDF
38	R. Singh, N. Bhat	An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
38	Li Ding 0002, Pinaki Mazumder, N. Srinivas	A dual-rail static edge-triggered latch.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
38	Claude Arm, Jean-Marc Masgonty, Christian Piguet	Double-Latch Clocking Scheme for Low-Power I.P. Cores.	PATMOS	2000	DBLP DOI BibTeX RDF
38	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
38	Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann	Optimal latch mapping and retiming within a tree.	ICCAD	1994	DBLP DOI BibTeX RDF
35	Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito	Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
35	Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto	An Experimental Study on Latch Up Failure of CMOS LSI.	SSIRI	2008	DBLP DOI BibTeX RDF	latch up, CMOS LSI
35	Jacob Savir	The Bidirectional Double Latch (BDDL).	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD
33	Zhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen	SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process.	DAC	2022	DBLP DOI BibTeX RDF
33	Naoki Fujieda, Shuichi Ichikawa	A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
33	Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi	DIRT latch: A novel low cost double node upset tolerant latch.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
33	Vijay Savani, N. M. Devashrayee	Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology.	VDAT	2015	DBLP DOI BibTeX RDF
33	Michael Heer, Krzysztof Domanski, Kai Esmark, Ulrich Glaser, Dionyz Pogany, Erich Gornik, Wolfgang Stadler	Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
33	Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli	Power dissipation in one-latch and two-latch double edge triggered flip-flops.	ICECS	1999	DBLP DOI BibTeX RDF
32	Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj	3D configuration caching for 2D FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
32	Saihua Lin, Huazhong Yang, Rong Luo	A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
32	Min-Lun Chuang, Chun-Yao Wang	Synthesis of reversible sequential elements.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	sequential elements, sequential circuits, Reversible logic
32	Min-Lun Chuang, Chun-Yao Wang	Synthesis of Reversible Sequential Elements.	ASP-DAC	2007	DBLP DOI BibTeX RDF
32	Jun Zhou, David Kinniment, Gordon Russell 0002, Alexandre Yakovlev	A Robust Synchronizer.	ISVLSI	2006	DBLP DOI BibTeX RDF
32	Soumitra Bose, Amit Nandi	Schematic array models for associative and non-associative memory circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
32	Payam Heydari, Ravindran Mohanavelu	Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
32	Soumitra Bose, Amit Nandi	Extraction of Schematic Array Models for Memory Circuits.	DATE	2004	DBLP DOI BibTeX RDF
32	Payam Heydari, Ravindran Mohanavelu	Design of ultra high-speed CMOS CML buffers and latches.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
32	Tsung-Chu Huang, Kuen-Jong Lee	Reduction of power consumption in scan-based circuits during testapplication by an input control technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
32	Nobuo Funabiki, Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	A Global Routing Technique for Wave-Steering Design Methodology.	DSD	2001	DBLP DOI BibTeX RDF
32	David L. Harris, Mark Horowitz, Dean Liu	Timing analysis including clock skew.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
32	Tsung-Chu Huang, Kuen-Jong Lee	An Input Control Technique for Power Reduction in Scan Circuits During Test Application.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
32	Prashant Saxena, Peichen Pan, C. L. Liu 0001	The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.	VLSI Design	1999	DBLP DOI BibTeX RDF
32	Jacob Savir	On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
32	Weiwei Mao, Michael D. Ciletti	Reducing correlation to improve coverage of delay faults in scan-path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
32	Srinivas Devadas	Approaches to Multi-level Sequential Logic Synthesis.	DAC	1989	DBLP DOI BibTeX RDF
29	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
29	Charles E. Molnar, Ian W. Jones	Simple Circuits that Work for Complicated Reasons.	ASYNC	2000	DBLP DOI BibTeX RDF	MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
29	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
29	Octavian-Dumitru Mocanu, Joan Oliver	Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	hamming SEC code, latch-up, memory system, single event upset, built-in current sensor
29	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	A unified approach in the analysis of latches and flip-flops for low-power systems.	ISLPED	1998	DBLP DOI BibTeX RDF	master-slave latch, optimization, timing, flip-flop, power measurement
29	Jacob Savir	Module level weighted random patterns.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
29	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
29	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
27		Latch Coupling.	Encyclopedia of Database Systems	2009	DBLP DOI BibTeX RDF
27	Chen-Hsuan Lin, Chun-Yao Wang	Dependent latch identification in the reachable state space.	ASP-DAC	2009	DBLP DOI BibTeX RDF
27	Chuan Lin 0002, Hai Zhou 0001	Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Kun Young Chung, Sandeep K. Gupta 0001	Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing.	VTS	2006	DBLP DOI BibTeX RDF
27	Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner	Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.	PATMOS	2005	DBLP DOI BibTeX RDF
27	Omid Mirmotahari, Yngvar Berg	A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
27	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
27	Massimo Alioto, Gaetano Palumbo	Design of MUX, XOR and D-latch SCL gates.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Marek Wróblewski, Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, Wilhelm Pieper, Josef A. Nossek	A power efficient register file architecture using master latch sharing.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
27	Peter Dahlgren, Paul Dickinson, Ishwar Parulkar	Latch Divergency In Microprocessor Failure Analysis.	ITC	2003	DBLP DOI BibTeX RDF
27	Kun Young Chung, Sandeep K. Gupta 0001	Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.	ITC	2003	DBLP DOI BibTeX RDF