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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 700 occurrences of 376 keywords
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Results
Found 2246 publication records. Showing 2246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
134 | Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik |
An approach for adaptive DRAM temperature and power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 63-72, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
power, temperature, DRAM |
127 | Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith 0001 |
Power-Efficient DRAM Speculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 317-328, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
126 | Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge |
High-Performance DRAMs in Workstation Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1133-1153, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling |
118 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David |
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 94-104, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip |
108 | Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun |
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 303-319, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
105 | George L. Yuan, Ali Bakhoda, Tor M. Aamodt |
Complexity effective memory access scheduling for many-core accelerator architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 34-44, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
graphics processors, on-chip interconnection networks, memory controller |
102 | Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich Weber |
DRAM errors in the wild: a large-scale field study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS/Performance ![In: Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems, SIGMETRICS/Performance 2009, Seattle, WA, USA, June 15-19, 2009, pp. 193-204, 2009, ACM, 978-1-60558-511-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dimm, dram reliability, ecc, hard error, empirical study, memory, soft error, dram, large-scale systems, data corruption |
102 | Taku Ohsawa, Koji Kai, Kazuaki J. Murakami |
Optimizing the DRAM refresh count for merged DRAM/logic LSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 82-87, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
99 | Yangyang Pan, Tong Zhang 0002 |
Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 38-45, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
96 | Mrinmoy Ghosh, Hsien-Hsin S. Lee |
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 134-145, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
96 | Jahangir Hasan, Satish Chandra 0001, T. N. Vijaykumar |
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 300-311, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
96 | Yangyang Pan, Tong Zhang 0002 |
DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 290, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dram-based fpga, memory stacking, 3d integration |
96 | Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi |
Rethinking DRAM design and organization for energy-constrained multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 175-186, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
chipkill, dram architecture, subarrays, energy-efficiency, locality |
86 | Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic |
Re-architecting DRAM memory systems with monolithically integrated silicon photonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 129-140, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dram architecture, energy-efficiency, silicon photonics |
86 | Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik |
A power and temperature aware DRAM architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 878-883, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
page hit aware write buffer, power, temperature, DRAM |
82 | Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg |
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 155-165, 2006, IEEE Computer Society, 0-7803-9368-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
80 | Youhei Zenda, Koji Nakamae, Hiromu Fujioka |
Cost Optimum Embedded DRAM Design by Yield Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 20-, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
80 | Haifeng Yu, Gershon Kedem |
DRAM-Page Based Prediction and Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 267-275, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
77 | Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt |
Improving memory bank-level parallelism in the presence of prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 327-336, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
77 | Onur Mutlu, Thomas Moscibroda |
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 146-160, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
70 | Pei-Lin Pai |
DRAM Industry Trend. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
70 | Zhichun Zhu, Zhao Zhang 0010 |
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 213-224, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
70 | Anru Wang, Wayne Wei-Ming Dai |
Area-IO DRAM/logic integration with system-in-a-package (SiP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 893-896, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
70 | Markus Rudack, Dirk Niggemeyer |
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 31-39, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
67 | Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 |
Design and Optimization of Large Size and Low Overhead Off-Chip Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 843-855, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Ahmed M. Amin, Zeshan Chishti |
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 383-388, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
DRAM energy efficiency, cache replacement, write buffer |
67 | Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis |
Micro-pages: increasing DRAM efficiency with locality-aware data placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 219-230, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dram row-buffer management, data placement |
67 | Qi Wu 0006, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002 |
Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 245-250, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
three-dimentional integration, dram, decoupling capacitor |
67 | Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger |
Architecting phase change memory as a scalable dram alternative. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 2-13, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance |
67 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu |
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 255-266, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bandwidth decoupling, decoupled DIMM, DRAM memories |
67 | Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin |
Fault models for embedded-DRAM macros. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 714-719, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
memory testing, embedded DRAM |
67 | Zaid Al-Ars, Ad J. van de Goor |
DRAM Specific Approximation of the Faulty Behavior of Cell Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 98-103, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory specific fault analysis, approximating dynamic behavior, memory testing, DRAM |
64 | Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers |
Scalable high performance main memory system using phase-change memory technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 24-33, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dram caching, phase change memory, wear leveling |
64 | Chin-Te Kao, Sam Wu, Jwu E. Chen |
A case study of failure analysis and guardband determination for a 64M-bit DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 447-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics |
64 | Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter |
Combined DRAM and logic chip for massively parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 4-16, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits |
60 | Rakesh S. Anigundi, Hongbin Sun 0001, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002 |
Architecture design exploration of three-dimensional (3D) integrated DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 86-90, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
60 | Ibrahim Hur, Calvin Lin |
A comprehensive approach to DRAM power management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 305-316, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi |
Effective Management of DRAM Bandwidth in Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 245-258, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell |
Exploring DRAM cache architectures for CMP server platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 55-62, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak |
Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2108-2111, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Haakon Dybdahl, Marius Grannæs, Lasse Natvig |
Cache Write-Back Schemes for Embedded Destructive-Read DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 145-159, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Anru Wang, Wayne Wei-Ming Dai |
Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 562-566, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001 |
Cached DRAM for ILP Processor Memory Access Latency Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 21(4), pp. 22-32, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
60 | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin |
Hardware and Software Techniques for Controlling DRAM Power Modes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1154-1173, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
low power compilation, software-directed energy management, low power, Memory architecture |
60 | Vinodh Cuppu, Bruce L. Jacob |
Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 62-71, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Systems Application Architecture |
60 | Brian Davis, Bruce L. Jacob, Trevor N. Mudge |
The New DRAM Interfaces: SDRAM, RDRAM and Variants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 26-31, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
57 | Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum |
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 23-30, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
superoperators, embedded systems, java virtual machine, energy estimation, profile-guided optimization |
57 | G. Jack Lipovski |
A four megabit Dynamic Systolic Associative Memory chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 4(1), pp. 37-51, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
57 | Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg |
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 147-160, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
memory technology, dynamic voltage scaling, DRAM, molecular electronics, molecular memory, low-power memory |
57 | Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck |
Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers, pp. 130-140, 2002, Springer, 3-540-01028-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Modeling, Petri Nets, DRAM, Memory Controller, Control Policy |
51 | Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao |
A randomized interleaved DRAM architecture for the maintenance of exact statistics counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS Perform. Evaluation Rev. ![In: SIGMETRICS Perform. Evaluation Rev. 37(2), pp. 53-54, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Gabriel H. Loh |
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 201-212, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
51 | Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu |
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 210-221, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt |
Prefetch-Aware DRAM Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 200-209, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Mohammed G. Khatib, Berend-Jan van der Zwaag, Pieter H. Hartel, Gerard J. M. Smit |
Interposing Flash between Disk and DRAM to Save Energy for Streaming Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESTIMedia ![In: Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2007, October 4-5, Salzburg, Austria, conjunction with CODES+ISSS 2007, pp. 7-12, 2007, IEEE Computer Society, 978-1-4244-1654-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Jike Chong, Chidamber Kulkarni, Gordon J. Brebner |
Building a flexible and scalable DRAM interface for networking applications on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 233, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Jyi-Tsong Lin, Mike Chang |
A New 1T DRAM Cell With Enhanced Floating Body Ef. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 23-27, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
51 | Lars Friebe, Yoshikazu Yabe, Masato Motomura |
A Study of Channeled DRAM Memory Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 261-266, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
51 | Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang |
A Programmable BIST Core for Embedded DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(1), pp. 59-70, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
51 | Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge |
A Performance Comparison of Contemporary DRAM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 222-233, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
48 | Girish B. C., R. Govindarajan |
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QEST ![In: Fourth International Conference on the Quantitative Evaluaiton of Systems (QEST 2007), 17-19 September 2007, Edinburgh, Scotland, UK, pp. 19-30, 2007, IEEE Computer Society, 0-7695-2883-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
48 | Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak |
Handheld System Energy Reduction by OS-Driven Refresh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 24-35, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Qi Zhao 0006, Jun (Jim) Xu, Zhen Liu |
Design of a novel statistics counter architecture with optimal space and time efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS/Performance ![In: Proceedings of the Joint International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS/Performance 2006, Saint Malo, France, June 26-30, 2006, pp. 323-334, 2006, ACM, 1-59593-319-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
statistics counter, data streaming, router |
48 | Jung Ho Ahn, Mattan Erez, William J. Dally |
Architecture - The design space of data-parallel memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 80, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Laurent Lopez, Jean-Michel Portal, Didier Née |
A New Embedded Measurement Structure for eDRAM Capacitor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 462-463, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
48 | Philip Machanick |
Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 146-159, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Joohee Kim, Marios C. Papaefthymiou |
Block-based multiperiod dynamic memory design for low data-retention power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(6), pp. 1006-1018, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero |
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 373-386, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
VL-CDRAM: variable line sized cached DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 132-137, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CDRAM, VL-CDRAM, variable line, energy |
48 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang 0010 |
Software thermal management of dram memory for multicore systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2-6, 2008, pp. 337-348, 2008, ACM, 978-1-60558-005-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
thermal management, DRAM memories |
48 | Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010 |
Thermal modeling and management of DRAM memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 312-322, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
thermal management, thermal modeling, DRAM memories |
45 | Zhichun Zhu, Zhao Zhang 0010, Xiaodong Zhang 0001 |
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 107-116, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DRAM configurations, fine-grain priority scheduling, memory-intensive applications and multi-channel memory systems |
45 | Wei-Fen Lin, Steven K. Reinhardt, Doug Burger |
Designing a Modern Memory Hierarchy with Hardware Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(11), pp. 1202-1218, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design |
45 | Balasubramanya Bhat, Frank Mueller 0001 |
Making DRAM Refresh Predictable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 22nd Euromicro Conference on Real-Time Systems, ECRTS 2010, Brussels, Belgium, July 6-9, 2010, pp. 145-154, 2010, IEEE Computer Society, 978-0-7695-4111-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
DRAM Refresh, Real-Time Systems, Timing Analysis, DRAM, Worst-Case Execution Time, Timing Predictability |
45 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 72-82, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
45 | Ki Chul Chun, Pulkit Jain, Chris H. Kim |
A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 119-120, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3T DRAM, gain cell, retention time, cache, static power, embedded DRAM |
42 | Sying-Jyan Wang, Chen-Jung Wei |
Efficient built-in self-test algorithm for memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 66-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips |
41 | Ciji Isen, Lizy Kurian John |
ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 337-346, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
allocated and freed memory states, cross-boundary or cross-layer architecture optimizations, memory power and energy, program semantic aware architecture |
41 | Daniel Schmidt 0001, Norbert Wehn |
DRAM power management and energy consumption: a critical assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
modelling, measurement, power management, SDRAM |
41 | Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar |
A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 373-378, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Martin Versen, Achim Schramm, Jan Schnepp, Dorina Diaconescu |
Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 776-779, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Chan-Kyung Kim, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun |
CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3094-3097, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Chiyuan Ma, Shuming Chen |
A DRAM Precharge Policy Based on Address Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 244-248, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Motoi Ichihashi, Haruki Toda |
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 487-490, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi |
Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 988-996, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Virantha N. Ekanayake, Rajit Manohar |
Asynchronous DRAM Design and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 174-183, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Wei-Chung Cheng, Massoud Pedram |
Power-optimal encoding for a DRAM address bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(2), pp. 109-118, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Masashi Hashimoto |
Adder Merged DRAM Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 88-94, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Wei-Fen Lin, Steven K. Reinhardt, Doug Burger |
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 301-312, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin |
DRAM Energy Management Using Software and Hardware Directed Power Mode Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 159-169, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Low Power Compilation, Software-Directed Energy Management, Low Power, Memory Architecture |
41 | Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano |
A prototype chip of multicontext FPGA with DRAM for virtual hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 17-18, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho |
BIST-Based Bitfail Mapping of an Embedded DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 29-, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Sunho Chang, Lee-Sup Kim |
Design trade-off in merged DRAM logic for video signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 267-270, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Wei-Chung Cheng, Massoud Pedram |
Power-optimal encoding for DRAM address bus (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 250-252, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Matthias Gries |
The Impact of Recent DRAM Architectures on Embedded Systems Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1282-, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | Shinji Miyano, Katsuhiko Sato, Kenji Numata |
Universal Test Interface for Embedded-DRAM Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(1), pp. 53-58, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Roderick McConnell, Udo Möller, Detlev Richter |
How we test Siemens Embedded DRAM Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1120-1125, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Tzi-cker Chiueh, Srinidhi Varadarajan |
Design and Evaluation of a DRAM-based Shared Memory ATM Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, Seattle, Washington, USA, June 15-18, 1997, pp. 248-259, 1997, ACM, 0-89791-909-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
41 | John Poulton |
An Embedded DRAM for CMOS ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 288-302, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger |
Use ECP, not ECC, for hard failures in resistive memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 141-152, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
hard failures, resistive memories, memory, error correction, phase change memory |
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