Search results for "DRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
134	Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik	An approach for adaptive DRAM temperature and power management.	ICS	2008	DBLP DOI BibTeX RDF	power, temperature, DRAM
127	Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, James E. Smith 0001	Power-Efficient DRAM Speculation.	HPCA	2008	DBLP DOI BibTeX RDF
126	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	High-Performance DRAMs in Workstation Environments.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	DRAM architectures, DRAM performance, DRAM systems, DDR DRAM, Direct Rambus DRAM, PC100 SDRAM, DDR2 DRAM, system modeling
118	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhang 0010, Howard David	DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.	ISPASS	2007	DBLP DOI BibTeX RDF	channel bandwidth utilization, DRAM-level prefetching, dynamic random access memory, fully-buffered DIMM, dual in-line memory module, redundant bandwidth, memory block, L2 cache block, DRAM power consumption, SPEC2000 program, software cache prefetching, idle memory latency, power saving, multicore processor, memory controller, interconnect structure, DRAM chip
108	Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun	The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.	ARVLSI	1997	DBLP DOI BibTeX RDF
105	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
102	Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich Weber	DRAM errors in the wild: a large-scale field study.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	dimm, dram reliability, ecc, hard error, empirical study, memory, soft error, dram, large-scale systems, data corruption
102	Taku Ohsawa, Koji Kai, Kazuaki J. Murakami	Optimizing the DRAM refresh count for merged DRAM/logic LSIs.	ISLPED	1998	DBLP DOI BibTeX RDF
99	Yangyang Pan, Tong Zhang 0002	Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking.	ASAP	2009	DBLP DOI BibTeX RDF
96	Mrinmoy Ghosh, Hsien-Hsin S. Lee	Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs.	MICRO	2007	DBLP DOI BibTeX RDF
96	Jahangir Hasan, Satish Chandra 0001, T. N. Vijaykumar	Efficient Use of Memory Bandwidth to Improve Network Processor Throughput.	ISCA	2003	DBLP DOI BibTeX RDF
96	Yangyang Pan, Tong Zhang 0002	DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dram-based fpga, memory stacking, 3d integration
96	Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Rethinking DRAM design and organization for energy-constrained multi-cores.	ISCA	2010	DBLP DOI BibTeX RDF	chipkill, dram architecture, subarrays, energy-efficiency, locality
86	Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic	Re-architecting DRAM memory systems with monolithically integrated silicon photonics.	ISCA	2010	DBLP DOI BibTeX RDF	dram architecture, energy-efficiency, silicon photonics
86	Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik	A power and temperature aware DRAM architecture.	DAC	2008	DBLP DOI BibTeX RDF	page hit aware write buffer, power, temperature, DRAM
82	Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg	Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM.	HPCA	2006	DBLP DOI BibTeX RDF
80	Youhei Zenda, Koji Nakamae, Hiromu Fujioka	Cost Optimum Embedded DRAM Design by Yield Analysis.	MTDT	2003	DBLP DOI BibTeX RDF
80	Haifeng Yu, Gershon Kedem	DRAM-Page Based Prediction and Prefetching.	ICCD	2000	DBLP DOI BibTeX RDF
77	Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt	Improving memory bank-level parallelism in the presence of prefetching.	MICRO	2009	DBLP DOI BibTeX RDF
77	Onur Mutlu, Thomas Moscibroda	Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
70	Pei-Lin Pai	DRAM Industry Trend.	MTDT	2006	DBLP DOI BibTeX RDF
70	Zhichun Zhu, Zhao Zhang 0010	A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.	HPCA	2005	DBLP DOI BibTeX RDF
70	Anru Wang, Wayne Wei-Ming Dai	Area-IO DRAM/logic integration with system-in-a-package (SiP).	ASP-DAC	2005	DBLP DOI BibTeX RDF
70	Markus Rudack, Dirk Niggemeyer	Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM.	DFT	1999	DBLP DOI BibTeX RDF
67	Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001	Design and Optimization of Large Size and Low Overhead Off-Chip Caches.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
67	Ahmed M. Amin, Zeshan Chishti	Rank-aware cache replacement and write buffering to improve DRAM energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	DRAM energy efficiency, cache replacement, write buffer
67	Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis	Micro-pages: increasing DRAM efficiency with locality-aware data placement.	ASPLOS	2010	DBLP DOI BibTeX RDF	dram row-buffer management, data placement
67	Qi Wu 0006, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002	Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	three-dimentional integration, dram, decoupling capacitor
67	Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger	Architecting phase change memory as a scalable dram alternative.	ISCA	2009	DBLP DOI BibTeX RDF	dram alternative, performance, scalability, power, energy, phase change memory, pcm, endurance
67	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Zhichun Zhu	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.	ISCA	2009	DBLP DOI BibTeX RDF	bandwidth decoupling, decoupled DIMM, DRAM memories
67	Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin	Fault models for embedded-DRAM macros.	DAC	2009	DBLP DOI BibTeX RDF	memory testing, embedded DRAM
67	Zaid Al-Ars, Ad J. van de Goor	DRAM Specific Approximation of the Faulty Behavior of Cell Defects.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	memory specific fault analysis, approximating dynamic behavior, memory testing, DRAM
64	Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers	Scalable high performance main memory system using phase-change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	dram caching, phase change memory, wear leveling
64	Chin-Te Kao, Sam Wu, Jwu E. Chen	A case study of failure analysis and guardband determination for a 64M-bit DRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
64	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
60	Rakesh S. Anigundi, Hongbin Sun 0001, Jian-Qiang Lu, Kenneth Rose, Tong Zhang 0002	Architecture design exploration of three-dimensional (3D) integrated DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
60	Ibrahim Hur, Calvin Lin	A comprehensive approach to DRAM power management.	HPCA	2008	DBLP DOI BibTeX RDF
60	Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi	Effective Management of DRAM Bandwidth in Multicore Processors.	PACT	2007	DBLP DOI BibTeX RDF
60	Li Zhao 0002, Ravi R. Iyer 0001, Ramesh Illikkal, Donald Newell	Exploring DRAM cache architectures for CMP server platforms.	ICCD	2007	DBLP DOI BibTeX RDF
60	Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak	Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh.	ISCAS	2007	DBLP DOI BibTeX RDF
60	Haakon Dybdahl, Marius Grannæs, Lasse Natvig	Cache Write-Back Schemes for Embedded Destructive-Read DRAM.	ARCS	2006	DBLP DOI BibTeX RDF
60	Anru Wang, Wayne Wei-Ming Dai	Design and Analysis of Area-IO DRAM/Logic Integration with System-in-a-Package(SiP).	ISQED	2005	DBLP DOI BibTeX RDF
60	Zhao Zhang 0010, Zhichun Zhu, Xiaodong Zhang 0001	Cached DRAM for ILP Processor Memory Access Latency Reduction.	IEEE Micro	2001	DBLP DOI BibTeX RDF
60	Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	Hardware and Software Techniques for Controlling DRAM Power Modes.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	low power compilation, software-directed energy management, low power, Memory architecture
60	Vinodh Cuppu, Bruce L. Jacob	Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?.	ISCA	2001	DBLP DOI BibTeX RDF	Systems Application Architecture
60	Brian Davis, Bruce L. Jacob, Trevor N. Mudge	The New DRAM Interfaces: SDRAM, RDRAM and Variants.	ISHPC	2000	DBLP DOI BibTeX RDF
57	Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum	Impact of JVM superoperators on energy consumption in resource-constrained embedded systems.	LCTES	2008	DBLP DOI BibTeX RDF	superoperators, embedded systems, java virtual machine, energy estimation, profile-guided optimization
57	G. Jack Lipovski	A four megabit Dynamic Systolic Associative Memory chip.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
57	Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg	ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	memory technology, dynamic voltage scaling, DRAM, molecular electronics, molecular memory, low-power memory
57	Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck	Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets.	PACS	2002	DBLP DOI BibTeX RDF	Modeling, Petri Nets, DRAM, Memory Controller, Control Policy
51	Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao	A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
51	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
51	Hongzhong Zheng, Jiang Lin, Zhao Zhang 0010, Eugene Gorbatov, Howard David, Zhichun Zhu	Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.	MICRO	2008	DBLP DOI BibTeX RDF
51	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware DRAM Controllers.	MICRO	2008	DBLP DOI BibTeX RDF
51	Mohammed G. Khatib, Berend-Jan van der Zwaag, Pieter H. Hartel, Gerard J. M. Smit	Interposing Flash between Disk and DRAM to Save Energy for Streaming Workloads.	ESTIMedia	2007	DBLP DOI BibTeX RDF
51	Jike Chong, Chidamber Kulkarni, Gordon J. Brebner	Building a flexible and scalable DRAM interface for networking applications on FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
51	Jyi-Tsong Lin, Mike Chang	A New 1T DRAM Cell With Enhanced Floating Body Ef.	MTDT	2006	DBLP DOI BibTeX RDF
51	Lars Friebe, Yoshikazu Yabe, Masato Motomura	A Study of Channeled DRAM Memory Architectures.	ICCD	2000	DBLP DOI BibTeX RDF
51	Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang	A Programmable BIST Core for Embedded DRAM.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
51	Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge	A Performance Comparison of Contemporary DRAM Architectures.	ISCA	1999	DBLP DOI BibTeX RDF
48	Girish B. C., R. Govindarajan	A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor.	QEST	2007	DBLP DOI BibTeX RDF
48	Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak	Handheld System Energy Reduction by OS-Driven Refresh.	PATMOS	2006	DBLP DOI BibTeX RDF
48	Qi Zhao 0006, Jun (Jim) Xu, Zhen Liu	Design of a novel statistics counter architecture with optimal space and time efficiency.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	statistics counter, data streaming, router
48	Jung Ho Ahn, Mattan Erez, William J. Dally	Architecture - The design space of data-parallel memory systems.	SC	2006	DBLP DOI BibTeX RDF
48	Laurent Lopez, Jean-Michel Portal, Didier Née	A New Embedded Measurement Structure for eDRAM Capacitor.	DATE	2005	DBLP DOI BibTeX RDF
48	Philip Machanick	Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
48	Joohee Kim, Marios C. Papaefthymiou	Block-based multiperiod dynamic memory design for low data-retention power.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
48	Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero	Design and Implementation of High-Performance Memory Systems for Future Packet Buffers.	MICRO	2003	DBLP DOI BibTeX RDF
48	Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	VL-CDRAM: variable line sized cached DRAMs.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	CDRAM, VL-CDRAM, variable line, energy
48	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang 0010	Software thermal management of dram memory for multicore systems.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	thermal management, DRAM memories
48	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang 0010	Thermal modeling and management of DRAM memory systems.	ISCA	2007	DBLP DOI BibTeX RDF	thermal management, thermal modeling, DRAM memories
45	Zhichun Zhu, Zhao Zhang 0010, Xiaodong Zhang 0001	Fine-Grain Priority Scheduling on Multi-Channel Memory Systems.	HPCA	2002	DBLP DOI BibTeX RDF	DRAM configurations, fine-grain priority scheduling, memory-intensive applications and multi-channel memory systems
45	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Designing a Modern Memory Hierarchy with Hardware Prefetching.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Rambus DRAM, caches, Prefetching, memory bandwidth, spatial locality, memory system design
45	Balasubramanya Bhat, Frank Mueller 0001	Making DRAM Refresh Predictable.	ECRTS	2010	DBLP DOI BibTeX RDF	DRAM Refresh, Real-Time Systems, Timing Analysis, DRAM, Worst-Case Execution Time, Timing Predictability
45	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
45	Ki Chul Chun, Pulkit Jain, Chris H. Kim	A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	3T DRAM, gain cell, retention time, cache, static power, embedded DRAM
42	Sying-Jyan Wang, Chen-Jung Wei	Efficient built-in self-test algorithm for memory.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	built-in self-test algorithm, built-in self test, BIST, DRAM, test patterns, pseudorandom testing, coupling faults, DRAM chips
41	Ciji Isen, Lizy Kurian John	ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem.	MICRO	2009	DBLP DOI BibTeX RDF	allocated and freed memory states, cross-boundary or cross-layer architecture optimizations, memory power and energy, program semantic aware architecture
41	Daniel Schmidt 0001, Norbert Wehn	DRAM power management and energy consumption: a critical assessment.	SBCCI	2009	DBLP DOI BibTeX RDF	modelling, measurement, power management, SDRAM
41	Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar	A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link.	VLSI Design	2009	DBLP DOI BibTeX RDF
41	Martin Versen, Achim Schramm, Jan Schnepp, Dorina Diaconescu	Test Instrumentation for a Laser Scanning Localization Technique for Analysis of High Speed DRAM devices.	DATE	2008	DBLP DOI BibTeX RDF
41	Chan-Kyung Kim, Bai-Sun Kong, Chil-Gee Lee, Young-Hyun Jun	CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control.	ISCAS	2008	DBLP DOI BibTeX RDF
41	Chiyuan Ma, Shuming Chen	A DRAM Precharge Policy Based on Address Analysis.	DSD	2007	DBLP DOI BibTeX RDF
41	Motoi Ichihashi, Haruki Toda	Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation.	VLSI Design	2006	DBLP DOI BibTeX RDF
41	Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi	Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.	ITC	2004	DBLP DOI BibTeX RDF
41	Virantha N. Ekanayake, Rajit Manohar	Asynchronous DRAM Design and Synthesis.	ASYNC	2003	DBLP DOI BibTeX RDF
41	Wei-Chung Cheng, Massoud Pedram	Power-optimal encoding for a DRAM address bus.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
41	Masashi Hashimoto	Adder Merged DRAM Architecture.	MTDT	2002	DBLP DOI BibTeX RDF
41	Wei-Fen Lin, Steven K. Reinhardt, Doug Burger	Reducing DRAM Latencies with an Integrated Memory Hierarchy Design.	HPCA	2001	DBLP DOI BibTeX RDF
41	Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin	DRAM Energy Management Using Software and Hardware Directed Power Mode Control.	HPCA	2001	DBLP DOI BibTeX RDF	Low Power Compilation, Software-Directed Energy Management, Low Power, Memory Architecture
41	Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano	A prototype chip of multicontext FPGA with DRAM for virtual hardware.	ASP-DAC	2001	DBLP DOI BibTeX RDF
41	Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho	BIST-Based Bitfail Mapping of an Embedded DRAM.	MTDT	2001	DBLP DOI BibTeX RDF
41	Sunho Chang, Lee-Sup Kim	Design trade-off in merged DRAM logic for video signal processing.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
41	Wei-Chung Cheng, Massoud Pedram	Power-optimal encoding for DRAM address bus (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
41	Matthias Gries	The Impact of Recent DRAM Architectures on Embedded Systems Performance.	EUROMICRO	2000	DBLP DOI BibTeX RDF
41	Shinji Miyano, Katsuhiko Sato, Kenji Numata	Universal Test Interface for Embedded-DRAM Testing.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
41	Roderick McConnell, Udo Möller, Detlev Richter	How we test Siemens Embedded DRAM Cores.	ITC	1998	DBLP DOI BibTeX RDF
41	Tzi-cker Chiueh, Srinidhi Varadarajan	Design and Evaluation of a DRAM-based Shared Memory ATM Switch.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
41	John Poulton	An Embedded DRAM for CMOS ASICs.	ARVLSI	1997	DBLP DOI BibTeX RDF
38	Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger	Use ECP, not ECC, for hard failures in resistive memories.	ISCA	2010	DBLP DOI BibTeX RDF	hard failures, resistive memories, memory, error correction, phase change memory