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1960-1975 (15) 1976-1981 (16) 1982-1986 (15) 1987-1988 (24) 1989 (15) 1990 (18) 1991-1992 (27) 1993 (25) 1994 (19) 1995 (40) 1996 (35) 1997 (32) 1998 (22) 1999 (44) 2000 (58) 2001 (39) 2002 (42) 2003 (40) 2004 (56) 2005 (74) 2006 (71) 2007 (81) 2008 (83) 2009 (54) 2010 (28) 2011 (23) 2012 (21) 2013 (27) 2014 (20) 2015 (19) 2016 (25) 2017 (20) 2018 (36) 2019 (22) 2020 (16) 2021 (27) 2022 (30) 2023 (61) 2024 (4)
Publication types (Num. hits)
article(449) book(2) incollection(4) inproceedings(857) phdthesis(11) proceedings(1)
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Found 1324 publication records. Showing 1324 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
52Stanley E. Lass Automated printed circuit routing with a stepping aperture. Search on Bibsonomy Commun. ACM The full citation details ... 1969 DBLP  DOI  BibTeX  RDF circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture
52Yongseok Cheon, Martin D. F. Wong Crowdedness-balanced multilevel partitioning for uniform resource utilization. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
51Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan Low-cost diagnosis of defects in MCM substrate interconnections. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF low-cost diagnosis, MCM substrate interconnections, substrate interconnect defects, defect location, defect size, fault diagnosis, integrated circuit testing, fault location, multichip modules, integrated circuit interconnections, fault-dictionary, substrates
43Shinichi Shionoya, Takafumi Aoki, Tatsuo Higuchi 0001 Multiwave Interconnection Networks for MCM-based Parallel Processing. Search on Bibsonomy Euro-Par The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Multichip module (MCM), messagepassing multiprocessors, parallel processing, interconnection networks, optical interconnections, wavelength division multiplexing (WDM)
43Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee Physical models and algorithms for optoelectronic MCM layout. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
42Dohoon Kim An architecture for internet inter-domain interconnections and bandwidth trading towards effective NGN deployment. Search on Bibsonomy Ann. des Télécommunications The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Internet interconnections, Bandwidth trading, Hub-and-spoke network, Network operations and management, NGN, Inter-Domain routing, End-to-end QoS, Network economics
42Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals A High-Speed Optical Multi-Drop Bus for Computer Interconnections. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus
42Jae-dong Lee, Kenneth E. Batcher A bitonic sorting network with simpler flip interconnections. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF flip interconnections, bitonic sorting network, inter-level wiring, parity technique, Construct-BSMF, N/2 even-parity keys, interconnection scheme, perfect-shuffle interconnection, parallel algorithms, parallel architectures, multiprocessor interconnection networks, sorting
42Alex Fit-Florea, Miroslav Halás, Fatih Kocan Enhancing Reliability of Operational Interconnections in FPGAs. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst Silicon VLSI processing architectures incorporating integrated optoelectronic devices. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si
35X. Cai, Keith Nabors, Jacob K. White 0001 Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures
35T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF self-timed CMOS design, testing interconnections, boundary-scan, MCM testing
35Guy Even, Ami Litman Overcoming chip-to-chip delays and clock skews. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
34Simon M. Kaplan, Steven K. Goering Garp: a graphical/textual language for concurrent programming. Search on Bibsonomy OOPSLA/ECOOP Workshop on Object-based Concurrent Programming The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
34Jianping Quan, Guoqiang Bai 0001 A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles. Search on Bibsonomy ITNG The full citation details ... 2009 DBLP  DOI  BibTeX  RDF WDDL, TDPL, NSDDL, unbalanced interconnections, early propagation effect, routing
34Yitzhak Birk, Noam Bloch The effects of destructive interference and wasted transmissions on the uniform-traffic capacity of non-bus-oriented single-hop interconnections. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF fiber optic networks, shared directional multichannel, single-hop interconnections, local area networks, capacity, multiple access
34Joe Kilian, Shlomo Kipnis, Charles E. Leiserson The Organization of Permutation Architectures with Bused Interconnections. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF permutation architectures, bused interconnections, abelian, combinatorial notion, multiprocessor interconnection networks, VLSI chips
33Weisheng Chen, Junmin Li Decentralized Output-Feedback Neural Control for Systems With Unknown Interconnections. Search on Bibsonomy IEEE Trans. Syst. Man Cybern. Part B The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk Global interconnections in FPGAs: modeling and performance analysis. Search on Bibsonomy SLIP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, throughput, interconnection, wave-pipelined
33Yuriy Sheynin, Elena Suvorova, Felix Shutenko Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Ming Cong, Sunan Huang 0002 Neural Network Control Design for Large-Scale Systems with Higher-Order Interconnections. Search on Bibsonomy ISNN (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Chen Dong 0003, S. Haruehanroengra, Wei Wang 0003 Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee Single-probe traversal optimization for testing of MCM substrate interconnections. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
26Mario R. Casu, Luca Macchiarulo Adaptive Latency-Insensitive Protocols. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF latency-insensitive protocols, interconnections, ICs, wire pipelining
26Arjan Durresi, Gojko Babic, Raj Jain Measurement of ATM Frame Latency. Search on Bibsonomy LCN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF ATM frame latency measurement, MIMO latency, message-in message-out latency, latency metrics, continuous frame technologies, measurement results, switch performance, MIMO aggregation, network element, network interconnections, quality of service, asynchronous transfer mode, MIMO systems, telecommunication networks, QoS parameters, network devices
26Maria Brielmann, Joachim Stroop, Uwe Honekamp, Peter Wältermann Simulation of hybrid mechatronic systems: a case study. Search on Bibsonomy ECBS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF hybrid mechatronic systems, continuous system parts, discrete system parts, car electric windows, extended predicate/transition nets, hardware-in-the-loop simulation, hybrid simulation parallelisation, interconnections, complex systems, DSL, automaton, mechatronics, specification techniques, block diagram, simulation techniques
26V. B. Fyodorov Bit-Parallel Selfrouting Optoelectronic Switching Fabrics for Massively Parallel Wide-Format Data Processing: Principle and Optical Architecture. Search on Bibsonomy ISPAN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Free space optical interconnections, Completely connected networks, Smart pixel arrays, VCSEL technology
26Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. Search on Bibsonomy HPCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
26Sajal K. Das 0001, Sanjoy K. Sen Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories. Search on Bibsonomy IPPS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time
26Andrew B. Kahng, Kei Masuko, Sudhakar Muddu Analytical delay models for VLSI interconnects under ramp input. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections
26Bradly K. Fawcett, J. Watson Reconfigurable Processing With Field Programmable Gate Arrays. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
26Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov Designing an asynchronous pipeline token ring interface. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks
26Sushil Aryal, James S. Meditch Design of a large ATM switch with trunk grouping. Search on Bibsonomy ICCCN The full citation details ... 1995 DBLP  DOI  BibTeX  RDF load throughput value, dense VLSI implementation, large ATM switch with trunk grouping, LAST switch, IBSS, ideal bit by bit self routing switch, delay, topology, throughput, interconnections, communication complexity, modules, circuit complexity, cell loss
26Alexander Dalal, Lavi Lev, Sundari Mitra Design of an efficient power distribution network for the UltraSPARC-I microprocessor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network
26Sven Simon 0001, Ralf Bucher, Josef A. Nossek Retiming of synchronous circuits with variable topology. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits
26C. V. Ramamoorthy, Yutaka Usuda, Atul Prakash 0001, Wei-Tek Tsai The Evolution Support Environment System. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF evolution support environment system, ESE system, integrated support, software architecture configuration, life-cycle configuration, software objects, design, specifications, software development, management, programming environments, interconnections, software components, traceability, code, version control, test cases, semantic information, evolving software system
26Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo Efficient datapath merging for partially reconfigurable architectures. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
26Chittaranjan A. Mandal, R. M. Zimmer A Genetic Algorithm for the Synthesis of Structured Data Paths. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation
26Stuart K. Tewksbury, Lawrence A. Hornak Optical Clock Distribution in Electronic Systems. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
26Debashis Basak, Dhabaleswar K. Panda 0001 Designing Clustered Multiprocessor Systems under Packaging and Technological Advancements. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF k-ary n-cube interconnection, packaging constraints, interconnection networks, parallel architectures, Multiprocessor systems, clustered architectures, hierarchical organization, scalable systems
26Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson LILA: layout generation for iterative logic arrays. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
25Ulf Jönsson, Michael Cantoni, Chung-Yao Kao On structured robustness analysis for feedback interconnections of unstable systems. Search on Bibsonomy CDC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Rami G. Melhem Low Diameter Interconnections for Routing in High-Performance Parallel Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF fixed diameter graphs, low diameter networks, Interconnection networks, directed graphs, circuit switching, deterministic routing
25Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri Yield prediction for 3D capacitive interconnections. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Roberto Navigli, Paola Velardi Structural Semantic Interconnections: A Knowledge-Based Approach to Word Sense Disambiguation. Search on Bibsonomy IEEE Trans. Pattern Anal. Mach. Intell. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Stefan Paal, Reiner Kammüller, Bernd Freisleben Self-Managing Remote Object Interconnections. Search on Bibsonomy DEXA Workshops The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Frédéric Gaffiot, Ian O'Connor Simulation of Electrical and Optical Interconnections for Future VLSI ICs. Search on Bibsonomy International Conference on Computational Science The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Guy Peterson Verification of Device Interface Hardware Interconnections Prior to the Start of Testing. Search on Bibsonomy ITC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
25Antonio Zenteno, Víctor H. Champac, Joan Figueras Detectability Conditions of Full Opens in the Interconnections. Search on Bibsonomy J. Electron. Test. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF logic testing, IDDQ testing, opens, defect modeling
25Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
25Andrea Carmignani, Giuseppe Di Battista, Walter Didimo, Francesco Matera, Maurizio Pizzonia Visualization of the Autonomous Systems Interconnections with HERMES. Search on Bibsonomy GD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
25Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang An Analytical Delay Model for SRAM-Based FPGA Interconnections. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
25Qian Wang, Sotirios G. Ziavras Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. Search on Bibsonomy ISPAN The full citation details ... 1999 DBLP  DOI  BibTeX  RDF communication operations, parallel processing, Interconnection networks
25Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian A distributed BIST technique for diagnosis of MCM interconnections. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25David C. Keezer, K. E. Newman, John S. Davis Improved sensitivity for parallel test of substrate interconnections. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
25Adam Kristof Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
25Shin-ichiro Tago, Shuichi Ueno Optimal Realization of Hypercubes by Three-Dimensional Space-Invariant Optical Interconnections. Search on Bibsonomy ISPAN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
25Chung-Sheng Li, Harold S. Stone, Young Kwark, C. Michael Olsen Fully differential optical interconnections for high-speed digital systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
25Dilip K. Bhavsar Testing Interconnections to Static RAMs. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
25Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen Three-dimensional capacitance computations for VLSI/ULSI interconnections. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
25Zhen-qiu Ning, Patrick M. Dewilde SPIDER: capacitance modelling for VLSI interconnections. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
17Shoaib Kamil 0001, Leonid Oliker, Ali Pinar, John Shalf Communication Requirements and Interconnect Optimization for High-End Scientific Applications. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF performance analysis, topology, Interconnections
17Torsten Hoefler Software and Hardware Techniques for Power-Efficient HPC Networking. Search on Bibsonomy Comput. Sci. Eng. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF power-efficient HPC, interconnections networks, large-scale networks, Green networking
17Olav Lysne, José Miguel Montañana, José Flich, José Duato, Timothy Mark Pinkston, Tor Skeie An Efficient and Deadlock-Free Network Reconfiguration Protocol. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Interconnections (Subsystems), Topology, I/O and Data Communications
17Madeleine Glick Optical Interconnects in Next Generation Data Centers: An End to End View. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF computer networks, optical interconnections, optical switches
17Assaf Shacham, Keren Bergman Building Ultralow-Latency Interconnection Networks Using Photonic Integration. Search on Bibsonomy IEEE Micro The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiple data stream architectures, interconnections, processor architectures, I/O and data communication
17Rodney Van Meter, Kae Nemoto, W. J. Munro Communication Links for Distributed Quantum Computation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Interconnections (Subsystems), Emerging technologies, Emerging technologies, Error-checking, Interconnection architectures
17Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan Lightweight Error Correction Coding for System-Level Interconnects. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Interconnections (subsystems), coding and information theory, error control codes, interconnection architectures, code design, coding tools and techniques
17Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter Leveraging Wire Properties at the Microarchitecture Level. Search on Bibsonomy IEEE Micro The full citation details ... 2006 DBLP  DOI  BibTeX  RDF interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies
17Alessandro Mei, Romeo Rizzi Online Permutation Routing in Partitioned Optical Passive Star Networks. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF partitioned optical passive star network, Optical interconnections, permutation routing
17Juan Rubio 0001, Lizy Kurian John Reducing Server Data Traffic Using a Hierarchical Computation Model. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF I/O interconnections topology, modeling, evaluation, databases, measurement, Distributed architectures, simulation of multiple-processor systems
17Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret Impact of Low-K on Crosstalk. Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Low-k, interconnections, Crosstalk, electromagnetic analysis
17Guoping Liu 0004, Kyungsook Y. Lee, Harry F. Jordan n-Dimensional Processor Arrays with Optical dBuses. Search on Bibsonomy J. Supercomput. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF de Bruijn digraph, wavelength division multiplexing, optical interconnections, processor array, time division multiplexing
17Brian Webb, Ahmed Louri A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF scalability, networks, parallel architectures, hypercubes, wavelength division multiplexing, Optical interconnections, crossbars, multiprocessor interconnection
17Bin Liu, Fabrizio Lombardi, Wei-Kang Huang Testing programmable interconnect systems: an algorithmic approach. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
17Chen-Huan Chiang, Sandeep K. Gupta 0001 BIST TPG for SRAM cluster interconnect testing at board level. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing
17Abby A. Ilumoka Efficient prediction of interconnect crosstalk using neural networks. Search on Bibsonomy ICTAI The full citation details ... 2000 DBLP  DOI  BibTeX  RDF interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration
17Prasasth Palnati, Mario Gerla, Emilio Leonardi Deadlock-free routing in an optical interconnect for high-speed wormhole routing networks. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high-speed wormhole routing networks, Supercomputer SuperNet, two-level hierarchical high-speed network, electronic mesh fabric, WDM optical backbone network, metropolitan area, campus area, backpressure hop-by-hop flow control mechanism, shufflenet multihop virtual topology, physical channels, up/down deadlock free routing scheme, bidirectional shufflenet, optical backbone, multiprocessor interconnection networks, network routing, virtual channels, wavelength division multiplexing, optical interconnections, optical interconnect, deadlock-free routing, deadlock prevention
17I-Shyan Hwang Performance evaluation of a WDMA OIDSM multiprocessors. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF WDMA OIDSM, WDMA, photonic network, reservation requests, coherence level control signals, performance evaluation, performance evaluation, interconnection network, multiprocessor interconnection networks, shared memory multiprocessors, shared memory systems, distributed shared memory, distributed memory systems, wavelength division multiplexing, optical interconnections, optically interconnected, access protocols, media access protocol
17Steven M. P. Yip, Nicholas Bambos Scalable routing schemes for massively parallel processing using reconfigurable optical interconnect. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF scalable routing schemes, reconfigurable optical interconnect, message broadcasting, massively parallel processing system, randomly generated packets, device capabilities, parallel processing, reconfigurable architectures, optical interconnections, message routing, massively parallel processing
17Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura An Optical Bus Computer Cluster with a deferred cache coherence protocol. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage
17Mounir Hamdi, J. Tong, C. W. Kin Fast sorting algorithms on reconfigurable array of processors with optical buses. Search on Bibsonomy ICPADS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
17Lutz J. Micheel, Hans L. Hartnagel Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. Search on Bibsonomy ISMVL The full citation details ... 1996 DBLP  DOI  BibTeX  RDF heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion
17Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi On the diagnosis of programmable interconnect systems: Theory and application. Search on Bibsonomy VTS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections
17Lizy Kurian John VaWiRAM: a variable width random access memory module. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
17Santonu Sarkar, Anupam Basu, Arun K. Majumdar Representation and Synthesis of Interface of a Circuit for its Reuse. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect
17Mounir Hamdi, Yi Pan 0001 Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
17Gregory Gravenstreter, Rami G. Melhem, Donald M. Chiarulli, Steven P. Levitan, James P. Teza The Partitioned Optical Passive Stars (POPS) topology. Search on Bibsonomy IPPS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF optical couplers, Partitioned Optical Passive Stars topology, POPS topology, multiple data channels, all-optical interconnection architecture, multiple nonhierarchical couplers, power budget, control overhead, random communication patterns, performance evaluation, optimization, parallel architectures, optimisation, multiprocessor interconnection networks, configurability, reconfigurable architectures, high performance, optical interconnections, network throughput, large systems, system complexity
17Mike Chou, Jacob K. White 0001 Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics)
17Steven E. Butner, David A. Skirmont Architecture and design of a 40 gigabit per second ATM switch. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF ATM links, buffering scheme, 40 Gbit/s, asynchronous transfer mode, multiprocessor interconnection networks, optical interconnections, ATM switch, optical communication, switch architecture
17Nikolaos G. Bourbakis, Mohammad Mortazavi An efficient building block layout methodology for compact placement. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing
17Tong Liu 0007, Fabrizio Lombardi, José Salinas Diagnosis of interconnects and FPICs using a structured walking-1 approach. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections
17Patrick W. Dowd, James A. Perreault, John C. Chu, David C. Hoffmeister, Dan Crouse LIGHTNING: A Scalable Dynamically Reconfigurable Hierarchical WDM Network for High-Performance Clustering. Search on Bibsonomy HPDC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF scalable dynamically reconfigurable hierarchical WDM network, high-performance clustering, supercomputer interconnection, optical network testbed, distributed shared memory environment, single-hop all-optical communication, n-level hierarchy, highly fault tolerant system behavior, memory interface, optical devices, scalability, parallel processing, reconfigurable architectures, system architecture, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, optical information processing, LIGHTNING, traffic intensities
17Anirudh Devgan, Ronald A. Rohrer Efficient simulation of interconnect and mixed analog-digital circuits in ACES. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
17S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects
17P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya VLSI floorplan generation and area optimization using AND-OR graph search. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
17Dinesh Bhatia, James Haralambides Resource requirements for field programmable interconnection chips. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network
17Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF photonic architectures, optical structures, processor interconnection, single-hop, optical fiber communication, parallel architectures, discrete-event simulation, discrete event simulation, analytic models, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, hierarchical, parallel computer architecture, hierarchical architectures
17Wen-Jing Hsu Fibonacci Cubes-A New Interconnection Technology. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF subgraph embedding, recurrent structures, sparse interconnections, Boolean cube, supergraph, node connectivity, system communication primitives, graph theory, fault-tolerant computing, topology, hypercube, multiprocessorinterconnection networks, interconnection topology, Fibonacci cube
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