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Publication years (Num. hits)
1974-1989 (15) 1990-1993 (16) 1994-1995 (21) 1996-1997 (20) 1998-1999 (32) 2000 (16) 2001 (19) 2002 (28) 2003 (34) 2004 (32) 2005 (36) 2006 (44) 2007 (40) 2008 (31) 2009 (29) 2010 (25) 2011 (26) 2012 (22) 2013 (23) 2014 (18) 2015 (24) 2016 (29) 2017 (32) 2018 (42) 2019 (34) 2020 (34) 2021 (34) 2022 (35) 2023 (52) 2024 (16)
Publication types (Num. hits)
article(312) incollection(1) inproceedings(546)
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Found 861 publication records. Showing 859 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
150Kei-Yong Khoo, Alan N. Willson Jr. Single-transistor transparent-latch clocking. Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
145Masayuki Tsukisaka, Masashi Imai, Takashi Nanya Asynchronous Scan-Latch controller for Low Area Overhead DFT. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
97Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra Latch Susceptibility to Transient Faults and New Hardening Approach. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Static Latch, Hardened Latch, Soft Errors, Transient Faults, Robust Design
91Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan Latch Modeling for Statistical Timing Analysis. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
91Tomohiro Yoshihara, Dai Kobayashi, Haruo Yokota A concurrency control protocol for parallel B-tree structures without latch-coupling for explosively growing digital content. Search on Bibsonomy EDBT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
91Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies. Search on Bibsonomy DSN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
89Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg Latch-to-Latch Timing Rules. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF latch-to-latch timing rules, consecutive latch pairs, multiple skew levels, data propagation delays, multiple clock pulse widths, clock phases, logic design, synchronous systems, combinational logic, propagation delay
83K. Wayne Current Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. Search on Bibsonomy ISMVL The full citation details ... 2000 DBLP  DOI  BibTeX  RDF quaternary, memory, circuit, latch
81Tzu-Yuan Kuo, Jinn-Shyan Wang A low-voltage latch-adder based tree multiplier. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
81Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF architecture, power, temperature, clock gating
75Pong-Fei Lu, Nianzheng Cao, Leon J. Sigal, Pieter Woltgens, Raphael Robertazzi, David F. Heidel A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF pulse latch, low-power, latch
67Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang Pulsed-latch aware placement for timing-integrity optimization. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF pulsed latch, placement, physical design
67Martin Saint-Laurent, Baker Mohammad, Paul Bassett A 65-nm pulsed latch with a single clocked transistor. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking
67Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain Solving the latch mapping problem in an industrial setting. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF latch mapping, combinational equivalence checking
67Jacob Savir Reduced Latch Count Shift Registers. Search on Bibsonomy J. Electron. Test. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF shift register latch, scan register, shifting clocks, STUMPS architecture, LSSD
64Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray Concurrent timing optimization of latch-based digital systems. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
64Sanjoy Kumar Dey, Swapna Banerjee An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
62Srivathsan Krishnamohan, Nihar R. Mahapatra Analysis and design of soft-error hardened latches. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multiple-upset, single-event, soft errors, single-event upset, latch, radiation hardening
59Flavio Carbognani, Luca Henzen Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF flipflops, low power design, clock, digital circuits, adiabatic
59Shweta Srivastava, Jaijeet S. Roychowdhury Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
59Saihua Lin, Huazhong Yang, Rong Luo High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
59Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu Static statistical timing analysis for latch-based pipeline designs. Search on Bibsonomy ICCAD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
59Victor V. Zyuban, Stephen V. Kosonocky Low power integrated scan-retention mechanism. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
59Samy Makar, Edward J. McCluskey Checking experiments to test latches. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
56Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. Search on Bibsonomy Formal Methods Syst. Des. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF phase abstraction, automatic abstraction, CTL model checking, level-sensitive latch, bisimulation, model reduction
56Shaz Qadeer, Robert K. Brayton, Vigyan Singhal Latch Redundancy Removal Without Global Reset. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF global reset assumption, latch redundancy, safe replacement, delayed replacement, Finite state machine, core, strongly connected components
54Mahdi Fazeli, Seyed Ghassem Miremadi A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
54Mustafa Emre Karagozler, Jason Campbell, Gary K. Fedder, Seth Copen Goldstein, Michael Philetus Weller, Byung Woo Yoon Electrostatic latching for inter-module adhesion, power transfer, and communication in modular robots. Search on Bibsonomy IROS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Seongmoo Heo, Ronny Krashinsky, Krste Asanovic Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Shweta Srivastava, Jaijeet S. Roychowdhury Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
48Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra Novel Transient Fault Hardened Static Latch. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
48Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
48Seongmoo Heo, Ronny Krashinsky, Krste Asanovic Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. Search on Bibsonomy ARVLSI The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
48Victor V. Zyuban, Peter M. Kogge Application of STD to latch-power estimation. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
48Paul Day, John V. Woods Investigation into micropipeline latch design styles. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
46Amit M. Sheth, Jacob Savir Scan Latch Design for Test Applications. Search on Bibsonomy J. Electron. Test. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF shift register latch, scan design, hardware overhead, LSSD
46Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF latch-based design, time borrowing, timing budgeting, static timing analysis, Cycle stealing
43Dana May Latch NSF Announcements: Theory of Computing Program. Search on Bibsonomy SIGACT News The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
43Dana May Latch NSF Announcements: Theory of Computing Program. Search on Bibsonomy SIGACT News The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
43Dana May Latch NSF Announcements: Theory of Computing Program. Search on Bibsonomy SIGACT News The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
43Dana May Latch, Ron Sigal A Local Termination Property for Term Rewriting Systems. Search on Bibsonomy RTA The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
43R. Bumby, E. Cooper, D. Latch Interactive Computation of Homology of Finite Partially Ordered Sets. Search on Bibsonomy SIAM J. Comput. The full citation details ... 1975 DBLP  DOI  BibTeX  RDF
43HeungJun Jeon, Yong-Bin Kim A low-offset high-speed double-tail dual-rail dynamic latched comparator. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clocked comparator, dynamic latched comparator, low-offset low-power high-speed, voltage sense amplifier (sa)
43Kim T. Le, Dong Hyun Baik, Kewal K. Saluja Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Karen J. Cassidy, Kenny C. Gross, Amir Malekpour Advanced Pattern Recognition for Detection of Complex Software Aging Phenomena in Online Transaction Processing Servers. Search on Bibsonomy DSN The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi Automatic state space decomposition for approximate FSM traversal based on circuit analysis. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
40Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Electrostatic discharge (ESD), electrical overstress (EOS), LVTSCR, latch-up, burn-in
38Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Shweta Srivastava, Jaijeet S. Roychowdhury Rapid and accurate latch characterization via direct Newton solution of setup/hold times. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Holly Pekau, Lee Hartley, James W. Haslett A re-configurable high-speed CMOS track and latch comparator with rail-to-rail input for IF digitization [software radio receiver applications]. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
38R. Singh, N. Bhat An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
38Li Ding 0002, Pinaki Mazumder, N. Srinivas A dual-rail static edge-triggered latch. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
38Claude Arm, Jean-Marc Masgonty, Christian Piguet Double-Latch Clocking Scheme for Low-Power I.P. Cores. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
38Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. Search on Bibsonomy ASYNC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann Optimal latch mapping and retiming within a tree. Search on Bibsonomy ICCAD The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
35Yoichi Sasaki 0001, Kazuteru Namba, Hideo Ito Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Masking circuit, Pass transistor, Schmitt trigger circuit, Soft error, Latch
35Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto An Experimental Study on Latch Up Failure of CMOS LSI. Search on Bibsonomy SSIRI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF latch up, CMOS LSI
35Jacob Savir The Bidirectional Double Latch (BDDL). Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD
33Zhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process. Search on Bibsonomy DAC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
33Naoki Fujieda, Shuichi Ichikawa A latch-latch composition of metastability-based true random number generator for Xilinx FPGAs. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
33Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi DIRT latch: A novel low cost double node upset tolerant latch. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
33Vijay Savani, N. M. Devashrayee Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology. Search on Bibsonomy VDAT The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
33Michael Heer, Krzysztof Domanski, Kai Esmark, Ulrich Glaser, Dionyz Pogany, Erich Gornik, Wolfgang Stadler Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
33Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli Power dissipation in one-latch and two-latch double edge triggered flip-flops. Search on Bibsonomy ICECS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj 3D configuration caching for 2D FPGAs. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF field programmable gate array (fpga), reconfigurable computing, 3d integration, configuration caching
32Saihua Lin, Huazhong Yang, Rong Luo A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
32Min-Lun Chuang, Chun-Yao Wang Synthesis of reversible sequential elements. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF sequential elements, sequential circuits, Reversible logic
32Min-Lun Chuang, Chun-Yao Wang Synthesis of Reversible Sequential Elements. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Jun Zhou, David Kinniment, Gordon Russell 0002, Alexandre Yakovlev A Robust Synchronizer. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Soumitra Bose, Amit Nandi Schematic array models for associative and non-associative memory circuits. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Payam Heydari, Ravindran Mohanavelu Design of ultrahigh-speed low-voltage CMOS CML buffers and latches. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Soumitra Bose, Amit Nandi Extraction of Schematic Array Models for Memory Circuits. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Payam Heydari, Ravindran Mohanavelu Design of ultra high-speed CMOS CML buffers and latches. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Tsung-Chu Huang, Kuen-Jong Lee Reduction of power consumption in scan-based circuits during testapplication by an input control technique. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Nobuo Funabiki, Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska A Global Routing Technique for Wave-Steering Design Methodology. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32David L. Harris, Mark Horowitz, Dean Liu Timing analysis including clock skew. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Tsung-Chu Huang, Kuen-Jong Lee An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF ATPG, VLSI testing, Power Minimization, Low-power Test, Full-scan
32Prashant Saxena, Peichen Pan, C. L. Liu 0001 The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Jacob Savir On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
32Weiwei Mao, Michael D. Ciletti Reducing correlation to improve coverage of delay faults in scan-path design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
32Srinivas Devadas Approaches to Multi-level Sequential Logic Synthesis. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
29S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
29Charles E. Molnar, Ian W. Jones Simple Circuits that Work for Complicated Reasons. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF MUTEX, Delay measurement technique, Latch control circuit, Charlie Box, Asynchronous, FIFO, Arbiter, Micropipeline
29Masayuki Tsukisaka, Takashi Nanya A testable design for asynchronous fine-grain pipeline circuits. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
29Octavian-Dumitru Mocanu, Joan Oliver Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF hamming SEC code, latch-up, memory system, single event upset, built-in current sensor
29Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa A unified approach in the analysis of latches and flip-flops for low-power systems. Search on Bibsonomy ISLPED The full citation details ... 1998 DBLP  DOI  BibTeX  RDF master-slave latch, optimization, timing, flip-flop, power measurement
29Jacob Savir Module level weighted random patterns. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF module level self-test architecture, pseudorandom pattern generator, universal weighting generator, scan latch, near-optimal weight, signal pins, weight control function, self-test time, logic testing, probability, integrated circuit testing, automatic testing, multivalued logic circuits, boundary scan testing, scan test, weighted random patterns, multiple input signature register
29Branka Medved Rogina, Bozidar Vojnovic Metastability evaluation method by propagation delay distribution measurement. Search on Bibsonomy Asian Test Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
29Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia Fast discrete function evaluation using decision diagrams. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
27 Latch Coupling. Search on Bibsonomy Encyclopedia of Database Systems The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
27Chen-Hsuan Lin, Chun-Yao Wang Dependent latch identification in the reachable state space. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
27Chuan Lin 0002, Hai Zhou 0001 Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Kun Young Chung, Sandeep K. Gupta 0001 Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. Search on Bibsonomy VTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Omid Mirmotahari, Yngvar Berg A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic. Search on Bibsonomy ISMVL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Manan Syal, Michael S. Hsiao, Sreejit Chakravarty Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. Search on Bibsonomy ITC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Massimo Alioto, Gaetano Palumbo Design of MUX, XOR and D-latch SCL gates. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
27Marek Wróblewski, Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, Wilhelm Pieper, Josef A. Nossek A power efficient register file architecture using master latch sharing. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
27Peter Dahlgren, Paul Dickinson, Ishwar Parulkar Latch Divergency In Microprocessor Failure Analysis. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
27Kun Young Chung, Sandeep K. Gupta 0001 Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. Search on Bibsonomy ITC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
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