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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1980 occurrences of 1232 keywords
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Results
Found 10676 publication records. Showing 9714 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
91 | Tia Newhall, Daniel Amato, Alexandr Pshenichkin |
Reliable adaptable Network RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: Proceedings of the 2008 IEEE International Conference on Cluster Computing, 29 September - 1 October 2008, Tsukuba, Japan, pp. 2-12, 2008, IEEE Computer Society, 978-1-4244-2640-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
83 | Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali |
Testing embedded RAM modules in SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 228, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
81 | Manoj Franklin, Kewal K. Saluja |
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9), pp. 1081-1087, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
78 | Miklós Ajtai |
Oblivious RAMs without cryptogrpahic assumptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 42nd ACM Symposium on Theory of Computing, STOC 2010, Cambridge, Massachusetts, USA, 5-8 June 2010, pp. 181-190, 2010, ACM, 978-1-4503-0050-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
RAM, oblivious |
76 | Juraj Wiedermann |
Normalizing and Accelerating RAM Computations and the Problem of Reasonable Space Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 17th International Colloquium, ICALP90, Warwick University, England, UK, July 16-20, 1990, Proceedings, pp. 125-138, 1990, Springer, 3-540-52826-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
68 | Aviad Zuck, Ohad Barzilay, Sivan Toledo |
NANDFS: a flexible flash file system for RAM-constrained systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 9th ACM & IEEE International conference on Embedded software, EMSOFT 2009, Grenoble, France, October 12-16, 2009, pp. 285-294, 2009, ACM, 978-1-60558-627-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
RAM constrained, page mapping, file system, flash, NAND flash |
68 | In Hwan Doh, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh |
Exploiting non-volatile RAM to enhance flash file system performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 7th ACM & IEEE International conference on Embedded software, EMSOFT 2007, September 30 - October 3, 2007, Salzburg, Austria, pp. 164-173, 2007, ACM, 978-1-59593-825-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-volatile RAM, metadata, file system, flash memory, experimental evaluation |
68 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-Based FPGAs: Testing the Embedded RAM Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 159-167, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, RAM, iterative testing |
68 | Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem |
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 230-241, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique |
68 | Li Xiao 0001, Xiaodong Zhang 0001, Stefan A. Kubricht |
Incorporating Job Migration and Network RAM to Share Cluster Memory Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the Ninth IEEE International Symposium on High Performance Distributed Computing, HPDC'00, Pittsburgh, Pennsylvania, USA, August 1-4, 2000., pp. 71-78, 2000, IEEE Computer Society, 0-7695-0783-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
62 | Alejandro López-Ortiz, Mehdi Mirzazadeh, Mohammad Ali Safari, M. Hossein Sheikh Attar |
Fast string sorting using order-preserving compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Exp. Algorithmics ![In: ACM J. Exp. Algorithmics 10, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Order-preserving compression, unit-cost RAM, sorting, word-RAM |
62 | Swapan Kumar Ray |
Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 575-587, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Content Addressable Memory (CAM), associative store, Associative Memory (AM), pipelined CAM, Content-To-Address Memory (CTAM), pipelined CTAM, Binary Search Processor (BSP), Pipelined Binary Search Processor (PBSP), pipelined binary search, Binary Search Pipeline (BSPL), pipelined search processor, pipelined search engine |
60 | Torben Hagerup |
Sorting and Searching on the Word RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 98, 15th Annual Symposium on Theoretical Aspects of Computer Science, Paris, France, February 25-27, 1998, Proceedings, pp. 366-398, 1998, Springer, 3-540-64230-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
word-level parallelism, exponential range reduction, fusion trees, exponential search trees, AC', searching, Sorting, network flow, multiplication, dictionaries, tries, word RAM, conservative algorithms |
60 | Naoto Takahashi, Atsushi Kameda, Masahito Yamamoto, Azuma Ohuchi |
Aqueous Computing with DNA Hairpin-Based RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DNA ![In: DNA Computing, 10th International Workshop on DNA Computing, DNA 10, Milan, Italy, June 7-10, 2004, Revised Selected Papers, pp. 355-364, 2004, Springer, 3-540-26174-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
60 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-based FPGA's: testing the LUT/RAM modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1102-1111, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
53 | An-I Andy Wang, Geoffrey H. Kuenning, Peter L. Reiher, Gerald J. Popek |
The Conquest file system: Better performance through a disk/persistent-RAM hybrid design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Storage ![In: ACM Trans. Storage 2(3), pp. 309-348, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Persistent RAM, performance measurement, file systems, storage management |
52 | Nathan Cooprider, John Regehr |
Offline compression for on-chip ram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, San Diego, California, USA, June 10-13, 2007, pp. 363-372, 2007, ACM, 978-1-59593-633-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sensor networks, static analysis, data compression, embedded software, TinyOS, memory optimization |
52 | Raphael V. Carneiro, Stiven Schwanz Dias, Dijalma Fardin, Hallysson Oliveira, Artur S. d'Avila Garcez, Alberto Ferreira de Souza |
Improving VG-RAM Neural Networks Performance Using Knowledge Correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (1) ![In: Neural Information Processing, 13th International Conference, ICONIP 2006, Hong Kong, China, October 3-6, 2006, Proceedings, Part I, pp. 427-436, 2006, Springer, 3-540-46479-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
52 | Lei Yang 0017, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar |
CRAMES: compressed RAM for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 93-98, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded system, compression, memory |
52 | Mohammed Sayed, Wael M. Badawy |
A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 328-332, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
52 | Etienne Grandjean, J. M. Robson |
RAM with Compact Memory: A Realistic and Robust Model of Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSL ![In: Computer Science Logic, 4th Workshop, CSL '90, Heidelberg, Germany, October 1-5, 1990, Proceedings, pp. 195-233, 1990, Springer, 3-540-54487-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
46 | Giuseppe Della Penna, Benedetto Intrigila, Enrico Tronci, Marisa Venturini Zilli |
Exploiting Transition Locality in the Disk Based Mur phi Verifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 202-219, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Manoj Franklin, Kewal K. Saluja |
Hypergraph Coloring and Reconfigured RAM Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(6), pp. 725-736, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area |
45 | Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002 |
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 1-6, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
STT-RAM, emerging memory, spintronic |
45 | Ping Yang, Shu Dai, Xiuhua Wu, Yong Yang |
The Hardware Research of Dual-port RAM for Main-spare CPU in Rural Power Terminal System of Power Quantity Collection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCTA ![In: Computer And Computing Technologies In Agriculture, Volume I, First IFIP TC 12 International Conference on Computer and Computing Technologies in Agriculture (CCTA 2007), Wuyishan, China, August 18-20, 2007, pp. 433-440, 2007, Springer, 978-0-387-77250-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-port RAM, main-spare CPU, terminal of power quantity collection, data exchange, parallel communication |
45 | Michel Renovell, Joan Figueras, Yervant Zorian |
Test of RAM-based FPGA: methodology and application to the interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 230-237, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect |
45 | Alberto Ferreira de Souza, Claudine Badue, Felipe Pedroni, Elias Oliveira, Stiven Schwanz Dias, Hallysson Oliveira, Sotério Ferreira de Souza |
Face Recognition with VG-RAM Weightless Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (1) ![In: Artificial Neural Networks - ICANN 2008 , 18th International Conference, Prague, Czech Republic, September 3-6, 2008, Proceedings, Part I, pp. 951-960, 2008, Springer, 978-3-540-87535-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Rui Chu, Nong Xiao, Xicheng Lu |
A Resource Information Management System for RAM Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing, Sixth International Conference on Grid and Cooperative Computing, GCC 2007, August 16-18, 2007, Urumchi, Xinjiang, China, Proceedings, pp. 181-188, 2007, IEEE Computer Society, 0-7695-2871-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Vassil Roussev, Golden G. Richard III, Daniel Tingstrom |
dRamDisk: efficient RAM sharing on a commodity cluster. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the 25th IEEE International Performance Computing and Communications Conference, IPCCC 2006, April 10-12, 2006, Phoenix, Arizona, USA, 2006, IEEE, 1-4244-0198-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J. Cohen, Steve Merrill, Ramesh Durairaj, Paul Daspit, Inder Monga, Sumit Naiksatam, Silvia M. Figueira, David Gutierrez, Doan B. Hoang, Franco Travostino |
DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 4th IEEE/ACM International Symposium on Cluster Computing and the Grid (CCGrid 2004), April 19-22, 2004, Chicago, Illinois, USA, pp. 762-764, 2004, IEEE Computer Society, 0-7803-8430-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
45 | Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas |
Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 805-812, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
45 | Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie |
Computational RAM: Implementing Processors in Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(1), pp. 32-41, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Manoj Sachdev |
Reducing the CMOS RAM test complexity withIDDQ and voltage testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 191-202, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fault model, faults, defects, March test, I DDQ testing |
45 | Jop F. Sibeyn, Tim J. Harris |
Exploiting Locality in LT-RAM Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SWAT ![In: Algorithm Theory - SWAT '94, 4th Scandinavian Workshop on Algorithm Theory, Aarhus, Denmark, July 6-8, 1994, Proceedings, pp. 338-349, 1994, Springer, 3-540-58218-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
39 | Betty Prince |
Embedded non-volatile memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 9, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM |
39 | John Oleszkiewicz, Li Xiao 0001, Yunhao Liu 0001 |
Effectively Utilizing Global Cluster Memory for Large Data-Intensive Parallel Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(1), pp. 66-77, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
network RAM, simulation, cluster, scheduling, peer-to-peer, Parallel programs |
39 | Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao |
An energy efficient TLB design methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 351-356, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Godson-I, embedded processor design, single-port RAM, energy efficient, TLB, low-power consumption |
39 | Kuo-Su Hsiao, Chung-Ho Chen |
An efficient wakeup design for energy reduction in high-performance superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 353-360, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
issue window, wakeup logic, low power, high performance |
39 | Li Xiao 0001, Songqing Chen, Xiaodong Zhang 0001 |
Adaptive Memory Allocations in Clusters to Handle Unexpectedly Large Data-Intensive Jobs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(7), pp. 577-592, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Yiming Hu, Tycho Nightingale, Qing Yang 0001 |
RAPID-Cache-A Reliable and Inexpensive Write Cache for High Performance Storage Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 13(3), pp. 290-307, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fault-tolerance, performance, reliability, storage systems, disks |
37 | Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili |
An energy efficient cache design using spin torque transfer (STT) RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 389-394, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
(STT)RAM, memory technologies, cache design |
37 | Hong-Hee Lee, Hoang M. Nguyen |
Implementation of Induction Motor Control System Using Matrix Converter Based on CAN Network and Dual-Port RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (2) ![In: Emerging Intelligent Computing Technology and Applications. With Aspects of Artificial Intelligence, 5th International Conference on Intelligent Computing, ICIC 2009, Ulsan, South Korea, September 16-19, 2009, Proceedings, pp. 1067-1074, 2009, Springer, 978-3-642-04019-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CAN network, dual-port RAM, Matrix converter |
37 | Chie Dou, Shing-Jeh Jiang, Kuo-Cheng Leu |
A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 111-115, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
CAM/RAM integration, buffer manager, content addressable memory, IP router |
37 | Marc D. Riedel, Janusz Rajski |
Fault coverage analysis of RAM test algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 227-234, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms |
37 | Puneet Sawhney, Haroon Rasheed |
Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 191-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators |
37 | Xuejun Yang, Nathan Cooprider, John Regehr |
Eliminating the call stack to save RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 60-69, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
stack liveness, sensor networks, compiler optimization, embedded software, memory allocation, memory optimizations |
37 | Claudine Badue, Felipe Pedroni, Alberto Ferreira de Souza |
Multi-label Text Categorization Using VG-RAM Weightless Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBRN ![In: 10th Brazilian Symposium on Neural Networks (SBRN 2008), Salvador, Bahia, Brazil, October 26-30, 2008, pp. 105-110, 2008, IEEE Computer Society, 978-0-7695-3361-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy |
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), pp. 278-290, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Rui Chu, Jiancong Xie, Nong Xiao, Xicheng Lu |
RAM Grid Middleware for Autonomic Cooperative Caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing, Sixth International Conference on Grid and Cooperative Computing, GCC 2007, August 16-18, 2007, Urumchi, Xinjiang, China, Proceedings, pp. 791-798, 2007, IEEE Computer Society, 0-7695-2871-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Min-Sik Jin, Min-Soo Jung |
A Study on Fast JCVM by Moving Object from EEPROM to RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China, pp. 84-88, 2005, IEEE Computer Society, 0-7695-2346-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Ran Mendelson, Mikkel Thorup, Uri Zwick |
Meldable RAM priority queues and minimum directed spanning trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Fifteenth Annual ACM-SIAM Symposium on Discrete Algorithms, SODA 2004, New Orleans, Louisiana, USA, January 11-14, 2004, pp. 40-48, 2004, SIAM, 0-89871-558-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
37 | Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli |
Integrating RAM and Disk Based Verification within the Mur-phi Verifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 277-282, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott |
An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 475-, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Nils Maltesson, David Naccache, Elena Trichina, Christophe Tymen |
Applet Verification Strategiesfor RAM-Constrained Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2002, 5th International Conference Seoul, Korea, November 28-29, 2002, Revised Papers, pp. 118-137, 2002, Springer, 3-540-00716-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Stamatios V. Kartalopoulos |
An associative RAM-based CAM and its application to broadband communications systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 9(5), pp. 1036-1041, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Jerry J. Cupal |
Initializing RAM-based logarithmic processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 4(2-3), pp. 243-252, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
37 | Nader H. Bshouty |
Lower Bounds for the Complexity of Functions in a Realistic RAM Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISTCS ![In: Theory of Computing and Systems, ISTCS'92, Israel Symposium, Haifa, Israel, May 1992, pp. 12-23, 1992, Springer, 3-540-55553-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
37 | Ashok K. Goel 0002, Apurva Kalia |
Simulation of ram-based asynchronous sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 23rd Annual Simulation Symposium (ANSS-23 1990), Nashville, Tennessee, USA, 1990, pp. 123-126, 1990, IEEE Computer Society, 0-8186-2067-6. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
32 | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu |
Simulation-Based Test Algorithm Generation for Random Access Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 291-296, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RAM fault simulation, March test algorithm, Cocktail-March test algorithms, semiconductor memories, RAM testing |
32 | Yuejian Wu, Sanjay Gupta |
Built-In Self-Test for Multi-Port RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 398-403, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST) |
32 | Kewal K. Saluja |
On-chip testing of random access memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(4), pp. 367-376, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing |
32 | Bowen Alpern, Larry Carter, Ephraim Feig |
Uniform Memory Hierarchies ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 31st Annual Symposium on Foundations of Computer Science, St. Louis, Missouri, USA, October 22-24, 1990, Volume II, pp. 600-608, 1990, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
RAM complexity, uniform memory hierarchy, computer memory, FFT programs, parallelism, RAM, parsimonious, random-access-machine |
32 | Vason P. Srini |
Fault Location in a Semiconductor Random-Access Memory Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 27(4), pp. 349-358, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
Cables, controlled register, RAM chip, RAM unit, fault model, fault location, test sequence |
31 | Ilya Baran, Erik D. Demaine, Mihai Patrascu |
Subquadratic Algorithms for 3SUM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 50(4), pp. 584-596, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3SUM, Randomization, Word RAM |
31 | Anne M. P. Canuto, Gareth Howells 0001, Michael C. Fairhurst |
An Investigation of the Effects of Variable Vigilance within the RePART Neuro-Fuzzy Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 29(4), pp. 317-334, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
reward/punishment parameter, RePART, fuzzy multi-layer perceptron, radial RAM, variable vigilance parameter, fuzzy ARTMAP, handwritten numeral recognition |
31 | Lizyamma Kurian, Daniel Brewer, Eugene John |
Design of a highly reconfigurable interconnect for array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 321-325, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies |
31 | Anand Raghunathan, Pranav Ashar, Sharad Malik |
Test generation for cyclic combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 104-109, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults |
31 | Xi Chen, Prateek Gangwal, Daji Qiao |
Practical Rate Adaptation in Mobile Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PerCom ![In: Seventh Annual IEEE International Conference on Pervasive Computing and Communications, PerCom 2009, 9-13 March 2009, Galveston, TX, USA, pp. 1-10, 2009, IEEE Computer Society, 978-1-4244-3304-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Jörg Kienzle, Wisam Al Abed, Jacques Klein |
Aspect-oriented multi-view modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AOSD ![In: Proceedings of the 8th International Conference on Aspect-Oriented Software Development, AOSD 2009, Charlottesville, Virginia, USA, March 2-6, 2009, pp. 87-98, 2009, ACM, 978-1-60558-442-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
aspect dependencies, binding, class diagram, sequence diagram, aspect-oriented modeling, state diagram, instantiation |
31 | Ann M. Bouchard, Gordon C. Osbourn |
Dynamic self-assembly in living systems as computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nat. Comput. ![In: Nat. Comput. 5(4), pp. 321-362, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
biological information processing, microtubule, motor protein, protein network, unary number, algorithm, computation, computing, information, self-assembly, stochastic, random access machine |
31 | Li-Pin Chang, Tei-Wei Kuo |
Efficient management for large-scale flash-memory storage systems with resource conservation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Storage ![In: ACM Trans. Storage 1(4), pp. 381-418, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded systems, memory management, Flash memory, storage systems, consumer electronics, portable devices |
31 | Seung-Joon Seok, Seok-Min Hong, Sung-Hyuck Lee, Chul-Hee Kang |
A Dynamic Marking Scheme of Assured Service for Alleviating Unfairness among Service Level Agreements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MMNS ![In: Management of Multimedia on the Internet, 5th IFIP/IEEE International Conference on Management of Multimedia Networks and Services, MMNS 2002, Santa Barbara, CA, USA, October 6-9, 2002, Proceedings, pp. 224-236, 2002, Springer, 3-540-44271-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Seung-Joon Seok, Sung-Hyuck Lee, Seok-Min Hong, Chul-Hee Kang |
Unfairness of Assured Service and a Rate Adaptive Marking Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QofIS ![In: From QoS Provisioning to QoS Charging, Third COST 263 International Workshop on Quality of Future Internet Services, QofIS 2002, and Second International Workshop on Internet Charging and QoS Technologies, ICQT 2002, Zurich, Switzerland, October 16-18, 2002, Proceedings, pp. 47-56, 2002, Springer, 3-540-44356-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Paolo Gai, Giuseppe Lipari, Marco Di Natale |
Minimizing Memory Utilization of Real-Time Task Sets in Single and Multi-Processor Systems-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 22nd IEEE Real-Time Systems Symposium (RTSS 2001), London, UK, 2-6 December 2001, pp. 73-83, 2001, IEEE Computer Society, 0-7695-1420-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik |
Computational power of pipelined memory hierarchies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: Proceedings of the Thirteenth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 2001, Heraklion, Crete Island, Greece, July 4-6, 2001, pp. 144-152, 2001, ACM, 1-58113-409-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
31 | Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley |
A Multi-Level Memory System Architecture for High-Performance DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 408-413, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Yiming Hu, Qing Yang 0001, Tycho Nightingale |
RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 204-213, 1999, IEEE Computer Society, 0-7695-0004-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Oded Goldreich 0001, Rafail Ostrovsky |
Software Protection and Simulation on Oblivious RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 43(3), pp. 431-473, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
simulation of random access machines, software protection, pseudorandom functions |
31 | Xiao-ping Ling, Hideharu Amano |
Performance evaluation of WASMII: a data driven computer on a virtual hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '93, Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, June 14-17, 1993, Proceedings, pp. 610-621, 1993, Springer, 3-540-56891-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
31 | Rafail Ostrovsky |
An Efficient Software Protection Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CRYPTO ![In: Advances in Cryptology - CRYPTO '89, 9th Annual International Cryptology Conference, Santa Barbara, California, USA, August 20-24, 1989, Proceedings, pp. 610-611, 1989, Springer, 3-540-97317-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Tia Newhall, Douglas Woos |
Incorporating Network RAM and Flash into Fast Backing Store for Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2011 IEEE International Conference on Cluster Computing (CLUSTER), Austin, TX, USA, September 26-30, 2011, pp. 121-129, 2011, IEEE Computer Society, 978-1-4577-1355-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Network RAM, cluster backing store, flash |
29 | Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho |
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 290-291, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
DVD-RAM, SATA, WSR, CMOS, optical storage |
29 | Kanad Chakraborty, Pinaki Mazumder |
New March Tests for Multiport RAM Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(4), pp. 389-395, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults |
29 | B. Suresh, Biswadeep Chaterjee, R. Harinath |
Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 512-517, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability |
29 | Trevor G. Clarkson, Denise Gorse, John G. Taylor, C. K. Ng |
Learning Probabilistic RAM Nets Using VLSI Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(12), pp. 1552-1561, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
synaptic noise, global rewards, global penalties, local penalties, RAM nets, VLSI structures, learning probabilistic RAMs, local reinforcement rules, local rewards, serial updating, VLSI, neural nets, backpropagation, backpropagation, weights, content-addressable storage, stochastic search, learning rule |
29 | René David, Antoine Fuentes |
Fault Diagnosis of RAM's from Random Testing Experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(2), pp. 220-229, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
random testing experiments, fault diagnosis, simulation results, fault location, random-access storage, RAM |
29 | Eric Regener |
A Transition Sequence Generator for RAM Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(3), pp. 362-368, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
transition sequence generator, RAM fault detection, n-bit CMOS memories, test address sequence, ordered pair, next-state generator, integrated circuit testing, logic circuit, CMOS integrated circuits, random-access storage, integrated memory circuits |
29 | Petra De Jong, Ad J. van de Goor |
Test Pattern Generation for API Faults in RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1426-1428, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
API faults, near optimal WRITE sequence, integrated circuit testing, BIST, automatic testing, fault location, test pattern generation, Hamiltonian paths, random-access storage, RAM, integrated memory circuits, pattern-sensitive faults |
29 | Thomas E. Fuja, Chris Heegard |
Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(11), pp. 996-1000, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
hard defects, RAM's, row/column replacement, reliability, redundancy, Error-control coding, yield improvement |
29 | Shalhav Zohar |
A Realization of the RAM Digital Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(10), pp. 1048-1053, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
hardware digital filter, negative radix application, RAM digital filter, real-time digital filter, Digital filter |
29 | Shijie Zhang, Jiong Yang 0001 |
RAM: Randomized Approximate Graph Mining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSDBM ![In: Scientific and Statistical Database Management, 20th International Conference, SSDBM 2008, Hong Kong, China, July 9-11, 2008, Proceedings, pp. 187-203, 2008, Springer, 978-3-540-69476-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Rui Chu, Nong Xiao, Lei Chen 0002, Xicheng Lu |
A push-based prefetching for cooperative caching RAM Grid. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 13th International Conference on Parallel and Distributed Systems, ICPADS 2007, Hsinchu, Taiwan, December 5-7, 2007, pp. 1-8, 2007, IEEE Computer Society, 978-1-4244-1889-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache |
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 199-200, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy |
Power-aware RAM mapping for FPGA embedded memory blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 189-198, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
embedded memory block, FPGA, dynamic power |
29 | Dongming Peng, Mi Lu |
Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(1), pp. 58-74, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Ghenadie Bodean, Diana Bodean, A. Labunetz |
New Schemes for Self-Testing RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 858-859, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Subhasis Bhattacharjee, Dhiraj K. Pradhan |
LPRAM: a novel low-power high-performance RAM design with testability and scalability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5), pp. 637-651, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Gaoxiang Ouyang, Xiaoli Li 0002, Xinping Guan, Zhiqiang Zhang, Xiuling Zhang, Ruxu Du |
Ram Velocity Control in Plastic Injection Molding Machines with Neural Network Learning Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2004, International Symposium on Neural Networks, Dalian, China, August 19-21, 2004, Proceedings, Part II, pp. 169-174, 2004, Springer, 3-540-22843-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Rui-fang Liu, Changsheng Xie, Zhi-hu Tan, Qing Yang 0001 |
A New Hierarchy Cache Scheme Using RAM and Pagefile. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 515-526, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Silvia M. Figueira, Sumit Naiksatam, Howard J. Cohen, Doug Cutrell, Paul Daspit, David Gutierrez, Doan B. Hoang, Tal Lavian, Joe Mambretti, Steve Merrill, Franco Travostino |
DWDM-RAM: enabling Grid services with dynamic optical networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 4th IEEE/ACM International Symposium on Cluster Computing and the Grid (CCGrid 2004), April 19-22, 2004, Chicago, Illinois, USA, pp. 707-714, 2004, IEEE Computer Society, 0-7803-8430-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
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