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The graphs summarize 1980 occurrences of 1232 keywords

Results
Found 10676 publication records. Showing 9714 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
91Tia Newhall, Daniel Amato, Alexandr Pshenichkin Reliable adaptable Network RAM. Search on Bibsonomy CLUSTER The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
83Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali Testing embedded RAM modules in SRAM-based FPGAs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
81Manoj Franklin, Kewal K. Saluja Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
78Miklós Ajtai Oblivious RAMs without cryptogrpahic assumptions. Search on Bibsonomy STOC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF RAM, oblivious
76Juraj Wiedermann Normalizing and Accelerating RAM Computations and the Problem of Reasonable Space Measures. Search on Bibsonomy ICALP The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
68Aviad Zuck, Ohad Barzilay, Sivan Toledo NANDFS: a flexible flash file system for RAM-constrained systems. Search on Bibsonomy EMSOFT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF RAM constrained, page mapping, file system, flash, NAND flash
68In Hwan Doh, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh Exploiting non-volatile RAM to enhance flash file system performance. Search on Bibsonomy EMSOFT The full citation details ... 2007 DBLP  DOI  BibTeX  RDF non-volatile RAM, metadata, file system, flash memory, experimental evaluation
68Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian SRAM-Based FPGAs: Testing the Embedded RAM Modules. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF FPGA, test, ATPG, RAM, iterative testing
68Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
68Li Xiao 0001, Xiaodong Zhang 0001, Stefan A. Kubricht Incorporating Job Migration and Network RAM to Share Cluster Memory Resources. Search on Bibsonomy HPDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
62Alejandro López-Ortiz, Mehdi Mirzazadeh, Mohammad Ali Safari, M. Hossein Sheikh Attar Fast string sorting using order-preserving compression. Search on Bibsonomy ACM J. Exp. Algorithmics The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Order-preserving compression, unit-cost RAM, sorting, word-RAM
62Swapan Kumar Ray Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Content Addressable Memory (CAM), associative store, Associative Memory (AM), pipelined CAM, Content-To-Address Memory (CTAM), pipelined CTAM, Binary Search Processor (BSP), Pipelined Binary Search Processor (PBSP), pipelined binary search, Binary Search Pipeline (BSPL), pipelined search processor, pipelined search engine
60Torben Hagerup Sorting and Searching on the Word RAM. Search on Bibsonomy STACS The full citation details ... 1998 DBLP  DOI  BibTeX  RDF word-level parallelism, exponential range reduction, fusion trees, exponential search trees, AC', searching, Sorting, network flow, multiplication, dictionaries, tries, word RAM, conservative algorithms
60Naoto Takahashi, Atsushi Kameda, Masahito Yamamoto, Azuma Ohuchi Aqueous Computing with DNA Hairpin-Based RAM. Search on Bibsonomy DNA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian SRAM-based FPGA's: testing the LUT/RAM modules. Search on Bibsonomy ITC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
53An-I Andy Wang, Geoffrey H. Kuenning, Peter L. Reiher, Gerald J. Popek The Conquest file system: Better performance through a disk/persistent-RAM hybrid design. Search on Bibsonomy ACM Trans. Storage The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Persistent RAM, performance measurement, file systems, storage management
52Nathan Cooprider, John Regehr Offline compression for on-chip ram. Search on Bibsonomy PLDI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF sensor networks, static analysis, data compression, embedded software, TinyOS, memory optimization
52Raphael V. Carneiro, Stiven Schwanz Dias, Dijalma Fardin, Hallysson Oliveira, Artur S. d'Avila Garcez, Alberto Ferreira de Souza Improving VG-RAM Neural Networks Performance Using Knowledge Correlation. Search on Bibsonomy ICONIP (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Lei Yang 0017, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar CRAMES: compressed RAM for embedded systems. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF embedded system, compression, memory
52Mohammed Sayed, Wael M. Badawy A New Class of Computational RAM Architectures for Real-Time MPEG-4 Applications. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52Etienne Grandjean, J. M. Robson RAM with Compact Memory: A Realistic and Robust Model of Computation. Search on Bibsonomy CSL The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
46Giuseppe Della Penna, Benedetto Intrigila, Enrico Tronci, Marisa Venturini Zilli Exploiting Transition Locality in the Disk Based Mur phi Verifier. Search on Bibsonomy FMCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Manoj Franklin, Kewal K. Saluja Hypergraph Coloring and Reconfigured RAM Testing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF hypergraph coloring, reconfigured RAM testing, RAM decoders, critical path lengths, memory chips, physical neighborhood pattern sensitive faults, reconfigured DRAMs, decoder faults, computational complexity, logic testing, redundancy, reconfigurable architectures, stuck-at faults, graph colouring, random-access storage, integrated memory circuits, test lengths, test algorithms, DRAM chips, silicon area
45Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002 Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF STT-RAM, emerging memory, spintronic
45Ping Yang, Shu Dai, Xiuhua Wu, Yong Yang The Hardware Research of Dual-port RAM for Main-spare CPU in Rural Power Terminal System of Power Quantity Collection. Search on Bibsonomy CCTA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dual-port RAM, main-spare CPU, terminal of power quantity collection, data exchange, parallel communication
45Michel Renovell, Joan Figueras, Yervant Zorian Test of RAM-based FPGA: methodology and application to the interconnect. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF RAM-based FPGA, manufacturing test procedure, user test procedure, orthogonal test configuration, diagonal-1 test configuration, diagonal-2 test configuration, field programmable gate arrays, interconnect
45Alberto Ferreira de Souza, Claudine Badue, Felipe Pedroni, Elias Oliveira, Stiven Schwanz Dias, Hallysson Oliveira, Sotério Ferreira de Souza Face Recognition with VG-RAM Weightless Neural Networks. Search on Bibsonomy ICANN (1) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Rui Chu, Nong Xiao, Xicheng Lu A Resource Information Management System for RAM Grid. Search on Bibsonomy GCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Vassil Roussev, Golden G. Richard III, Daniel Tingstrom dRamDisk: efficient RAM sharing on a commodity cluster. Search on Bibsonomy IPCCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Tal Lavian, Joe Mambretti, Doug Cutrell, Howard J. Cohen, Steve Merrill, Ramesh Durairaj, Paul Daspit, Inder Monga, Sumit Naiksatam, Silvia M. Figueira, David Gutierrez, Doan B. Hoang, Franco Travostino DWDM-RAM: a data intensive Grid service architecture enabled by dynamic optical networks. Search on Bibsonomy CCGRID The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Duncan G. Elliott, Michael Stumm, W. Martin Snelgrove, Christian Cojocaru, Robert McKenzie Computational RAM: Implementing Processors in Memory. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
45Manoj Sachdev Reducing the CMOS RAM test complexity withIDDQ and voltage testing. Search on Bibsonomy J. Electron. Test. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fault model, faults, defects, March test, I DDQ testing
45Jop F. Sibeyn, Tim J. Harris Exploiting Locality in LT-RAM Computations. Search on Bibsonomy SWAT The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
39Betty Prince Embedded non-volatile memories. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM
39John Oleszkiewicz, Li Xiao 0001, Yunhao Liu 0001 Effectively Utilizing Global Cluster Memory for Large Data-Intensive Parallel Programs. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF network RAM, simulation, cluster, scheduling, peer-to-peer, Parallel programs
39Dongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao An energy efficient TLB design methodology. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Godson-I, embedded processor design, single-port RAM, energy efficient, TLB, low-power consumption
39Kuo-Su Hsiao, Chung-Ho Chen An efficient wakeup design for energy reduction in high-performance superscalar processors. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF issue window, wakeup logic, low power, high performance
39Li Xiao 0001, Songqing Chen, Xiaodong Zhang 0001 Adaptive Memory Allocations in Clusters to Handle Unexpectedly Large Data-Intensive Jobs. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Yiming Hu, Tycho Nightingale, Qing Yang 0001 RAPID-Cache-A Reliable and Inexpensive Write Cache for High Performance Storage Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF fault-tolerance, performance, reliability, storage systems, disks
37Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili An energy efficient cache design using spin torque transfer (STT) RAM. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF (STT)RAM, memory technologies, cache design
37Hong-Hee Lee, Hoang M. Nguyen Implementation of Induction Motor Control System Using Matrix Converter Based on CAN Network and Dual-Port RAM. Search on Bibsonomy ICIC (2) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CAN network, dual-port RAM, Matrix converter
37Chie Dou, Shing-Jeh Jiang, Kuo-Cheng Leu A Novel CAM/RAM Based Buffer Manager for Next Generation IP Routers. Search on Bibsonomy DELTA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF CAM/RAM integration, buffer manager, content addressable memory, IP router
37Marc D. Riedel, Janusz Rajski Fault coverage analysis of RAM test algorithms. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms
37Puneet Sawhney, Haroon Rasheed Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
37Xuejun Yang, Nathan Cooprider, John Regehr Eliminating the call stack to save RAM. Search on Bibsonomy LCTES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF stack liveness, sensor networks, compiler optimization, embedded software, memory allocation, memory optimizations
37Claudine Badue, Felipe Pedroni, Alberto Ferreira de Souza Multi-label Text Categorization Using VG-RAM Weightless Neural Networks. Search on Bibsonomy SBRN The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Rui Chu, Jiancong Xie, Nong Xiao, Xicheng Lu RAM Grid Middleware for Autonomic Cooperative Caching. Search on Bibsonomy GCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
37Min-Sik Jin, Min-Soo Jung A Study on Fast JCVM by Moving Object from EEPROM to RAM. Search on Bibsonomy RTCSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Ran Mendelson, Mikkel Thorup, Uri Zwick Meldable RAM priority queues and minimum directed spanning trees. Search on Bibsonomy SODA The full citation details ... 2004 DBLP  BibTeX  RDF
37Giuseppe Della Penna, Benedetto Intrigila, Igor Melatti, Enrico Tronci, Marisa Venturini Zilli Integrating RAM and Disk Based Verification within the Mur-phi Verifier. Search on Bibsonomy CHARME The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture. Search on Bibsonomy DFT The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Nils Maltesson, David Naccache, Elena Trichina, Christophe Tymen Applet Verification Strategiesfor RAM-Constrained Devices. Search on Bibsonomy ICISC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
37Stamatios V. Kartalopoulos An associative RAM-based CAM and its application to broadband communications systems. Search on Bibsonomy IEEE Trans. Neural Networks The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Jerry J. Cupal Initializing RAM-based logarithmic processors. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
37Nader H. Bshouty Lower Bounds for the Complexity of Functions in a Realistic RAM Model. Search on Bibsonomy ISTCS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
37Ashok K. Goel 0002, Apurva Kalia Simulation of ram-based asynchronous sequential circuits. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
32Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu Simulation-Based Test Algorithm Generation for Random Access Memories. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF RAM fault simulation, March test algorithm, Cocktail-March test algorithms, semiconductor memories, RAM testing
32Yuejian Wu, Sanjay Gupta Built-In Self-Test for Multi-Port RAMs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Random Access Memory (RAM) test, multi-port RAM test, Built-In Self-Test (BIST)
32Kewal K. Saluja On-chip testing of random access memories. Search on Bibsonomy J. Electron. Test. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF BIST RAM, reconfigured random access memories, test parallelism, Built-In Self-Test, pattern sensitive faults, test architectures, RAM testing
32Bowen Alpern, Larry Carter, Ephraim Feig Uniform Memory Hierarchies Search on Bibsonomy FOCS The full citation details ... 1990 DBLP  DOI  BibTeX  RDF RAM complexity, uniform memory hierarchy, computer memory, FFT programs, parallelism, RAM, parsimonious, random-access-machine
32Vason P. Srini Fault Location in a Semiconductor Random-Access Memory Unit. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1978 DBLP  DOI  BibTeX  RDF Cables, controlled register, RAM chip, RAM unit, fault model, fault location, test sequence
31Ilya Baran, Erik D. Demaine, Mihai Patrascu Subquadratic Algorithms for 3SUM. Search on Bibsonomy Algorithmica The full citation details ... 2008 DBLP  DOI  BibTeX  RDF 3SUM, Randomization, Word RAM
31Anne M. P. Canuto, Gareth Howells 0001, Michael C. Fairhurst An Investigation of the Effects of Variable Vigilance within the RePART Neuro-Fuzzy Network. Search on Bibsonomy J. Intell. Robotic Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF reward/punishment parameter, RePART, fuzzy multi-layer perceptron, radial RAM, variable vigilance parameter, fuzzy ARTMAP, handwritten numeral recognition
31Lizyamma Kurian, Daniel Brewer, Eugene John Design of a highly reconfigurable interconnect for array processors. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF reconfigurable interconnect, static-RAM programming technology, faulty elements, fault-tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, network topology, reconfigurable architectures, array processors, interconnection topologies, mesh topologies
31Anand Raghunathan, Pranav Ashar, Sharad Malik Test generation for cyclic combinational circuits. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cyclic combinational circuits, bus structures, single-stuck-at fault test pattern, test generation problem, program RAM, fault diagnosis, logic testing, integrated circuit testing, network topology, combinational circuits, automatic testing, fault coverage, test pattern generators, formal analysis, data paths, testing algorithm, combinational logic circuits, untestable faults
31Xi Chen, Prateek Gangwal, Daji Qiao Practical Rate Adaptation in Mobile Environments. Search on Bibsonomy PerCom The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
31Jörg Kienzle, Wisam Al Abed, Jacques Klein Aspect-oriented multi-view modeling. Search on Bibsonomy AOSD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF aspect dependencies, binding, class diagram, sequence diagram, aspect-oriented modeling, state diagram, instantiation
31Ann M. Bouchard, Gordon C. Osbourn Dynamic self-assembly in living systems as computation. Search on Bibsonomy Nat. Comput. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF biological information processing, microtubule, motor protein, protein network, unary number, algorithm, computation, computing, information, self-assembly, stochastic, random access machine
31Li-Pin Chang, Tei-Wei Kuo Efficient management for large-scale flash-memory storage systems with resource conservation. Search on Bibsonomy ACM Trans. Storage The full citation details ... 2005 DBLP  DOI  BibTeX  RDF embedded systems, memory management, Flash memory, storage systems, consumer electronics, portable devices
31Seung-Joon Seok, Seok-Min Hong, Sung-Hyuck Lee, Chul-Hee Kang A Dynamic Marking Scheme of Assured Service for Alleviating Unfairness among Service Level Agreements. Search on Bibsonomy MMNS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Seung-Joon Seok, Sung-Hyuck Lee, Seok-Min Hong, Chul-Hee Kang Unfairness of Assured Service and a Rate Adaptive Marking Strategy. Search on Bibsonomy QofIS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
31Paolo Gai, Giuseppe Lipari, Marco Di Natale Minimizing Memory Utilization of Real-Time Task Sets in Single and Multi-Processor Systems-on-a-Chip. Search on Bibsonomy RTSS The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
31Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik Computational power of pipelined memory hierarchies. Search on Bibsonomy SPAA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
31Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley A Multi-Level Memory System Architecture for High-Performance DSP Applications. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
31Yiming Hu, Qing Yang 0001, Tycho Nightingale RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems. Search on Bibsonomy HPCA The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
31Oded Goldreich 0001, Rafail Ostrovsky Software Protection and Simulation on Oblivious RAMs. Search on Bibsonomy J. ACM The full citation details ... 1996 DBLP  DOI  BibTeX  RDF simulation of random access machines, software protection, pseudorandom functions
31Xiao-ping Ling, Hideharu Amano Performance evaluation of WASMII: a data driven computer on a virtual hardware. Search on Bibsonomy PARLE The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
31Rafail Ostrovsky An Efficient Software Protection Scheme. Search on Bibsonomy CRYPTO The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
29Tia Newhall, Douglas Woos Incorporating Network RAM and Flash into Fast Backing Store for Clusters. Search on Bibsonomy CLUSTER The full citation details ... 2011 DBLP  DOI  BibTeX  RDF Network RAM, cluster backing store, flash
29Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh, Hong-Ching Chen, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang, Benjamin Chiu, Alex Ho A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF DVD-RAM, SATA, WSR, CMOS, optical storage
29Kanad Chakraborty, Pinaki Mazumder New March Tests for Multiport RAM Devices. Search on Bibsonomy J. Electron. Test. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF multi-port RAM, simplex and duplex coupling faults, concurrent coupling faults
29B. Suresh, Biswadeep Chaterjee, R. Harinath Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability
29Trevor G. Clarkson, Denise Gorse, John G. Taylor, C. K. Ng Learning Probabilistic RAM Nets Using VLSI Structures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF synaptic noise, global rewards, global penalties, local penalties, RAM nets, VLSI structures, learning probabilistic RAMs, local reinforcement rules, local rewards, serial updating, VLSI, neural nets, backpropagation, backpropagation, weights, content-addressable storage, stochastic search, learning rule
29René David, Antoine Fuentes Fault Diagnosis of RAM's from Random Testing Experiments. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF random testing experiments, fault diagnosis, simulation results, fault location, random-access storage, RAM
29Eric Regener A Transition Sequence Generator for RAM Fault Detection. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF transition sequence generator, RAM fault detection, n-bit CMOS memories, test address sequence, ordered pair, next-state generator, integrated circuit testing, logic circuit, CMOS integrated circuits, random-access storage, integrated memory circuits
29Petra De Jong, Ad J. van de Goor Test Pattern Generation for API Faults in RAM. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF API faults, near optimal WRITE sequence, integrated circuit testing, BIST, automatic testing, fault location, test pattern generation, Hamiltonian paths, random-access storage, RAM, integrated memory circuits, pattern-sensitive faults
29Thomas E. Fuja, Chris Heegard Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1986 DBLP  DOI  BibTeX  RDF hard defects, RAM's, row/column replacement, reliability, redundancy, Error-control coding, yield improvement
29Shalhav Zohar A Realization of the RAM Digital Filter. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1976 DBLP  DOI  BibTeX  RDF hardware digital filter, negative radix application, RAM digital filter, real-time digital filter, Digital filter
29Shijie Zhang, Jiong Yang 0001 RAM: Randomized Approximate Graph Mining. Search on Bibsonomy SSDBM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
29Rui Chu, Nong Xiao, Lei Chen 0002, Xicheng Lu A push-based prefetching for cooperative caching RAM Grid. Search on Bibsonomy ICPADS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy Power-aware RAM mapping for FPGA embedded memory blocks. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF embedded memory block, FPGA, dynamic power
29Dongming Peng, Mi Lu Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Ghenadie Bodean, Diana Bodean, A. Labunetz New Schemes for Self-Testing RAM. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Subhasis Bhattacharjee, Dhiraj K. Pradhan LPRAM: a novel low-power high-performance RAM design with testability and scalability. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Gaoxiang Ouyang, Xiaoli Li 0002, Xinping Guan, Zhiqiang Zhang, Xiuling Zhang, Ruxu Du Ram Velocity Control in Plastic Injection Molding Machines with Neural Network Learning Control. Search on Bibsonomy ISNN (2) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Rui-fang Liu, Changsheng Xie, Zhi-hu Tan, Qing Yang 0001 A New Hierarchy Cache Scheme Using RAM and Pagefile. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
29Silvia M. Figueira, Sumit Naiksatam, Howard J. Cohen, Doug Cutrell, Paul Daspit, David Gutierrez, Doan B. Hoang, Tal Lavian, Joe Mambretti, Steve Merrill, Franco Travostino DWDM-RAM: enabling Grid services with dynamic optical networks. Search on Bibsonomy CCGRID The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
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