Search results for "VDD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
161	Yan Lin 0001, Lei He 0001	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	programmable-Vdd, time slack, FPGA, low power
139	Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, low power, power efficient, dual-Vdd, dual-Vt
128	Yan Lin 0001, Fei Li 0003, Lei He 0001	Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
128	Yan Lin 0001, Lei He 0001	Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
128	Fei Li 0003, Yan Lin 0001, Lei He 0001	Vdd programmability to reduce FPGA interconnect power.	ICCAD	2004	DBLP DOI BibTeX RDF
120	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
106	Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	A dual-VDD boosted pulsed bus technique for low power and low leakage operation.	ISLPED	2006	DBLP DOI BibTeX RDF	pulsed bus, leakage, repeaters, Dual-VDD
106	Fei Li 0003, Yan Lin 0001, Lei He 0001	FPGA power reduction using configurable dual-Vdd.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, low power, configurable, power efficient, dual-Vdd
97	Takayasu Sakurai	Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control.	ISQED	2000	DBLP DOI BibTeX RDF	VDD, VTH, VLSI, Low-power, CMOS
87	Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001	Low-power technology mapping for FPGA architectures with dual supply voltages.	FPGA	2004	DBLP DOI BibTeX RDF	low-power FPGA, technology mapping, dual supply voltage
87	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
85	Himanshu Kaul, Dennis Sylvester	A novel buffer circuit for energy efficient signaling in dual-VDD systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	on-chip signaling, low-power, repeaters, dual-VDD
85	Sarvesh H. Kulkarni, Dennis Sylvester	Power distribution techniques for dual VDD circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
85	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.	DAC	2006	DBLP DOI BibTeX RDF	FPGA, low power, retiming
85	Yu Ching Chang, King Ho Tam, Lei He 0001	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
85	King Ho Tam, Lei He 0001	Power optimal dual-Vdd buffered tree considering buffer stations and blockages.	DAC	2005	DBLP DOI BibTeX RDF	low power, buffer insertion, detail routing
85	Dongku Kang, Mark C. Johnson, Kaushik Roy 0001	Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.	ICCD	2003	DBLP DOI BibTeX RDF
76	Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
76	Fei Li 0003, Yan Lin 0001, Lei He 0001	Field Programmability of Supply Voltages for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
76	Yan Lin 0001, Fei Li 0003, Lei He 0001	Circuits and architectures for field programmable gate array with configurable supply voltage.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
74	Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001	Fast dual-vdd buffering based on interconnect prediction and sampling.	SLIP	2007	DBLP DOI BibTeX RDF	routing, low power, interconnect, buffer insertion, dual-Vdd
74	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
74	Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	A Dual-VDD Low Power FPGA Architecture.	FPL	2004	DBLP DOI BibTeX RDF
65	Howard Chen 0001, Daniel L. Ostapko	Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.	PATMOS	2004	DBLP DOI BibTeX RDF
63	Yong Zhan, Sachin S. Sapatnekar	Automated module assignment in stacked-Vdd designs for high-efficiency power delivery.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF
63	Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan	Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Low power, retiming
63	S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur	Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block.	VLSI Design	2008	DBLP DOI BibTeX RDF
63	Yan Lin 0001, Lei He 0001	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.	DATE	2007	DBLP DOI BibTeX RDF
63	Aswath Oruganti, Nagarajan Ranganathan	Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation.	VLSI Design	2006	DBLP DOI BibTeX RDF
63	Tadahiro Kuroda	Optimization and control of VDD and VTH for low-power, high-speed CMOS design.	ICCAD	2002	DBLP DOI BibTeX RDF
63	Hiroshi Kawaguchi 0001, Gang Zhang, Seongsoo Lee, Takayasu Sakurai	An LSI for VDD-hopping and MPEG4 system based on the chip.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
61	Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester	A new algorithm for improved VDD assignment in low power dual VDD systems.	ISLPED	2004	DBLP DOI BibTeX RDF	ECVS, dual VDD design, low power design algorithms, CVS, level converters
54	Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini	Automatic synthesis of near-threshold circuits with fine-grained performance tunability.	ISLPED	2010	DBLP DOI BibTeX RDF	near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
54	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
54	Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim	Yield-driven near-threshold SRAM design.	ICCAD	2007	DBLP DOI BibTeX RDF
54	Deming Chen, Jason Cong, Junjuan Xu	Optimal simultaneous module and multivoltage assignment for low power.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Data path generation, functional unit binding, level conversion, scheduling, high-level synthesis, low power design, power optimization, multiple voltage
54	Deming Chen, Jason Cong, Junjuan Xu	Optimal module and voltage assignment for low-power.	ASP-DAC	2005	DBLP DOI BibTeX RDF
52	Stephen Bijansky, Sae Kyu Lee, Adnan Aziz	TuneLogic: Post-silicon tuning of dual-Vdd designs.	ISQED	2009	DBLP DOI BibTeX RDF
52	Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar	Module assignment for pin-limited designs under the stacked-Vdd paradigm.	ICCAD	2007	DBLP DOI BibTeX RDF
52	Yan Lin 0001, Yu Hu 0002, Lei He 0001, Vijay Raghunat	An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.	ISLPED	2006	DBLP DOI BibTeX RDF	time slack, FPGA, low power
52	Hari Ananthan, Chris H. Kim, Kaushik Roy 0001	Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.	ISLPED	2004	DBLP DOI BibTeX RDF	forward body bias, junction leakage, sub-threshold leakage, process variations
52	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.	DAC	2004	DBLP DOI BibTeX RDF	optimization, power dissipation, multiple voltages
52	Kaushik Roy 0001, Liqiong Wei, Zhanping Chen	Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
44	Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
43	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
43	Chun Yu Cheng, Ka Nang Leung, Yi Ki Sun, Pui Ying Or	Design of a Low-Voltage CMOS Charge Pump.	DELTA	2008	DBLP DOI BibTeX RDF	efficiency, Charge pump
43	Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy 0001, Chaitali Chakrabarti	Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.	ICCAD	2007	DBLP DOI BibTeX RDF
43	Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.	ISLPED	2007	DBLP DOI BibTeX RDF	signal slope, interconnect, gate delay, subthreshold operation
43	Laura Frigerio, Fabio Salice	RAM-Based Fault Tolerant State Machines for FPGAs.	DFT	2007	DBLP DOI BibTeX RDF
43	Chunjie Duan, Sunil P. Khatri	Computing during supply voltage switching in DVS enabled real-time processors.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Jen-Wei Yang, Po-Tsang Huang, Wei Hwang	On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology.	APCCAS	2006	DBLP DOI BibTeX RDF
43	D. Barros Júnior, Marcial Jesús Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas 0001, João Paulo Teixeira 0001	Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	intermittent faults modeling and simulation, digital SoC, EMI/EMC standard compliance, delay fault simulation, power supply voltage transients, fault tolerance
43	David Fitrio, Jugdutt Singh, Aleksandar Stojcevski	Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
43	Man Lung Mui, Kaustav Banerjee, Amit Mehrotra	Power Supply Optimization in sub-130 nm Leakage Dominant Technologies .	ISQED	2004	DBLP DOI BibTeX RDF
43	Chin-Chih Chang, Jason Cong	Pseudopin assignment with crosstalk noise control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
43	Haluk Konuk, F. Joel Ferguson, Tracy Larrabee	Charge-based fault simulation for CMOS network breaks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
42	José Pineda de Gyvez, Guido Gronthoud, Rashid Amine	Multi-VDD Testing for Analog Circuits.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	VDD, ramp, test, analog, IDDQ
41	Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo	CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
41	H. Oshiyama, Toshihiro Matsuda, K. Suzuki, Hideyuki Iwata, Takashi Ohzone	A VDD independent temperature sensor circuit with scaled CMOS process.	ASP-DAC	2009	DBLP DOI BibTeX RDF
41	Soman Purushothaman	A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD.	EIT	2008	DBLP DOI BibTeX RDF
41	Bruce Tseng, Hung-Ming Chen	Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.	ISPD	2008	DBLP DOI BibTeX RDF	voltage island architecture, low power, buffer insertion
41	Stephen Bijansky, Adnan Aziz	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, delay, process variation, yield, tuning
41	Hsiang-Hui Huang, Ching-Hwa Cheng	Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit.	VTS	2007	DBLP DOI BibTeX RDF
41	Mongkol Ekpanyapong, Sung Kyu Lim	Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization.	ISPD	2006	DBLP DOI BibTeX RDF	supply and threshold voltage scaling, low power design, retiming
41	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.	DATE	2004	DBLP DOI BibTeX RDF
41	Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo	Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels.	ISQED	2004	DBLP DOI BibTeX RDF
39	Dharmaray Nedalgi, Saroja V. Siddamal	Differential receiver with 2 × VDD input signals using 1 × VDD devices.	Integr.	2022	DBLP DOI BibTeX RDF
39	Liang Wen, Yuejun Zhang, Xiaoyang Zeng	Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
39	Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei	Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
39	Ming-Dou Ker, Po-Yen Chiu	Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
39	Yongtao Geng, Dongsheng Ma 0001	Design of reliable 2×VDD and 3×VDD series-parallel charge pumps in nanoscale CMOS.	ISCAS	2013	DBLP DOI BibTeX RDF
39	Po-Yen Chiu, Ming-Dou Ker	Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology.	SoCC	2013	DBLP DOI BibTeX RDF
39	Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai	12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.	ISLPED	2011	DBLP BibTeX RDF
39	Chua-Chin Wang, Chia-Hao Hsu, Yi-Cheng Liu	A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
39	Wen-An Tsou, Wen-Shen Wuen, Kuei-Ann Wen	A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with Vdd/AM and Vdd /PM Compensations in EER System.	PACCS	2009	DBLP DOI BibTeX RDF
39	Canh Quang Tran, Hiroshi Kawaguchi 0001, Takayasu Sakurai	Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
39	Célia Fonseca Guerra, Jan-Willem Handgraaf, Evert Jan Baerends, Friedrich Matthias Bickelhaupt	Voronoi deformation density (VDD) charges: Assessment of the Mulliken, Bader, Hirshfeld, Weinhold, and VDD methods for charge analysis.	J. Comput. Chem.	2004	DBLP DOI BibTeX RDF
33	Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet	Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC.	NOCS	2008	DBLP DOI BibTeX RDF	Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS
33	Sherif A. Tawfik, Volkan Kursun	Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.	ISLPED	2007	DBLP DOI BibTeX RDF	dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
33	John Wei, Chris Rowen	Implementing low-power configurable processors: practical options and tradeoffs.	DAC	2005	DBLP DOI BibTeX RDF	PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power
33	Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal	Xetal-Pro: an ultra-low energy and high throughput SIMD processor.	DAC	2010	DBLP DOI BibTeX RDF	Xetal-Pro, hybrid memory system, SIMD, low-energy
33	Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun	Power switch characterization for fine-grained dynamic voltage scaling.	ICCD	2008	DBLP DOI BibTeX RDF
33	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
33	Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura	Simultaneous optimization of memory configuration and code allocation for low power embedded systems.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	code allocation, low power design, on-chip memory
33	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.	ISQED	2008	DBLP DOI BibTeX RDF
33	Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar	Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation.	ISQED	2008	DBLP DOI BibTeX RDF	DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant
33	Lerong Cheng, Fei Li 0003, Yan Lin 0001, Phoebe Wong, Lei He 0001	Device and Architecture Cooptimization for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
33	Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Enhancing the Tolerance to Power-Supply Instability in Digital Circuits.	ISVLSI	2007	DBLP DOI BibTeX RDF
33	Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel	Voltage- and ABB-island optimization in high level synthesis.	ISLPED	2007	DBLP DOI BibTeX RDF	adaptive body biasing, process variation, leakage, voltage islands
33	Flavio Bertini 0002, D. Davide Lamanna, Roberto Baldoni	Virtual Distro Dispatcher: A Costless Distributed Virtual Environment from Trashware.	ISPA	2007	DBLP DOI BibTeX RDF	Trashware, LTSP, Clustering, Virtualization, User Mode Linux
33	Christian Piguet, Christian Schuster, Jean-Luc Nagel	Static and Dynamic Power Reduction by Architecture Selection.	PATMOS	2006	DBLP DOI BibTeX RDF
33	Jun Zhou, David Kinniment, Gordon Russell 0002, Alexandre Yakovlev	A Robust Synchronizer.	ISVLSI	2006	DBLP DOI BibTeX RDF
33	Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu	Optimality study of resource binding with multi-Vdds.	DAC	2006	DBLP DOI BibTeX RDF	low power design, behavioral synthesis, resource binding
33	Lerong Cheng, Phoebe Wong, Fei Li 0003, Yan Lin 0001, Lei He 0001	Device and architecture co-optimization for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	Psim, Ptrace, powergating, FPGA, low power
33	Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung	Leakage Reduction techniques in a 0.13um SRAM Cell.	VLSI Design	2004	DBLP DOI BibTeX RDF
33	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	Theoretical and practical limits of dynamic voltage scaling.	DAC	2004	DBLP DOI BibTeX RDF	minimum energy point, dynamic voltage scaling
33	Rajamohana Hegde, Naresh R. Shanbhag	Toward achieving energy efficiency in presence of deep submicron noise.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
33	Manish Goel, Naresh R. Shanbhag	Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
33	Atila Alvandpour, Per Larsson-Edefors, Christer Svensson	Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	short-circuit current, power consumption, power estimation
33	Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell	CMOS IC reliability indicators and burn-in economics.	ITC	1998	DBLP DOI BibTeX RDF