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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 303 occurrences of 173 keywords
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Results
Found 495 publication records. Showing 495 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
161 | Yan Lin 0001, Lei He 0001 |
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 720-725, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
programmable-Vdd, time slack, FPGA, low power |
139 | Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong |
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 42-50, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, low power, power efficient, dual-Vdd, dual-Vt |
128 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 199-207, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd |
128 | Yan Lin 0001, Lei He 0001 |
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2023-2034, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
128 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Vdd programmability to reduce FPGA interconnect power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 760-765, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
120 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 273-274, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
106 | Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka |
A dual-VDD boosted pulsed bus technique for low power and low leakage operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 73-78, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pulsed bus, leakage, repeaters, Dual-VDD |
106 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
FPGA power reduction using configurable dual-Vdd. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 735-740, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, low power, configurable, power efficient, dual-Vdd |
97 | Takayasu Sakurai |
Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 417-424, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VDD, VTH, VLSI, Low-power, CMOS |
87 | Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001 |
Low-power technology mapping for FPGA architectures with dual supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 109-117, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
low-power FPGA, technology mapping, dual supply voltage |
87 | Deming Chen, Jason Cong |
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 70-73, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
circuit clustering, low-power FPGA, dual supply voltage |
85 | Himanshu Kaul, Dennis Sylvester |
A novel buffer circuit for energy efficient signaling in dual-VDD systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 462-467, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
on-chip signaling, low-power, repeaters, dual-VDD |
85 | Sarvesh H. Kulkarni, Dennis Sylvester |
Power distribution techniques for dual VDD circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 838-843, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
85 | Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan |
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 478-483, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, low power, retiming |
85 | Yu Ching Chang, King Ho Tam, Lei He 0001 |
Power-optimal repeater insertion considering Vdd and Vth as design freedoms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 137-142, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, buffer insertion |
85 | King Ho Tam, Lei He 0001 |
Power optimal dual-Vdd buffered tree considering buffer stations and blockages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 497-502, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, buffer insertion, detail routing |
85 | Dongku Kang, Mark C. Johnson, Kaushik Roy 0001 |
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 412-418, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
76 | Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang |
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 39-44, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd |
76 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Field Programmability of Supply Voltages for FPGA Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4), pp. 752-764, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
76 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Circuits and architectures for field programmable gate array with configurable supply voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(9), pp. 1035-1047, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
74 | Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001 |
Fast dual-vdd buffering based on interconnect prediction and sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 95-102, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
routing, low power, interconnect, buffer insertion, dual-Vdd |
74 | Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal |
A high-level clustering algorithm targeting dual Vdd FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 57:1-57:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power |
74 | Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan |
A Dual-VDD Low Power FPGA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 145-157, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
65 | Howard Chen 0001, Daniel L. Ostapko |
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 809-818, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
63 | Yong Zhan, Sachin S. Sapatnekar |
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(4), pp. 18:1-18:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
63 | Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan |
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 30:1-30:29, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, Low power, retiming |
63 | S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur |
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 509-514, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
63 | Yan Lin 0001, Lei He 0001 |
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 636-641, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
63 | Aswath Oruganti, Nagarajan Ranganathan |
Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 766-769, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
63 | Tadahiro Kuroda |
Optimization and control of VDD and VTH for low-power, high-speed CMOS design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 28-34, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
63 | Hiroshi Kawaguchi 0001, Gang Zhang, Seongsoo Lee, Takayasu Sakurai |
An LSI for VDD-hopping and MPEG4 system based on the chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 918-921, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
61 | Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester |
A new algorithm for improved VDD assignment in low power dual VDD systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 200-205, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ECVS, dual VDD design, low power design algorithms, CVS, level converters |
54 | Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini |
Automatic synthesis of near-threshold circuits with fine-grained performance tunability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 401-406, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold |
54 | Insup Shin, Seungwhun Paik, Youngsoo Shin |
Register allocation for high-level synthesis using dual supply voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 937-942, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, high-level synthesis, register allocation, dual supply voltage |
54 | Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim |
Yield-driven near-threshold SRAM design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 660-666, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Deming Chen, Jason Cong, Junjuan Xu |
Optimal simultaneous module and multivoltage assignment for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(2), pp. 362-386, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Data path generation, functional unit binding, level conversion, scheduling, high-level synthesis, low power design, power optimization, multiple voltage |
54 | Deming Chen, Jason Cong, Junjuan Xu |
Optimal module and voltage assignment for low-power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 850-855, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Stephen Bijansky, Sae Kyu Lee, Adnan Aziz |
TuneLogic: Post-silicon tuning of dual-Vdd designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 394-400, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
52 | Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar |
Module assignment for pin-limited designs under the stacked-Vdd paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 656-659, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Yan Lin 0001, Yu Hu 0002, Lei He 0001, Vijay Raghunat |
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 168-173, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
time slack, FPGA, low power |
52 | Hari Ananthan, Chris H. Kim, Kaushik Roy 0001 |
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 8-13, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
forward body bias, junction leakage, sub-threshold leakage, process variations |
52 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 783-787, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, power dissipation, multiple voltages |
52 | Kaushik Roy 0001, Liqiong Wei, Zhanping Chen |
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 366-370, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
44 | Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara |
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 529-533, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate |
43 | Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 34-37, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Chun Yu Cheng, Ka Nang Leung, Yi Ki Sun, Pui Ying Or |
Design of a Low-Voltage CMOS Charge Pump. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 342-345, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
efficiency, Charge pump |
43 | Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy 0001, Chaitali Chakrabarti |
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 199-204, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001 |
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 387-390, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
signal slope, interconnect, gate delay, subthreshold operation |
43 | Laura Frigerio, Fabio Salice |
RAM-Based Fault Tolerant State Machines for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 312-320, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Chunjie Duan, Sunil P. Khatri |
Computing during supply voltage switching in DVS enabled real-time processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Jen-Wei Yang, Po-Tsang Huang, Wei Hwang |
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 666-669, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | D. Barros Júnior, Marcial Jesús Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas 0001, João Paulo Teixeira 0001 |
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(4), pp. 349-363, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
intermittent faults modeling and simulation, digital SoC, EMI/EMC standard compliance, delay fault simulation, power supply voltage transients, fault tolerance |
43 | David Fitrio, Jugdutt Singh, Aleksandar Stojcevski |
Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 52-64, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Man Lung Mui, Kaustav Banerjee, Amit Mehrotra |
Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 409-414, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
43 | Chin-Chih Chang, Jason Cong |
Pseudopin assignment with crosstalk noise control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 598-611, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Haluk Konuk, F. Joel Ferguson, Tracy Larrabee |
Charge-based fault simulation for CMOS network breaks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), pp. 1555-1567, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
42 | José Pineda de Gyvez, Guido Gronthoud, Rashid Amine |
Multi-VDD Testing for Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(3), pp. 311-322, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VDD, ramp, test, analog, IDDQ |
41 | Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo |
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 93-94, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | H. Oshiyama, Toshihiro Matsuda, K. Suzuki, Hideyuki Iwata, Takashi Ohzone |
A VDD independent temperature sensor circuit with scaled CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 111-112, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Soman Purushothaman |
A simple 4 quadrant NMOS analog multiplier with input range equal to +/-VDD and very low THD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 134-139, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Bruce Tseng, Hung-Ming Chen |
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 23-30, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
voltage island architecture, low power, buffer insertion |
41 | Stephen Bijansky, Adnan Aziz |
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 796-799, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, delay, process variation, yield, tuning |
41 | Hsiang-Hui Huang, Ching-Hwa Cheng |
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 110-118, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Mongkol Ekpanyapong, Sung Kyu Lim |
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 142-148, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
supply and threshold voltage scaling, low power design, retiming |
41 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 718-719, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo |
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 433-438, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Dharmaray Nedalgi, Saroja V. Siddamal |
Differential receiver with 2 × VDD input signals using 1 × VDD devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 87, pp. 306-312, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
39 | Liang Wen, Yuejun Zhang, Xiaoyang Zeng |
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(6), pp. 1470-1474, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
39 | Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei |
Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9), pp. 1475-1488, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Ming-Dou Ker, Po-Yen Chiu |
Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(10), pp. 2549-2560, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
39 | Yongtao Geng, Dongsheng Ma 0001 |
Design of reliable 2×VDD and 3×VDD series-parallel charge pumps in nanoscale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 705-708, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
39 | Po-Yen Chiu, Ming-Dou Ker |
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 33-36, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
39 | Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai |
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 163-168, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
39 | Chua-Chin Wang, Chia-Hao Hsu, Yi-Cheng Liu |
A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7), pp. 1642-1653, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
39 | Wen-An Tsou, Wen-Shen Wuen, Kuei-Ann Wen |
A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with Vdd/AM and Vdd /PM Compensations in EER System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACCS ![In: 2009 Pacific-Asia Conference on Circuits, Communications and Systems, PACCS 2009, Chengdu, China, 16-17 May 2009, pp. 47-50, 2009, IEEE Computer Society, 978-0-7695-3614-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Canh Quang Tran, Hiroshi Kawaguchi 0001, Takayasu Sakurai |
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 89-C(3), pp. 280-286, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
39 | Célia Fonseca Guerra, Jan-Willem Handgraaf, Evert Jan Baerends, Friedrich Matthias Bickelhaupt |
Voronoi deformation density (VDD) charges: Assessment of the Mulliken, Bader, Hirshfeld, Weinhold, and VDD methods for charge analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Chem. ![In: J. Comput. Chem. 25(2), pp. 189-210, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet |
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 129-138, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pausable clock, Vdd Hopping, Network-on-Chip, power, DVFS, GALS |
33 | Sherif A. Tawfik, Volkan Kursun |
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 62-67, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD |
33 | John Wei, Chris Rowen |
Implementing low-power configurable processors: practical options and tradeoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 706-711, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power |
33 | Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, Anteneh A. Abbo, Sebastian M. Londono, Henk Corporaal |
Xetal-Pro: an ultra-low energy and high throughput SIMD processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 543-548, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Xetal-Pro, hybrid memory system, SIMD, low-energy |
33 | Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun |
Power switch characterization for fine-grained dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 605-611, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat |
Analysis and minimization of practical energy in 45nm subthreshold logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 294-300, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura |
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 403-406, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
code allocation, low power design, on-chip memory |
33 | Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai |
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 133-136, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar |
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 30-34, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
DRV, low power, ECC, leakage, SRAM, variation, low voltage, error tolerant |
33 | Lerong Cheng, Fei Li 0003, Yan Lin 0001, Phoebe Wong, Lei He 0001 |
Device and Architecture Cooptimization for FPGA Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1211-1221, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001 |
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 207-212, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel |
Voltage- and ABB-island optimization in high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 153-158, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
adaptive body biasing, process variation, leakage, voltage islands |
33 | Flavio Bertini 0002, D. Davide Lamanna, Roberto Baldoni |
Virtual Distro Dispatcher: A Costless Distributed Virtual Environment from Trashware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, 5th International Symposium, ISPA 2007, Niagara Falls, Canada, August 29-31, 2007, Proceedings, pp. 223-234, 2007, Springer, 978-3-540-74741-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Trashware, LTSP, Clustering, Virtualization, User Mode Linux |
33 | Christian Piguet, Christian Schuster, Jean-Luc Nagel |
Static and Dynamic Power Reduction by Architecture Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 659-668, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Jun Zhou, David Kinniment, Gordon Russell 0002, Alexandre Yakovlev |
A Robust Synchronizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 442-443, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu |
Optimality study of resource binding with multi-Vdds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 580-585, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power design, behavioral synthesis, resource binding |
33 | Lerong Cheng, Phoebe Wong, Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Device and architecture co-optimization for FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 915-920, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Psim, Ptrace, powergating, FPGA, low power |
33 | Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung |
Leakage Reduction techniques in a 0.13um SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 215-221, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner |
Theoretical and practical limits of dynamic voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 868-873, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
minimum energy point, dynamic voltage scaling |
33 | Rajamohana Hegde, Naresh R. Shanbhag |
Toward achieving energy efficiency in presence of deep submicron noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 379-391, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Manish Goel, Naresh R. Shanbhag |
Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 463-476, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Atila Alvandpour, Per Larsson-Edefors, Christer Svensson |
Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 245-249, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
short-circuit current, power consumption, power estimation |
33 | Alan W. Righter, Charles F. Hawkins, Jerry M. Soden, Peter C. Maxwell |
CMOS IC reliability indicators and burn-in economics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 194-203, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
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