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IPDPS(464) IEEE Trans. Computers(447) DATE(392) CoRR(368) ISCAS(348) ISCA(344) DAC(331) IEEE Trans. Parallel Distribut...(324) ICASSP(295) IEEE J. Solid State Circuits(284) MICRO(270) ICCD(252) FPL(249) IEEE Trans. Very Large Scale I...(248) IEEE Micro(233) ASAP(228) More (+10 of total 2714)
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Found 25938 publication records. Showing 25938 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
50Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg Processor Architectures for Multimedia Applications. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
48Yung-Kang Chu, I-Ling Yen, Diane T. Rover Guiding processor allocation with estimated execution time for mesh connected multiple processor systems. Search on Bibsonomy HICSS (2) The full citation details ... 1995 DBLP  DOI  BibTeX  RDF estimated execution time, mesh connected multiple processor systems, mesh connected parallel architectures, multiprocessor systems design, submesh allocation strategies, two-dimensional mesh systems, estimated execution times, submesh allocation, processor allocation strategies, extensive simulations, system performance improvement, execution failures, scheduling, performance, resource allocation, parallel architectures, response time, processor scheduling, software performance evaluation, execution time, processor allocation, standard deviation, job characteristics, load conditions
46Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma 0011 A strategy for determining a Jacobi specific dataflow processor. Search on Bibsonomy ASAP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Jacobi specific dataflow processor, Jacobi algorithms, real-lime adaptive signal processing applications, quasi regularity property, dependence graph representations, exploration iteration, processor template, mapper, hierarchical exploration method, mapping efficiency, lookahead techniques, pipelining, retiming, adaptive signal processing, application domain, array processing
46Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, Rainer Schoenen, Heinrich Meyr DSP Processor/Compiler Co-Design: A Quantitative Approach. Search on Bibsonomy ISSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF processor/compiler codesign, benchmarking methodology, DSPstone, fast processor simulation, SuperSim, compiled processor simulation, performance evaluation, embedded systems, digital signal processing, digital signal processing chips, LISA, top-down approach, machine description
46Sukhamoy Som, Roland R. Mielke, John W. Stoughton Prediction of Performance and Processor Requirements in Real-Time Data Flow Architectures. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF processor requirements, ATAMM, Algorithm to Architecture Mapping Model, multiprocessor operating system, reliableperformance, four-processor architecture, VHSIC 1750A Instruction Set Processor, iterative control, signal processing algorithms, nonpreemptive, dynamicmultiprocessor scheduling, processor requirement prediction, faulttolerant computing, real-timesystems, scheduling, performance, real-time systems, multiprocessing systems, operating systems (computers), periodic, data flow graph, data flow architectures
46Mark I. Halpern Programming Languages: Toward a general processor for programming languages. Search on Bibsonomy Commun. ACM The full citation details ... 1968 DBLP  DOI  BibTeX  RDF compiler writing system, general processor, general translator, macro instruction processor, meta compiler, meta language processor, meta language translator, meta processor, programming language processor, programming language translator, compiler-compiler, translator writing system
46Marcus Bednara, Frank Hannig, Jürgen Teich Generation of Distributed Loop Control. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
44Fuji Ren Dialogue Machine Translation System Using Multiple Translation Processors. Search on Bibsonomy DEXA Workshops The full citation details ... 2000 DBLP  DOI  BibTeX  RDF dialogue machine translation system, multiple translation processors, natural dialogues, irregular expressions, natural conversation, ill-formed sentences, dialogue machine translation, MTP, translation processors, original language analysis, target language generation processing, Robust Parser based Translation Processor, Example Based Translation Processor, Family Modal based Translation Processor, Super Function based Translation Processor, information analysis model, syntactic constraint analysis model, semantic constraint analysis model, robust dialogue translation, language translation
44Rajaa S. Shindi, Shaun Cooper Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated. Search on Bibsonomy SIGAda The full citation details ... 2006 DBLP  DOI  BibTeX  RDF sim-alpha, cache, cpu, context switches, processor simulators
44Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux Vector Processing as a Soft Processor Accelerator. Search on Bibsonomy ACM Trans. Reconfigurable Technol. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF parallelism, Computer architecture, embedded processor, vector processor, multimedia processing, soft processor
43Jürgen Teich, Lothar Thiele Exact Partitioning of Affine Dependence Algorithms. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
42Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith 0001 A mechanistic performance model for superscalar out-of-order processors. Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
41Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau Aggregating processor free time for energy reduction. Search on Bibsonomy CODES+ISSS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF processor free time, embedded systems, aggregation, clock gating, code transformation, energy reduction
41Samuli Aalto, Urtzi Ayesta, Sem C. Borst, Vishal Misra, Rudesindo Núñez-Queija Beyond processor sharing. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF discriminatory processor sharing, in-sensitivity, multilevel processor sharing, workload, service differentiation, asymptotic analysis, queue length, sojourn time, generalized processor sharing, slowdown, delay minimization, size-based scheduling
41Alan R. Shealy, Brian A. Malloy, David A. Sykes SIMx86: An extensible simulator for the Intel 80×86 processor family. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF SIMx86, extensible simulator, Intel 80/spl times/86, Intel 8088 processor, 8086 processor, debugging facilities, simulator construction, virtual machines, domain model, performance gains, processor simulators
41W. Lynn Gallagher, Chuan-lin Wu Evaluation of a memory hierarchy for the MTS multithreaded processor. Search on Bibsonomy ICPADS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
41S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta A single chip, pipelined, cascadable, multichannel, signal processor. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron
40Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven A 2D Addressing Mode for Multimedia Applications. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Konstantin Avrachenkov, Urtzi Ayesta, Patrick Brown 0001 Batch Arrival Processor-Sharing with Application to Multi-Level Processor-Sharing Scheduling. Search on Bibsonomy Queueing Syst. Theory Appl. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF MX/G/1, work conservation, multi-level processor-sharing, processor-sharing, batch arrivals
38Ching-Hsien Hsu, Yeh-Ching Chung, Don-Lin Yang, Chyi-Ren Dow A Generalized Processor Mapping Technique for Array Redistribution. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF generalized processor mapping, distributed memory multicomputers, runtime support, Array redistribution
38Len Dekker, Edward E. E. Frietman Optical link and processor clustering in the Delft parallel processor. Search on Bibsonomy ICS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
38Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis (eds.) Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Vladimir D. Zivkovic, Paul Lieverse An Overview of Methodologies and Tools in the Field of System-Level Design. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Andy D. Pimentel, Simon Polstra, Frank Terpstra, A. W. van Halderen, Joseph E. Coffland, Louis O. Hertzberger Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38C. John Glossner, Michael J. Schulte, Stamatis Vassiliadis A Java-Enabled DSP. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana Microcoded Reconfigurable Embedded Processors: Current Developments. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Peter M. W. Knijnenburg, Toru Kisuki, Michael F. P. O'Boyle Iterative Compilation. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Clark N. Taylor, Debashis Panigrahi, Sujit Dey Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis Translating Imperative Affine Nested Loop Programs into Process Networks. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Henk L. Muller, Dan Page, James Irwin, David May 0001 Caches with Compositional Performance. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Christian Haubelt, Jürgen Teich, Kai Richter 0001, Rolf Ernst Flexibility/Cost-Tradeoffs of Platform-Based Systems. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Patrice Quinton, Tanguy Risset Structured Scheduling of Recurrence Equations: Theory and Practice. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF parallelization of loop nests, structured recurrence equations, automatic synthesis of parallel architectures, parallel VLSI architectures, scheduling
38Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Y-chart approach, Architecture Template, Stack of Y-charts, Abstraction Pyramid, Embedded Systems, Design Space Exploration
38Dirk Desmet, Prabhat Avasare, Paul Coene, Stijn Decneut, Filip Hendrickx, Théodore Marescaux, Jean-Yves Mignolet, Robert Pasko, Patrick Schaumont, Diederik Verkest Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Bishnupriya Bhattacharya, Shuvra S. Bhattacharyya Consistency Analysis of Reconfigurable Dataflow Specifications. Search on Bibsonomy Embedded Processor Design Challenges The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
36Jonah Probell Architecture Considerations for Multi-Format Programmable Video Processors. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF software programmable processor, hardwired processor, data tiling, SIMD, VLIW, processor architecture, multiprocessing
36Daniel Jiménez-González, Xavier Martorell, Alex Ramírez Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. Search on Bibsonomy ISPASS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
36Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki Area/delay estimation for digital signal processor cores. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
36Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno Hierarchical power distribution and power management scheme for a single chip mobile processor. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF mobile processor, partial power off, power domain, VLSI
36Sunghyun Jee, Kannappan Palaniappan Performance evaluation for a compressed-VLIW processor. Search on Bibsonomy SAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF CVLIW processor, individual instruction scheduling, VLIW, ILP
36Jean-Paul Theis, Lothar Thiele POM: a processor model for image processing. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF POM, Periodic Operation Model, optimal mapping trajectory, bus bandwidth constraints, scheduling, real-time systems, computational complexity, image processing, image processing, parallel processing, allocation, processor architecture, processor model
36Valentina Salapura, Michael Gschwind Hardware/Software Co-Design of a Fuzzy RISC Processor. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
36Francesco Gregoretti, F. Intini, Luciano Lavagno, Roberto Passerone, Leonardo Maria Reyneri Design and Implementation of the Control Structure of the PAPRICA-3 Processor. Search on Bibsonomy PDP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF PAPRICA-3 processor, instruction execution, linear array processor PAPRICA-9, multi path queue structure, real-time systems, image processing, embedded systems, parallel architectures, image recognition, pipeline processing, array processor, pipeline architecture, application programs, real time image processing, control structure, image processing equipment, algorithmic efficiency
36Michèle Dion, Tanguy Risset, Yves Robert Resource-constrained scheduling of partitioned algorithms on processor arrays. Search on Bibsonomy PDP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF physical processor arrays, communication capabilities, complex optimization problem, single integer linear programming problem, scheduling, computational complexity, complexity, linear programming, mapping, optimisation, processor arrays, partitioned algorithms, communication links, resource-constrained scheduling, optimal scheduling algorithms, linear processor arrays
36C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven Hades-towards the design of an asynchronous superscalar processor. Search on Bibsonomy ASYNC The full citation details ... 1995 DBLP  DOI  BibTeX  RDF asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design
35Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman Power-Conscious Design of the Cell Processor's Synergistic Processor Element. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Synergistic processor element, power-conscious design, low power, CMOS, SPE, Cell Processor
34Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas Architecture and Evaluation of an Asynchronous Array of Simple Processors. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous
34Donald F. Towsley, C. Gary Rommel, John A. Stankovic Analysis of Fork-Join Program Response Times on Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF fork-join program response times, task scheduling processor sharing, job scheduling processor sharing, system parameter values, performance evaluation, performance, multiprocessors, multiprocessing systems
34Bharadwaj Veeravalli, Debasish Ghose, V. Mani Optimal Sequencing and Arrangement in Distributed Single-Level Tree Networks with Communication Delays. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF optimalsequencing, distributed single-level tree networks, optimalprocessing time, single-level treearchitecture, optimal load distribution, load sequencing, processor-link arrangement, general case, computationalresults, root processor, front-end processor, optimal arrangement, resource allocation, distributed processing, distributed processing, optimisation, trees (mathematics), communication delays, distributed computing system, communication links, closed-form expressions
33Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown A Multithreaded Soft Processor for SoPC Area Reduction. Search on Bibsonomy FCCM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Roman L. Lysecky, Frank Vahid Design and implementation of a MicroBlaze-based warp processor. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
33Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan Online cache state dumping for processor debug. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cache compression, processor debug, silicon debug, design for debug, post-silicon validation
33Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai A low power VLIW processor generation method by means of extracting non-redundant activation conditions. Search on Bibsonomy CODES+ISSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low power, ASIP, clock gating, VLIW processor
33Ji-Jon Sit, Rahul Sarpeshkar A Cochlear-Implant Processor for Encoding Music and Lowering Stimulation Power. Search on Bibsonomy IEEE Pervasive Comput. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF fine-timing information, electrode stimulation, analog processor, phase information, music processor, neural stimulation, low power, asynchronous, cochlear implant
33Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek A Parallel Multimedia Processor for Macroblock Based Compression Standards. Search on Bibsonomy ICIP (2) The full citation details ... 1997 DBLP  DOI  BibTeX  RDF parallel multimedia processor, macroblock based compression standards, block-based video processing algorithms, DGP, digital generic processor, generic system architecture, pixel processors, RISC controller, video processing algorithms, video effects, window clipping, H.261, 1.7 GIPS, 54 MHz, 0.5 micron, code, video compression, digital filtering, MPEG-2, digital signal processing chips, H.263, SIMD architecture, MPEG-1
33Cheng Chang, Chien-Chung Chen, Yao-Liang Chen, Fu-Shin Huang Real-time scheduling in a programmable radar signal processor. Search on Bibsonomy RTCSA The full citation details ... 1997 DBLP  DOI  BibTeX  RDF programmable radar signal processor, parallel multi-processor architecture, real-time scheduling algorithm, digital signal processing, real-time scheduling, processing speed, radar signal processing
33Hiroshi Fujita, Tatsuo Nakajima, Hiroshi Tezuka A processor reservation system supporting dynamic QOS control. Search on Bibsonomy RTCSA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF processor reservation system, dynamic QOS control, QOS values, user-level admission server, kernel support, scheduling, processor scheduling, multimedia computing, multimedia computing
33Bret Stott, Dave Johnson 0003, Venkatesh Akella Asynchronous 2-D discrete cosine transform core processor. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
33Fujio Yamaguchi A unified approach to interference problems using a triangle processor. Search on Bibsonomy SIGGRAPH The full citation details ... 1985 DBLP  DOI  BibTeX  RDF determinant processor, geometry processor, interference problems, geometric modeling
33Peter R. Cappello Application-specific Processor Architecture: Then and Now. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF field-programmable gate array, FPGA, computer architecture, taxonomy, systolic array, processor array, application-specific processor, general-purpose processor
33Myung Hoon Sunwoo, Soohwan Ong, Byungdug Ahn, Kyungwoo Lee Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor. Search on Bibsonomy ASAP The full citation details ... 1995 DBLP  DOI  BibTeX  RDF SIMD Array Processors, ASIC Chip, Image Processing, VLSI Design, VLSI Architectures
33Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. Search on Bibsonomy IEEE Micro The full citation details ... 2005 DBLP  DOI  BibTeX  RDF 11 fan-out of four, 11FO4, Synergistic Processor Element, private memory, streaming processing, Cell processor, multimedia processing, scratch pad memory
31Krutartha Patel, Sridevan Parameswaran, Seng Lin Shee Ensuring secure program execution in multiprocessor embedded systems: a case study. Search on Bibsonomy CODES+ISSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF embedded system processors, tensilica, security, multiprocessors, code injection attacks
31Edward D. Moreno, Sergio Takeo Kofuji Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results. Search on Bibsonomy ISPAN The full citation details ... 1997 DBLP  DOI  BibTeX  RDF shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness
31Clifford W. Mercer, Ragunathan Rajkumar An interactive interface and RT-Mach support for monitoring and controlling resource management. Search on Bibsonomy IEEE Real Time Technology and Applications Symposium The full citation details ... 1995 DBLP  DOI  BibTeX  RDF RT-Mach, Real-Time Mach, resource management monitoring, resource management control, timing characteristics, a priori resource allocation decisions, changing user needs, operating system resource reserves, resource reservation abstraction, processor capacity reserves, rmon, processor usage display, processor reservation, reservation change requests, policy decisions, real-time systems, user interfaces, resource allocation, timing, multimedia systems, dynamic systems, interactive systems, operating systems (computers), multimedia computing, system monitoring, quality of service manager, interactive interface
31Norman R. Howes, Alfred C. Weaver Measurements of Ada Overhead in OSI-Style Communications Systems. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF OSI-style communications systems, Ada model, seven-layer OSI reference model, single-processor machines, VAX 11/785, Rational 1000, expected message delay, novel model, server tasks, eight-processor Sequent Model 821, 14-processor Encore Multimax 320, Buhr model, server task model, Ada rendezvous, Ada overhead per message, parallel programming, Ada, concurrency, standards, computer networks, open systems, communications model, procedure calls
31Chen-Yong Cher, Michael Gschwind Cell GC: using the cell synergistic processor as a garbage collection coprocessor. Search on Bibsonomy VEE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF BDW, SPU, explicitly managed memory hierarchies, local store, garbage collection, accelerator, SPE, coprocessor, cell, mark-sweep
31Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF IPI power model, black-box power model, prefetch power model, processor power modeling, software power estimation
31Michael J. Schulte, John Glossner, Sanjay Jinturkar, Mayan Moudgill, Suman Mamidi, Stamatis Vassiliadis A Low-Power Multithreaded Processor for Software Defined Radio. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF low power, wireless communication, computer architecture, multithreading, microarchitecture, Software Defined Radio, processor design
31Kristen Accardi, Tony Bock, Frank T. Hady, Jon Krueger Network processor acceleration for a Linux* netfilter firewall. Search on Bibsonomy ANCS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF hybrid firewall, network firewall, prototype, throughput, network processor, netfilter
31Phillip Krueger, Ten-Hwang Lai, Vibha A. Dixit-Radiya ob Scheduling is More Important than Processor Allocation for Hypercube Computers. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF hypercubecomputers, scheduling, scheduling, resource allocation, hypercube, hypercube networks, job scheduling, Scan, processor allocation, performance problems
31Sascha Uhrig, Jörg Wiese jamuth: an IP processor core for embedded Java real-time systems. Search on Bibsonomy JTRES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Java execution environment, embedded system-on-a-chip implementation, virtual machine, real-time embedded system, multithreaded processor, Java processor, embedded operating system
31Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF C compiler retargeting, embedded processor design, architecture description language, processor model, electronic system level
31Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose Application-specific customization of soft processor microarchitecture. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
31Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen A unified processor architecture for RISC & VLIW DSP. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF dual-core processor, register organization, variable-length instruction encoding, digital signal processor
31Robert Yung, Neil C. Wilhelm Caching processor general registers. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
31Sanjeev Setia, Mark S. Squillante, Satish K. Tripathi Analysis of Processor Allocation in Multiprogrammed, Distributed-Memory Parallel Processing Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF queueingtheory, independent jobs, multiple sequential tasks, job response time, distributed fork-joinqueueing system, processor allocation policy, bulk arrival queues, communicationoverhead, fork-join queues, modeling and analysis, scheduling, scheduling, parallel processing, parallel architectures, operating systems, shared-memory, synchronisation, shared memory systems, distributed memory systems, multiprogrammed, multiprogramming, processor allocation, distributed-memory, distributed memory, parallel processing systems, synchronization delay
31Dipak Ghosal, Giuseppe Serazzi, Satish K. Tripathi The Processor Working Set and Its Use in Scheduling Multiprocessor Systems. Search on Bibsonomy IEEE Trans. Software Eng. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF processor working set, PWS, parallel program behavior, transputer-based multiprocessor machine, processor allocation strategies, static allocation policy, scheduling, scheduling, multiprocessing systems, transputers
31J. M. Herron, J. Farley, Kendall Preston Jr., H. Sellner A General-Purpose High-Speed Logical Transform Image Processor. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF peripheral processor, image processor, neighborhood transform, parallel processor, Array processing, cellular logic
29David J. Bastyr Nondedicated interprocessor communications discipline. Search on Bibsonomy AFIPS National Computer Conference The full citation details ... 1977 DBLP  DOI  BibTeX  RDF
29Ragunathan Rajkumar, Michael Gagliardi High availability in the real-time publisher/subscriber inter-process communication model. Search on Bibsonomy RTSS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF real time publisher/subscriber communications model, interprocess communication model, rejoins, repetitive real time processes, RT P/S model, processor membership protocol layer, periodic broadcast membership protocol, strong semantics, idempotence properties, weak interleaving needs, communication programming interface, steady state real time execution paths, multimedia dissemination applications, fault tolerant computing, distributed processing, feedback control, distributed real time systems, node failures, processor failures
29Sekhar R. Sarukkai, Jerry C. Yan, Melisa Schmidt Automated instrumentation and monitoring of data movement in parallel programs. Search on Bibsonomy IPPS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF data-structure alignments, inter-processor data-structure interactions, compiler front end tools, tracking data-structure movements, NAS benchmarks, parallel programming, parallel programs, data structures, message passing, data flow analysis, software performance evaluation, program diagnostics, performance tools, message passing programs, inter-processor communications, data movement
29Chris H. L. Moller, Gerald G. Pechanek Architectural simulation system for M.f.a.s.t. Search on Bibsonomy Annual Simulation Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF pulse transformers, architectural simulation system, architecture verification, Mwave folded array signal transform processor, single chip scalable very long instruction word processor array, independent processes, socket mechanism, execution-unit operations, execution emulation, M.f.a.s.t. processor, parallel architectures, virtual machines, reconfigurable architectures, digital signal processing chips, instruction sets, functional models, array signal processing, simulator performance
28Joshua Noseworthy, Miriam Leeser Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Guilin Chen, Mahmut T. Kandemir Optimizing inter-processor data locality on embedded chip multiprocessors. Search on Bibsonomy EMSOFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF chip multiprocessors, data locality, stencil computation
28Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
28Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz Using a configurable processor generator for computer architecture prototyping. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
28Robert C. Hampshire, William A. Massey A note on the event horizon for a processor sharing queue. Search on Bibsonomy Queueing Syst. Theory Appl. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Processor sharing queues, Diffusion limits, Dynamical queueing systems, Uniform acceleration, Virtual customers, Sojourn times, Transient behavior, Fluid limits
28Mladen Berekovic, Tim Niggemeier A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF clustering, distributed computing, DSP, MPEG-4, multi-threading, processor architecture, SMT
28Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt Methodology for multi-granularity embedded processor power model generation for an ESL design flow. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF system-on-chip, embedded processor, power modeling, esl
28Xiaodong Li, Ritu Gupta, Sarita V. Adve, Yuanyuan Zhou Cross-component energy management: Joint adaptation of processor and memory. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low-power design, memory, adaptive systems, processor, Energy management, performance guarantee, control algorithms
28Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich Efficient event-driven simulation of parallel processor architectures. Search on Bibsonomy SCOPES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF embedded tools, simulation, modeling, processor arrays
28Nikolay Kostadinov, Anelia Ivanova A VHDL training model of a processor. Search on Bibsonomy CompSysTech The full citation details ... 2007 DBLP  DOI  BibTeX  RDF CPLD implementation, VHDL model, processor, instruction set
28Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar An ultra low-power processor for sensor networks. Search on Bibsonomy ASPLOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF picojoule computing, sensor network processor, sensor networks, wireless, asynchronous, low-energy, event-driven
28Minsu Choi, Nohpill Park, Fabrizio Lombardi Hardware-Software Co-Reliability in Field Reconfigurable Multi-Processor-Memory Systems. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Multi-Processor-Memory System, Field Reconfiguration, HW/SW Co-reliability, Modular Redundancy
28Sunghyun Jee, Kannappan Palaniappan Compiler Processor Tradeoffs for DISVLIW Architecture. Search on Bibsonomy ISPAN The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Balanced Scheduling, DISVLIW, Processor architecture, ILP
28Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens Processor modeling and code selection for retargetable compilation. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF code selection, graph instruction set graph, retargetable code generation, embedded systems, system design, retargetable compilation, processor modeling
28T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik Processor Evaluation in an Embedded Systems Design Environment. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF ASAP scheduler, Architecture constrained scheduler, ASIP, Processor architecture, Real-time constraints, Application profiling
28Anteneh Alemu Abbo An Embedded Processor for Integrated Navigation Receiver. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Integrated Navigation, Embedded Systems, FIR Filter, Application-Specific Processor
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