Search results for "instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
97	John D. Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
85	Yuying Wang, Xingshe Zhou 0001	Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy.	ICPP Workshops	2007	DBLP DOI BibTeX RDF	Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy
81	Xianhua Liu 0001, Jiyu Zhang, Xu Cheng 0001	NISD: A Framework for Automatic Narrow Instruction Set Design.	ICESS	2007	DBLP DOI BibTeX RDF	dual-width instruction set, narrow instruction set design, automatic instruction set design
78	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye	Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.	MICRO	1996	DBLP DOI BibTeX RDF	TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures
77	Toshinori Sato	A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism.	EUROMICRO	1999	DBLP DOI BibTeX RDF	instruction reissue, instruction window design, instruction level parallelism, data speculation, dynamic instruction scheduling
73	Ahmad Zmily, Christos Kozyrakis	A low power front-end for embedded processors using a block-aware instruction set.	CASES	2007	DBLP DOI BibTeX RDF	instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching
72	Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).	LCTES	2009	DBLP DOI BibTeX RDF	l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic)
72	Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min	Selective code transformation for dual instruction set processors.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Dual instruction set processors, mixed-width instruction set architecture, reduced bid-width instruction set architecture
69	Jack W. Davidson, David B. Whalley	Ease: An Environment for Architecture Study and Experimentation.	SIGMETRICS	1990	DBLP DOI BibTeX RDF
68	Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001	CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache
68	Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung	Design of Instruction Stream Buffer with Trace Support for X86 Processors.	ICCD	2000	DBLP DOI BibTeX RDF	instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache
66	Arvind Krishnaswamy, Rajiv Gupta 0001	Dynamic coalescing for 16-bit instructions.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, energy, Embedded processor, code size
63	Jun Yan 0008, Wei Zhang 0002	Analyzing the worst-case execution time for instruction caches with prefetching.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	instruction caches, hard real-time, Worst-case execution time analysis, instruction prefetching
63	Jun Yan 0008, Wei Zhang 0002	WCET analysis of instruction caches with prefetching.	LCTES	2007	DBLP DOI BibTeX RDF	instruction cache, hard real-time, worst-case execution time analysis, instruction prefetching
63	Pierre Michaud, André Seznec, Stéphan Jourdan	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
63	Gideon D. Intrater, Ilan Y. Spillinger	Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	decoded instruction cache, variable instruction length computers, instruction decoder, instruction pipeline stages, instruction length distribution, UNIX applications, performance evaluation, performance evaluation, computer architecture, trace driven simulations, buffer storage
61	A. F. R. Brown	Language Translation.	J. ACM	1958	DBLP DOI BibTeX RDF
60	Stephen Roderick Hines, Gary S. Tyson, David B. Whalley	Addressing instruction fetch bottlenecks by using an instruction register file.	LCTES	2007	DBLP DOI BibTeX RDF	L0/filter cache, instruction packing, instruction register file
60	Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt	Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.	DAC	2003	DBLP DOI BibTeX RDF	instruction abstraction, interpretive simulation, instruction set architectures, compiled simulation
60	Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001	A retargetable framework for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm
60	Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt	An efficient retargetable framework for instruction-set simulation.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm
60	Robert Yung	Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture.	MICRO	1996	DBLP DOI BibTeX RDF	UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor
59	W. Lynn Gallagher, Chuan-lin Wu	Evaluation of a memory hierarchy for the MTS multithreaded processor.	ICPADS	1997	DBLP DOI BibTeX RDF	memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache
59	Stavros Harizopoulos, Anastassia Ailamaki	Improving instruction cache performance in OLTP.	ACM Trans. Database Syst.	2006	DBLP DOI BibTeX RDF	Instruction cache, cache misses
58	Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos	Temporal instruction fetch streaming.	MICRO	2008	DBLP DOI BibTeX RDF
58	Jun Yang 0002, Rajiv Gupta 0001	Load Redundancy Removal through Instruction Reuse.	ICPP	2000	DBLP DOI BibTeX RDF
57	Roger Collins, Gordon B. Steven	Instruction Scheduling for a Superscalar Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
57	Robert Law	Using student blogs for documentation in software development projects.	ITiCSE	2011	DBLP DOI BibTeX RDF
55	Eric Rotenberg, Steve Bennett, James E. Smith 0001	Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.	MICRO	1996	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, instruction cache, trace cache, instruction fetching
55	Allen C. Cheng, Gary S. Tyson	An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Low-power design, reconfigurable hardware, real-time and embedded systems, energy-aware systems, instruction set design
55	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
54	Toshinori Sato, Itsujiro Arita	Simplifying Instruction Issue Logic in Superscalar Processors.	DSD	2002	DBLP DOI BibTeX RDF
54	Glenn Reinman, Brad Calder, Todd M. Austin	Optimizations Enabled by a Decoupled Front-End Architecture.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	fetch architectures, branch prediction, Decoupled architectures, instruction prefetching
53	Alfred Kirigha, Neema-Abooki	Systemic Design of Instruction On Achieving The Goals of Undergraduate Level Education in Universities: A Case Study of Makerere University.	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF	ADDIE: Analysis, Implementation and Evaluation, FCIT: Faculty of Computing and Information Technologies, ICT: Information Communication Technologies, MANCOVA: Multiple Analysis of Covariance, SOE: School of Education, Design, Development
52	Shao-Yang Wang, Rong-Guey Chang	Code size reduction by compressing repeated instruction sequences.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Repeated instruction sequence, Index table, Instruction table, Register bank, Code compression, Decompression, Instruction prefetching
52	Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye	Dynamic Binary Translation and Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	adaptive code generation, profile-directed feedback, very long instruction word architectures, instruction set layering, virtual machines, instruction-level parallelism, dynamic optimization, just-in-time compilation, binary translation, Dynamic compilation, instruction set architectures
51	Aleksandar Milenkovic, Milena Milenkovic	An efficient single-pass trace compression technique utilizing instruction streams.	ACM Trans. Model. Comput. Simul.	2007	DBLP DOI BibTeX RDF	Instruction and data traces, instruction streams, trace compression
51	Ahmad Zmily, Christos Kozyrakis	Block-aware instruction set architecture.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	basic block, software hints, branch prediction, Instruction set architecture, instruction fetch, decoupled architecture
51	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler optimization on VLIW instruction scheduling for low power.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers
51	Jack Liu, Timothy Kong, Fred C. Chow	Effective Compilation Support for Variable Instruction Set Architecture.	IEEE PACT	2002	DBLP DOI BibTeX RDF	configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling
51	Valentina Salapura, Michael Gschwind	Hardware/Software Co-Design of a Fuzzy RISC Processor.	DATE	1998	DBLP DOI BibTeX RDF	hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism
50	J. H. Jacobs, Augustus K. Uht, R. C. Ord	Modeling the effects of instruction queue loading on a static instruction stream micro-architecture.	MICRO	1988	DBLP BibTeX RDF
50	Chih-Yao Lo, Hsin-I Chang, Yu-Teng Chang	Research on Recreational Sports Instruction Using an Expert System.	AMT	2009	DBLP DOI BibTeX RDF	Recreational Sports Instruction, Fuzzy Inference Mechanism, Expert System
50	Chris J. Michael, Maciej Brodowicz, Thomas L. Sterling	Improving code compression using clustered modalities.	ACM Southeast Regional Conference	2008	DBLP DOI BibTeX RDF	data clustering, code compression, instruction set architecture
50	Arvind Krishnaswamy, Rajiv Gupta 0001	Enhancing the performance of 16-bit code using augmenting instructions.	LCTES	2003	DBLP DOI BibTeX RDF	16-bit thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, embedded processor, code size
49	Pairoj Trirathanakul, Suwanna Sombunsukho, Suriyong Lertkulvanich, Nithi Buranajant	An Effective Construction of Computer Assisted Lesson Based on Interactive Multimedia Computer Assisted Instruction Theory (IMMCAI).	Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education	2008	DBLP DOI BibTeX RDF
48	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Instruction set synthesis with efficient instruction encoding for configurable processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding
48	Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura	Energy-efficient dynamic instruction scheduling logic through instruction grouping.	ISLPED	2006	DBLP DOI BibTeX RDF	instruction grouping, issue queue, dynamic instruction scheduling
48	Jack Liu, Fred C. Chow	A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor.	CASES	2002	DBLP DOI BibTeX RDF	configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling
48	Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi	A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .	ISSS	2002	DBLP DOI BibTeX RDF	compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure
47	Ahmad Zmily, Christos Kozyrakis	Energy-efficient and high-performance instruction fetch using a block-aware ISA.	ISLPED	2005	DBLP DOI BibTeX RDF	basic blocks, energy efficiency, instruction set architecture, decoupled architecture, instruction delivery
47	Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures
47	Jack Liu, Fred C. Chow, Timothy Kong, Rupan Roy	Variable Instruction Set Architecture and Its Compiler Support.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling
47	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Energy-efficient instruction set synthesis for application-specific processors.	ISLPED	2003	DBLP DOI BibTeX RDF	low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product
46	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Efficient instruction encoding for automatic instruction set design of configurable ASIPs.	ICCAD	2002	DBLP DOI BibTeX RDF
46	Demid Borodin, Ben H. H. Juurlink	Protective redundancy overhead reduction using instruction vulnerability factor.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	instruction vulnerability, selective protection, performance, redundancy, fault detection
46	Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec	Generalized instruction selection using SSA-graphs.	LCTES	2008	DBLP DOI BibTeX RDF	pbqp, compiler, code generation, instruction selection
46	Martina Ziefle	Instruction Formats and Navigation Aids in Mobile Devices.	USAB	2008	DBLP DOI BibTeX RDF	Instruction format, navigation effectiveness, landmark knowledge, route knowledge, survey knowledge, efficiency, navigation aid
46	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
46	Ruby B. Lee, A. Murat Fiskiran	PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, processor architecture, instruction set architecture, media processing, ISA
46	Eric Rotenberg, Steve Bennett, James E. Smith 0001	A Trace Cache Microarchitecture and Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching
46	Shengning Wu, Sikun Li	Instruction Selection for ARM/Thumb Processors Based on a Multi-objective Ant Algorithm.	CSR	2006	DBLP DOI BibTeX RDF
46	Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min	A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.	SCOPES	2004	DBLP DOI BibTeX RDF
46	Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson	Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.	SCOPES	2003	DBLP DOI BibTeX RDF
46	Eunlim Chi, Chanjung Park, Hwakyung Rim	Evaluating the Web-Based Instruction by Item Analysis.	ICCSA (2)	2003	DBLP DOI BibTeX RDF
46	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	An instruction-level energy model for embedded VLIW architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
46	Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta	Instruction fetch deferral using static slack.	MICRO	2002	DBLP DOI BibTeX RDF
46	Glenn Reinman, Brad Calder, Todd M. Austin	Fetch Directed Instruction Prefetching.	MICRO	1999	DBLP DOI BibTeX RDF
46	Toshinori Sato	Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure.	Euro-Par	1999	DBLP DOI BibTeX RDF
45	Ramón D. Acosta, Jacob Kjelstrup, Hwa C. Torng	An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	processor performance enhancement, Dispatch stack, instruction issuing, instruction unit, multiple functional unit processors, multiple instruction dispatching, dynamic instruction scheduling
45	James Leslie Keedy	An Instruction Set for Evaluating Expressions.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	stack-based instruction sets, instruction set optimization, memory-to-memory instruction sets, Code compactness, expression evaluation, instruction set design
44	Hai Lin 0004, Yunsi Fei	A novel multi-objective instruction synthesis flow for application-specific instruction set processors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	instruction set synthesis, application-specific instruction set processor (ASIP)
44	Ing-Jer Huang	Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis
43	Daniel Christopher Powell, Björn Franke	Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	continuous statistical machine learning, performance prediction, instruction set simulator
43	Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke	Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions.	CGO	2010	DBLP DOI BibTeX RDF	ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection
43	Yulai Zhao 0003, Xianfeng Li, Dong Tong 0001, Xu Cheng 0001	An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	content associative memory (CAM), tag elimination, waiting instruction buffer, instruction scheduler, energy-efficient architecture
43	Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero	A first glance at Kilo-instruction based multiprocessors.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors
43	Aneesh Aggarwal, Manoj Franklin	Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency.	IEEE PACT	2003	DBLP DOI BibTeX RDF	Instruction Replication, Inter-PE communication, Instruction Distribution, Instructions per Cycle, Load Imbalance, Clustered processors
43	Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero	A Simple Low-Energy Instruction Wakeup Mechanism.	ISHPC	2003	DBLP DOI BibTeX RDF	Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window
43	Shyh-Kwei Chen, W. Kent Fuchs	Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
43	David A. Dunn, Wei-Chung Hsu	Instruction Scheduling for the HP PA-8000.	MICRO	1996	DBLP DOI BibTeX RDF	HP PA-8000, instruction polarity cache interfaces, memory dependences, production compiler, scheduling, latency, compiler optimization, instruction scheduling, resource constraints, micro-architecture
42	Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita	SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture.	ISCA	1989	DBLP DOI BibTeX RDF
42	Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt	Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation
42	David Ryan Koes, Seth Copen Goldstein	Near-optimal instruction selection on dags.	CGO	2008	DBLP DOI BibTeX RDF	instruction selection
42	Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra	Exploiting forwarding to improve data bandwidth of instruction-set extensions.	DAC	2006	DBLP DOI BibTeX RDF	instruction-set extensions, data forwarding
42	Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam	A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy.	ISCA	2004	DBLP DOI BibTeX RDF	Complexity-effective design, Temporal Redundancy, Instruction Reuse
42	G. Surendra, Subhasis Banerjee, S. K. Nandy 0001	On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	multiprocessors, network processors, value prediction, instruction reuse
42	Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick	A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	architectural verification, biased random instruction generation, correctness checking, design error coverage, design verification, coverage metrics
42	Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark	Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	instruction window size, register-update unit, simulation, cache, sampling, branch prediction, Microarchitecture, trade-offs, out-of-order execution
42	Stephen Hines, David B. Whalley, Gary S. Tyson	Adapting compilation techniques to enhance the packing of instructions into registers.	CASES	2006	DBLP DOI BibTeX RDF	instruction packing, instruction register file, compiler optimizations
42	Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim	DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems.	DATE	2007	DBLP DOI BibTeX RDF
42	Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte	Power-efficient Instruction Encoding Optimization for Embedded Processors.	VLSI Design	2007	DBLP DOI BibTeX RDF
42	Hai-Chen Wang, Chung-Kwong Yuen	Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor.	IPDPS	2006	DBLP DOI BibTeX RDF
42	Dinesh C. Suresh, Walid A. Najjar, Jun Yang 0002	Power Efficient Instruction Caches for Embedded Systems.	SAMOS	2005	DBLP DOI BibTeX RDF
42	Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon	Energy estimation and optimization of embedded VLIW processors based on instruction clustering.	DAC	2002	DBLP DOI BibTeX RDF	power estimation, vliw architectures
42	Heidi Pan, Krste Asanovic	Heads and tails: a variable-length instruction format supporting parallel fetch and decode.	CASES	2001	DBLP DOI BibTeX RDF
42	P.-H. Chang, Wen-mei W. Hwu	Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors.	MICRO	1989	DBLP DOI BibTeX RDF
42	Wen-mei W. Hwu, Pohua P. Chang	Achieving High Instruction Cache Performance with an Optimizing Compiler.	ISCA	1989	DBLP DOI BibTeX RDF
42	Jack W. Davidson, Richard A. Vaughan	The Effect of Instruction Set Complexity on Program Size and Memory Performance.	ASPLOS	1987	DBLP DOI BibTeX RDF
41	Arvind Krishnaswamy, Rajiv Gupta 0001	Efficient Use of Invisible Registers in Thumb Code.	MICRO	2005	DBLP DOI BibTeX RDF