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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8210 occurrences of 3021 keywords
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Results
Found 11442 publication records. Showing 11442 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
97 | John D. Bunda, Donald S. Fussell, William C. Athas |
Energy-efficient instruction set architecture for CMOS microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 298-305, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density |
85 | Yuying Wang, Xingshe Zhou 0001 |
Mutual Effect of Instruction Layout Optimization and Instruction Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 10-14 September 2007, Xi-An, China, pp. 22, 2007, IEEE Computer Society, 978-0-7695-2934-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Instruction Layout Optimization, Instruction Cache Miss Rate, Cache Memory Hierarchy |
81 | Xianhua Liu 0001, Jiyu Zhang, Xu Cheng 0001 |
NISD: A Framework for Automatic Narrow Instruction Set Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 271-282, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
dual-width instruction set, narrow instruction set design, automatic instruction set design |
78 | Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye |
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 201-211, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures |
77 | Toshinori Sato |
A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1178-1185, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction reissue, instruction window design, instruction level parallelism, data speculation, dynamic instruction scheduling |
73 | Ahmad Zmily, Christos Kozyrakis |
A low power front-end for embedded processors using a block-aware instruction set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 267-276, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
instruction re-ordering, low power front-end, software hints, tagless instruction cache, unified instruction cache and BTB, instruction prefetching |
72 | Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson |
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 119-128, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic) |
72 | Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min |
Selective code transformation for dual instruction set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 6(2), pp. 10, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Dual instruction set processors, mixed-width instruction set architecture, reduced bid-width instruction set architecture |
69 | Jack W. Davidson, David B. Whalley |
Ease: An Environment for Architecture Study and Experimentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, University of Colorado, Boulder, Colorado, USA, May 22-25, 1990, pp. 259-260, 1990, ACM, 0-89791-359-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
68 | Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001 |
CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(1), pp. 141-153, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache |
68 | Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 294-299, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache |
66 | Arvind Krishnaswamy, Rajiv Gupta 0001 |
Dynamic coalescing for 16-bit instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(1), pp. 3-37, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
16-bit Thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, energy, Embedded processor, code size |
63 | Jun Yan 0008, Wei Zhang 0002 |
Analyzing the worst-case execution time for instruction caches with prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(1), pp. 7:1-7:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instruction caches, hard real-time, Worst-case execution time analysis, instruction prefetching |
63 | Jun Yan 0008, Wei Zhang 0002 |
WCET analysis of instruction caches with prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 175-184, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
instruction cache, hard real-time, worst-case execution time analysis, instruction prefetching |
63 | Pierre Michaud, André Seznec, Stéphan Jourdan |
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 2-10, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, branch prediction, superscalar processors, instruction fetch |
63 | Gideon D. Intrater, Ilan Y. Spillinger |
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(10), pp. 1140-1150, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
decoded instruction cache, variable instruction length computers, instruction decoder, instruction pipeline stages, instruction length distribution, UNIX applications, performance evaluation, performance evaluation, computer architecture, trace driven simulations, buffer storage |
61 | A. F. R. Brown |
Language Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 5(1), pp. 1-8, 1958. The full citation details ...](Pics/full.jpeg) |
1958 |
DBLP DOI BibTeX RDF |
|
60 | Stephen Roderick Hines, Gary S. Tyson, David B. Whalley |
Addressing instruction fetch bottlenecks by using an instruction register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 165-174, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
L0/filter cache, instruction packing, instruction register file |
60 | Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt |
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 758-763, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
instruction abstraction, interpretive simulation, instruction set architectures, compiled simulation |
60 | Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001 |
A retargetable framework for instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 431-452, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm |
60 | Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt |
An efficient retargetable framework for instruction-set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 13-18, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm |
60 | Robert Yung |
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 178-190, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor |
59 | W. Lynn Gallagher, Chuan-lin Wu |
Evaluation of a memory hierarchy for the MTS multithreaded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 11-13 December 1997, Seoul, Korea, Proceedings, pp. 346-351, 1997, IEEE Computer Society, 0-8186-8227-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache |
59 | Stavros Harizopoulos, Anastassia Ailamaki |
Improving instruction cache performance in OLTP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Database Syst. ![In: ACM Trans. Database Syst. 31(3), pp. 887-920, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Instruction cache, cache misses |
58 | Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos |
Temporal instruction fetch streaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 1-10, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
58 | Jun Yang 0002, Rajiv Gupta 0001 |
Load Redundancy Removal through Instruction Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 2000 International Conference on Parallel Processing, ICPP 2000, Toronto, Canada, August 21-24, 2000, pp. 61-68, 2000, IEEE Computer Society, 0-7695-0768-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
57 | Roger Collins, Gordon B. Steven |
Instruction Scheduling for a Superscalar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 643-650, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions |
57 | Robert Law |
Using student blogs for documentation in software development projects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 16th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2011, Darmstadt, Germany, June 27-29, 2011, pp. 366, 2011, ACM, 978-1-4503-0697-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
55 | Eric Rotenberg, Steve Bennett, James E. Smith 0001 |
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 24-35, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiple branch prediction, superscalar processors, instruction cache, trace cache, instruction fetching |
55 | Allen C. Cheng, Gary S. Tyson |
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 698-713, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Low-power design, reconfigurable hardware, real-time and embedded systems, energy-aware systems, instruction set design |
55 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 123-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers |
54 | Toshinori Sato, Itsujiro Arita |
Simplifying Instruction Issue Logic in Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 341-346, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
54 | Glenn Reinman, Brad Calder, Todd M. Austin |
Optimizations Enabled by a Decoupled Front-End Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 338-355, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fetch architectures, branch prediction, Decoupled architectures, instruction prefetching |
53 | Alfred Kirigha, Neema-Abooki |
Systemic Design of Instruction On Achieving The Goals of Undergraduate Level Education in Universities: A Case Study of Makerere University. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education ![In: Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education, Proceedings of the 2007 International Conference on Engineering Education, Instructional Technology, Assessment, and E-learning (EIAE 2007), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2007), Bridgeport, CT, USA, December 3-12, 2007, pp. 35-40, 2008, Springer, 978-1-4020-8738-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ADDIE: Analysis, Implementation and Evaluation, FCIT: Faculty of Computing and Information Technologies, ICT: Information Communication Technologies, MANCOVA: Multiple Analysis of Covariance, SOE: School of Education, Design, Development |
52 | Shao-Yang Wang, Rong-Guey Chang |
Code size reduction by compressing repeated instruction sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 40(3), pp. 319-331, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Repeated instruction sequence, Index table, Instruction table, Register bank, Code compression, Decompression, Instruction prefetching |
52 | Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye |
Dynamic Binary Translation and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(6), pp. 529-548, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
adaptive code generation, profile-directed feedback, very long instruction word architectures, instruction set layering, virtual machines, instruction-level parallelism, dynamic optimization, just-in-time compilation, binary translation, Dynamic compilation, instruction set architectures |
51 | Aleksandar Milenkovic, Milena Milenkovic |
An efficient single-pass trace compression technique utilizing instruction streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Model. Comput. Simul. ![In: ACM Trans. Model. Comput. Simul. 17(1), pp. 2, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Instruction and data traces, instruction streams, trace compression |
51 | Ahmad Zmily, Christos Kozyrakis |
Block-aware instruction set architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(3), pp. 327-357, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
basic block, software hints, branch prediction, Instruction set architecture, instruction fetch, decoupled architecture |
51 | Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai |
Compiler optimization on VLIW instruction scheduling for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(2), pp. 252-268, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers |
51 | Jack Liu, Timothy Kong, Fred C. Chow |
Effective Compilation Support for Variable Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 56-67, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
51 | Valentina Salapura, Michael Gschwind |
Hardware/Software Co-Design of a Fuzzy RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 875-882, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism |
50 | J. H. Jacobs, Augustus K. Uht, R. C. Ord |
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 11-20, 1988, ACM/IEEE, 0-8186-1919-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
50 | Chih-Yao Lo, Hsin-I Chang, Yu-Teng Chang |
Research on Recreational Sports Instruction Using an Expert System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMT ![In: Active Media Technology, 5th International Conference, AMT 2009, Beijing, China, October 22-24, 2009. Proceedings, pp. 250-262, 2009, Springer, 978-3-642-04874-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Recreational Sports Instruction, Fuzzy Inference Mechanism, Expert System |
50 | Chris J. Michael, Maciej Brodowicz, Thomas L. Sterling |
Improving code compression using clustered modalities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 46th Annual Southeast Regional Conference, 2008, Auburn, Alabama, USA, March 28-29, 2008, pp. 423-428, 2008, ACM, 978-1-60558-105-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
data clustering, code compression, instruction set architecture |
50 | Arvind Krishnaswamy, Rajiv Gupta 0001 |
Enhancing the performance of 16-bit code using augmenting instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03). San Diego, California, USA, June 11-13, 2003, pp. 254-264, 2003, ACM, 1-58113-647-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
16-bit thumb ISA, 32-bit ARM ISA, AX instructions, instruction coalescing, performance, embedded processor, code size |
49 | Pairoj Trirathanakul, Suwanna Sombunsukho, Suriyong Lertkulvanich, Nithi Buranajant |
An Effective Construction of Computer Assisted Lesson Based on Interactive Multimedia Computer Assisted Instruction Theory (IMMCAI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education ![In: Innovative Techniques in Instruction Technology, E-learning, E-assessment, and Education, Proceedings of the 2007 International Conference on Engineering Education, Instructional Technology, Assessment, and E-learning (EIAE 2007), part of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2007), Bridgeport, CT, USA, December 3-12, 2007, pp. 526-531, 2008, Springer, 978-1-4020-8738-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(1), pp. 9:1-9:37, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
48 | Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura |
Energy-efficient dynamic instruction scheduling logic through instruction grouping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 43-48, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction grouping, issue queue, dynamic instruction scheduling |
48 | Jack Liu, Fred C. Chow |
A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 9-18, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
48 | Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi |
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 120-125, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure |
47 | Ahmad Zmily, Christos Kozyrakis |
Energy-efficient and high-performance instruction fetch using a block-aware ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 36-41, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
basic blocks, energy efficiency, instruction set architecture, decoupled architecture, instruction delivery |
47 | Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao |
Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(1), pp. 4-20, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures |
47 | Jack Liu, Fred C. Chow, Timothy Kong, Rupan Roy |
Variable Instruction Set Architecture and Its Compiler Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(7), pp. 881-895, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling |
47 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Energy-efficient instruction set synthesis for application-specific processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 330-333, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product |
46 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Efficient instruction encoding for automatic instruction set design of configurable ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 649-654, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Demid Borodin, Ben H. H. Juurlink |
Protective redundancy overhead reduction using instruction vulnerability factor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 319-326, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
instruction vulnerability, selective protection, performance, redundancy, fault detection |
46 | Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec |
Generalized instruction selection using SSA-graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 31-40, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pbqp, compiler, code generation, instruction selection |
46 | Martina Ziefle |
Instruction Formats and Navigation Aids in Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USAB ![In: HCI and Usability for Education and Work, 4th Symposium of the Workgroup Human-Computer Interaction and Usability Engineering of the Austrian Computer Society, USAB 2008, Graz, Austria, November 20-21, 2008. Proceedings, pp. 339-358, 2008, Springer, 978-3-540-89349-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Instruction format, navigation effectiveness, landmark knowledge, route knowledge, survey knowledge, efficiency, navigation aid |
46 | Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero |
Kilo-instruction processors, runahead and prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 269-278, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors |
46 | Ruby B. Lee, A. Murat Fiskiran |
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(1), pp. 85-108, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multimedia, processor architecture, instruction set architecture, media processing, ISA |
46 | Eric Rotenberg, Steve Bennett, James E. Smith 0001 |
A Trace Cache Microarchitecture and Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(2), pp. 111-120, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching |
46 | Shengning Wu, Sikun Li |
Instruction Selection for ARM/Thumb Processors Based on a Multi-objective Ant Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSR ![In: Computer Science - Theory and Applications, First International Symposium on Computer Science in Russia, CSR 2006, St. Petersburg, Russia, June 8-12, 2006, Proceedings, pp. 641-651, 2006, Springer, 3-540-34166-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min |
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 8th International Workshop, SCOPES 2004, Amsterdam, The Netherlands, September 2-3, 2004, Proceedings, pp. 244-258, 2004, Springer, 3-540-23035-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson |
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 33-48, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Eunlim Chi, Chanjung Park, Hwakyung Rim |
Evaluating the Web-Based Instruction by Item Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2003, International Conference, Montreal, Canada, May 18-21, 2003, Proceedings, Part II, pp. 901-908, 2003, Springer, 3-540-40161-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
An instruction-level energy model for embedded VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9), pp. 998-1010, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta |
Instruction fetch deferral using static slack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 51-61, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
46 | Glenn Reinman, Brad Calder, Todd M. Austin |
Fetch Directed Instruction Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 16-27, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
46 | Toshinori Sato |
Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 1281-1290, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
45 | Ramón D. Acosta, Jacob Kjelstrup, Hwa C. Torng |
An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(9), pp. 815-828, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
processor performance enhancement, Dispatch stack, instruction issuing, instruction unit, multiple functional unit processors, multiple instruction dispatching, dynamic instruction scheduling |
45 | James Leslie Keedy |
An Instruction Set for Evaluating Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(5), pp. 476-478, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
stack-based instruction sets, instruction set optimization, memory-to-memory instruction sets, Code compactness, expression evaluation, instruction set design |
44 | Hai Lin 0004, Yunsi Fei |
A novel multi-objective instruction synthesis flow for application-specific instruction set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 409-412, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
instruction set synthesis, application-specific instruction set processor (ASIP) |
44 | Ing-Jer Huang |
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(1), pp. 93-121, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
compiler instruction optimization, instruction set processor, pipeline hazards, pipeline taxonomy, synthesis |
43 | Daniel Christopher Powell, Björn Franke |
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 315-324, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
continuous statistical machine learning, performance prediction, instruction set simulator |
43 | Tobias J. K. Edler von Koch, Igor Böhm, Björn Franke |
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Proceedings of the CGO 2010, The 8th International Symposium on Code Generation and Optimization, Toronto, Ontario, Canada, April 24-28, 2010, pp. 180-189, 2010, ACM, 978-1-60558-635-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ARCompact, dual instruction set architecture, variable-length instructions, register allocation, code size, instruction selection |
43 | Yulai Zhao 0003, Xianfeng Li, Dong Tong 0001, Xu Cheng 0001 |
An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(1), pp. 15-24, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
content associative memory (CAM), tag elimination, waiting instruction buffer, instruction scheduler, energy-efficient architecture |
43 | Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero |
A first glance at Kilo-instruction based multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 212-221, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ROB, in-flight instructions, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, Kilo-instruction processors |
43 | Aneesh Aggarwal, Manoj Franklin |
Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 46-55, 2003, IEEE Computer Society, 0-7695-2021-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Instruction Replication, Inter-PE communication, Instruction Distribution, Instructions per Cycle, Load Imbalance, Clustered processors |
43 | Marco Antonio Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero |
A Simple Low-Energy Instruction Wakeup Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings, pp. 99-112, 2003, Springer, 3-540-20359-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Instruction wake up, Low power, Superscalar processors, Out of order execution, CAM, Instruction window |
43 | Shyh-Kwei Chen, W. Kent Fuchs |
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(12), pp. 1293-1304, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry |
43 | David A. Dunn, Wei-Chung Hsu |
Instruction Scheduling for the HP PA-8000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 298-307, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
HP PA-8000, instruction polarity cache interfaces, memory dependences, production compiler, scheduling, latency, compiler optimization, instruction scheduling, resource constraints, micro-architecture |
42 | Kazuaki J. Murakami, Naohiko Irie, Morihiro Kuga, Shinji Tomita |
SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 78-85, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
42 | Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt |
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 20:1-20:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation |
42 | David Ryan Koes, Seth Copen Goldstein |
Near-optimal instruction selection on dags. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Sixth International Symposium on Code Generation and Optimization (CGO 2008), April 5-9, 2008, Boston, MA, USA, pp. 45-54, 2008, ACM, 978-1-59593-978-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instruction selection |
42 | Ramkumar Jayaseelan, Haibin Liu, Tulika Mitra |
Exploiting forwarding to improve data bandwidth of instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 43-48, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction-set extensions, data forwarding |
42 | Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam |
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 376-386, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Complexity-effective design, Temporal Redundancy, Instruction Reuse |
42 | G. Surendra, Subhasis Banerjee, S. K. Nandy 0001 |
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 31(6), pp. 469-487, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multiprocessors, network processors, value prediction, instruction reuse |
42 | Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick |
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 13-27, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
architectural verification, biased random instruction generation, correctness checking, design error coverage, design verification, coverage metrics |
42 | Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark |
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(11), pp. 1260-1281, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction window size, register-update unit, simulation, cache, sampling, branch prediction, Microarchitecture, trade-offs, out-of-order execution |
42 | Stephen Hines, David B. Whalley, Gary S. Tyson |
Adapting compilation techniques to enhance the packing of instructions into registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 43-53, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction packing, instruction register file, compiler optimizations |
42 | Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim |
DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1343-1348, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte |
Power-efficient Instruction Encoding Optimization for Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 595-600, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Hai-Chen Wang, Chung-Kwong Yuen |
Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Dinesh C. Suresh, Walid A. Najjar, Jun Yang 0002 |
Power Efficient Instruction Caches for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 182-191, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon |
Energy estimation and optimization of embedded VLIW processors based on instruction clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 886-891, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
power estimation, vliw architectures |
42 | Heidi Pan, Krste Asanovic |
Heads and tails: a variable-length instruction format supporting parallel fetch and decode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 168-175, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | P.-H. Chang, Wen-mei W. Hwu |
Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 188-198, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
42 | Wen-mei W. Hwu, Pohua P. Chang |
Achieving High Instruction Cache Performance with an Optimizing Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 242-251, 1989, ACM, 0-89791-319-1. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
42 | Jack W. Davidson, Richard A. Vaughan |
The Effect of Instruction Set Complexity on Program Size and Memory Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987., pp. 60-64, 1987, ACM Press, 0-8186-0805-6. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
41 | Arvind Krishnaswamy, Rajiv Gupta 0001 |
Efficient Use of Invisible Registers in Thumb Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 30-42, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
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