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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1038 occurrences of 719 keywords
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Results
Found 1324 publication records. Showing 1324 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
52 | Stanley E. Lass |
Automated printed circuit routing with a stepping aperture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 12(5), pp. 262-265, 1969. The full citation details ...](Pics/full.jpeg) |
1969 |
DBLP DOI BibTeX RDF |
circuit board, printed circuit, stepping aperture, routing, interconnections, lines, computer program, vias, pins, aperture |
52 | Yongseok Cheon, Martin D. F. Wong |
Crowdedness-balanced multilevel partitioning for uniform resource utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 418-423, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Bruce C. Kim, Abhijit Chatterjee, Madhavan Swaminathan |
Low-cost diagnosis of defects in MCM substrate interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 260-265, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
low-cost diagnosis, MCM substrate interconnections, substrate interconnect defects, defect location, defect size, fault diagnosis, integrated circuit testing, fault location, multichip modules, integrated circuit interconnections, fault-dictionary, substrates |
43 | Shinichi Shionoya, Takafumi Aoki, Tatsuo Higuchi 0001 |
Multiwave Interconnection Networks for MCM-based Parallel Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '95 Parallel Processing, First International Euro-Par Conference, Stockholm, Sweden, August 29-31, 1995, Proceedings, pp. 593-607, 1995, Springer, 3-540-60247-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Multichip module (MCM), messagepassing multiprocessors, parallel processing, interconnection networks, optical interconnections, wavelength division multiplexing (WDM) |
43 | Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee |
Physical models and algorithms for optoelectronic MCM layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 124-135, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
42 | Dohoon Kim |
An architecture for internet inter-domain interconnections and bandwidth trading towards effective NGN deployment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. des Télécommunications ![In: Ann. des Télécommunications 63(11-12), pp. 607-619, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Internet interconnections, Bandwidth trading, Hub-and-spoke network, Network operations and management, NGN, Inter-Domain routing, End-to-end QoS, Network economics |
42 | Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals |
A High-Speed Optical Multi-Drop Bus for Computer Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 3-10, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus |
42 | Jae-dong Lee, Kenneth E. Batcher |
A bitonic sorting network with simpler flip interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 104-109, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
flip interconnections, bitonic sorting network, inter-level wiring, parity technique, Construct-BSMF, N/2 even-parity keys, interconnection scheme, perfect-shuffle interconnection, parallel algorithms, parallel architectures, multiprocessor interconnection networks, sorting |
42 | Alex Fit-Florea, Miroslav Halás, Fatih Kocan |
Enhancing Reliability of Operational Interconnections in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 746-747, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst |
Silicon VLSI processing architectures incorporating integrated optoelectronic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 17-27, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si |
35 | X. Cai, Keith Nabors, Jacob K. White 0001 |
Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 200-213, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
piecewise constant techniques, permittivity, Galerkin techniques, multipole-accelerated capacitance extraction, multiple dielectrics, arbitrary piecewise-constant dielectric medium, IC interconnections, VLSI, VLSI, integrated circuit design, circuit CAD, boundary-elements methods, boundary element method, capacitance, integrated circuit interconnections, Galerkin method, capacitance extraction, 3D structures |
35 | T. A. García, Antonio J. Acosta 0001, J. M. Mora, J. Ramos, José Luis Huertas |
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(1-2), pp. 115-127, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
self-timed CMOS design, testing interconnections, boundary-scan, MCM testing |
35 | Guy Even, Ami Litman |
Overcoming chip-to-chip delays and clock skews. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 199-208, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews |
34 | Simon M. Kaplan, Steven K. Goering |
Garp: a graphical/textual language for concurrent programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA/ECOOP Workshop on Object-based Concurrent Programming ![In: Proceedings of the 1988 ACM SIGPLAN Workshop on Object-based Concurrent Programming, OOPSLA/ECOOP Workshop on Object-based Concurrent Programming 1988, San Diego, CA, USA, September 26-27, 1988, pp. 184-186, 1988, ACM, 978-0-89791-304-1. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
34 | Jianping Quan, Guoqiang Bai 0001 |
A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 58-63, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
WDDL, TDPL, NSDDL, unbalanced interconnections, early propagation effect, routing |
34 | Yitzhak Birk, Noam Bloch |
The effects of destructive interference and wasted transmissions on the uniform-traffic capacity of non-bus-oriented single-hop interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 4(3), pp. 442-448, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
fiber optic networks, shared directional multichannel, single-hop interconnections, local area networks, capacity, multiple access |
34 | Joe Kilian, Shlomo Kipnis, Charles E. Leiserson |
The Organization of Permutation Architectures with Bused Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1346-1358, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
permutation architectures, bused interconnections, abelian, combinatorial notion, multiprocessor interconnection networks, VLSI chips |
33 | Weisheng Chen, Junmin Li |
Decentralized Output-Feedback Neural Control for Systems With Unknown Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Part B ![In: IEEE Trans. Syst. Man Cybern. Part B 38(1), pp. 258-266, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Global interconnections in FPGAs: modeling and performance analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 51-58, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, throughput, interconnection, wave-pipelined |
33 | Yuriy Sheynin, Elena Suvorova, Felix Shutenko |
Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 283-288, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Ming Cong, Sunan Huang 0002 |
Neural Network Control Design for Large-Scale Systems with Higher-Order Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part II, pp. 1007-1012, 2006, Springer, 3-540-34437-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Chen Dong 0003, S. Haruehanroengra, Wei Wang 0003 |
Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Rajesh Pendurkar, Craig A. Tovey, Abhijit Chatterjee |
Single-probe traversal optimization for testing of MCM substrate interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1178-1191, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Mario R. Casu, Luca Macchiarulo |
Adaptive Latency-Insensitive Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 442-452, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
latency-insensitive protocols, interconnections, ICs, wire pipelining |
26 | Arjan Durresi, Gojko Babic, Raj Jain |
Measurement of ATM Frame Latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: Proceedings 27th Conference on Local Computer Networks, Tampa, Florida, USA, 8-10 November, 2000, pp. 614-619, 2000, IEEE Computer Society, 0-7695-0912-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
ATM frame latency measurement, MIMO latency, message-in message-out latency, latency metrics, continuous frame technologies, measurement results, switch performance, MIMO aggregation, network element, network interconnections, quality of service, asynchronous transfer mode, MIMO systems, telecommunication networks, QoS parameters, network devices |
26 | Maria Brielmann, Joachim Stroop, Uwe Honekamp, Peter Wältermann |
Simulation of hybrid mechatronic systems: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 1997 Workshop on Engineering of Computer-Based Systems (ECBS '97), March 24-28, 1997, Monterey, CA, USA, pp. 256-263, 1997, IEEE Computer Society, 0-8186-7889-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
hybrid mechatronic systems, continuous system parts, discrete system parts, car electric windows, extended predicate/transition nets, hardware-in-the-loop simulation, hybrid simulation parallelisation, interconnections, complex systems, DSL, automaton, mechatronics, specification techniques, block diagram, simulation techniques |
26 | V. B. Fyodorov |
Bit-Parallel Selfrouting Optoelectronic Switching Fabrics for Massively Parallel Wide-Format Data Processing: Principle and Optical Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 479-486, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Free space optical interconnections, Completely connected networks, Smart pixel arrays, VCSEL technology |
26 | Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh |
The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 74-84, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention |
26 | Sajal K. Das 0001, Sanjoy K. Sen |
Analysis of Memory Interference in Buffered Multiprocessor Systems in Presence of Hot Spots and Favorite Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 281-285, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
buffered multiprocessor systems, discrete Markov chain model, processor-memory interconnections, hot memory, favorite memory, mean queue length, memory request, asymptotic bandwidth, performance evaluation, Markov processes, shared memory systems, upper bound, hot spots, simulation studies, memory interference, mean waiting time |
26 | Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
Analytical delay models for VLSI interconnects under ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 30-36, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
SPICE-computed delay, VLSI routing topologies layout, analytical delay models, arbitrary interconnect trees, interconnect transfer function, performance-driven synthesis, ramp input, source-sink delays, VLSI, Elmore delay, interconnect delays, VLSI interconnects, RLC interconnections |
26 | Bradly K. Fawcett, J. Watson |
Reconfigurable Processing With Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 293-302, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays |
26 | Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov |
Designing an asynchronous pipeline token ring interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 32-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks |
26 | Sushil Aryal, James S. Meditch |
Design of a large ATM switch with trunk grouping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 406, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
load throughput value, dense VLSI implementation, large ATM switch with trunk grouping, LAST switch, IBSS, ideal bit by bit self routing switch, delay, topology, throughput, interconnections, communication complexity, modules, circuit complexity, cell loss |
26 | Alexander Dalal, Lavi Lev, Sundari Mitra |
Design of an efficient power distribution network for the UltraSPARC-I microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 118-123, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
computer power supplies, UltraSPARC-I, simulation method, exact layout locations, excessive voltage drop, floorplanning constraints, power interconnections, reduced time-to-market, circuit analysis computing, circuit layout CAD, microprocessor chips, electromigration, CAD tools, power distribution network |
26 | Sven Simon 0001, Ralf Bucher, Josef A. Nossek |
Retiming of synchronous circuits with variable topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 130-134, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
variable topology, combinational elements selection, circuit graph, optimization, graph theory, linear programming, delays, timing, interconnections, logic design, network topology, logic CAD, retiming, circuit CAD, circuit optimisation, synchronous circuits |
26 | C. V. Ramamoorthy, Yutaka Usuda, Atul Prakash 0001, Wei-Tek Tsai |
The Evolution Support Environment System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(11), pp. 1225-1234, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
evolution support environment system, ESE system, integrated support, software architecture configuration, life-cycle configuration, software objects, design, specifications, software development, management, programming environments, interconnections, software components, traceability, code, version control, test cases, semantic information, evolving software system |
26 | Nahri Moreano, Edson Borin, Cid C. de Souza, Guido Araujo |
Efficient datapath merging for partially reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 969-980, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich |
Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11110-11111, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Chittaranjan A. Mandal, R. M. Zimmer |
A Genetic Algorithm for the Synthesis of Structured Data Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 206-211, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation |
26 | Stuart K. Tewksbury, Lawrence A. Hornak |
Optical Clock Distribution in Electronic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 225-246, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Debashis Basak, Dhabaleswar K. Panda 0001 |
Designing Clustered Multiprocessor Systems under Packaging and Technological Advancements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(9), pp. 962-978, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
k-ary n-cube interconnection, packaging constraints, interconnection networks, parallel architectures, Multiprocessor systems, clustered architectures, hierarchical organization, scalable systems |
26 | Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson |
LILA: layout generation for iterative logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11), pp. 1359-1369, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
25 | Ulf Jönsson, Michael Cantoni, Chung-Yao Kao |
On structured robustness analysis for feedback interconnections of unstable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CDC ![In: Proceedings of the 47th IEEE Conference on Decision and Control, CDC 2008, December 9-11, 2008, Cancún, Mexico, pp. 351-356, 2008, IEEE, 978-1-4244-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Rami G. Melhem |
Low Diameter Interconnections for Routing in High-Performance Parallel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(4), pp. 502-510, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fixed diameter graphs, low diameter networks, Interconnection networks, directed graphs, circuit switching, deterministic routing |
25 | Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri |
Yield prediction for 3D capacitive interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 809-814, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Roberto Navigli, Paola Velardi |
Structural Semantic Interconnections: A Knowledge-Based Approach to Word Sense Disambiguation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 27(7), pp. 1075-1086, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Stefan Paal, Reiner Kammüller, Bernd Freisleben |
Self-Managing Remote Object Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEXA Workshops ![In: 15th International Workshop on Database and Expert Systems Applications (DEXA 2004), with CD-ROM, 30 August - 3 September 2004, Zaragoza, Spain, pp. 758-763, 2004, IEEE Computer Society, 0-7695-2195-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Grzegorz Tosik, Zbigniew Lisik, Malgorzata Langer, Frédéric Gaffiot, Ian O'Connor |
Simulation of Electrical and Optical Interconnections for Future VLSI ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part IV, pp. 1037-1044, 2004, Springer, 3-540-22129-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Guy Peterson |
Verification of Device Interface Hardware Interconnections Prior to the Start of Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 297-300, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Antonio Zenteno, Víctor H. Champac, Joan Figueras |
Detectability Conditions of Full Opens in the Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(2), pp. 85-95, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
logic testing, IDDQ testing, opens, defect modeling |
25 | Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo |
Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 702-705, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Andrea Carmignani, Giuseppe Di Battista, Walter Didimo, Francesco Matera, Maurizio Pizzonia |
Visualization of the Autonomous Systems Interconnections with HERMES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GD ![In: Graph Drawing, 8th International Symposium, GD 2000, Colonial Williamsburg, VA, USA, September 20-23, 2000, Proceedings, pp. 150-163, 2000, Springer, 3-540-41554-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang |
An Analytical Delay Model for SRAM-Based FPGA Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 101-104, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Qian Wang, Sotirios G. Ziavras |
Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99), 23-25 June 1999, Fremantle, Australia, pp. 222-229, 1999, IEEE Computer Society, 0-7695-0231-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
communication operations, parallel processing, Interconnection networks |
25 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
A distributed BIST technique for diagnosis of MCM interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 214-221, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | David C. Keezer, K. E. Newman, John S. Davis |
Improved sensitivity for parallel test of substrate interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 228-233, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Adam Kristof |
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 630, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Shin-ichiro Tago, Shuichi Ueno |
Optimal Realization of Hypercubes by Three-Dimensional Space-Invariant Optical Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 44-48, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Chung-Sheng Li, Harold S. Stone, Young Kwark, C. Michael Olsen |
Fully differential optical interconnections for high-speed digital systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 151-163, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
25 | Dilip K. Bhavsar |
Testing Interconnections to Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 8(2), pp. 63-71, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
25 | Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen |
Three-dimensional capacitance computations for VLSI/ULSI interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12), pp. 1319-1326, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
25 | Zhen-qiu Ning, Patrick M. Dewilde |
SPIDER: capacitance modelling for VLSI interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12), pp. 1221-1228, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Shoaib Kamil 0001, Leonid Oliker, Ali Pinar, John Shalf |
Communication Requirements and Interconnect Optimization for High-End Scientific Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 21(2), pp. 188-202, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance analysis, topology, Interconnections |
17 | Torsten Hoefler |
Software and Hardware Techniques for Power-Efficient HPC Networking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Sci. Eng. ![In: Comput. Sci. Eng. 12(6), pp. 30-37, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
power-efficient HPC, interconnections networks, large-scale networks, Green networking |
17 | Olav Lysne, José Miguel Montañana, José Flich, José Duato, Timothy Mark Pinkston, Tor Skeie |
An Efficient and Deadlock-Free Network Reconfiguration Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(6), pp. 762-779, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interconnections (Subsystems), Topology, I/O and Data Communications |
17 | Madeleine Glick |
Optical Interconnects in Next Generation Data Centers: An End to End View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA, pp. 178-181, 2008, IEEE Computer Society, 978-0-7695-3380-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
computer networks, optical interconnections, optical switches |
17 | Assaf Shacham, Keren Bergman |
Building Ultralow-Latency Interconnection Networks Using Photonic Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(4), pp. 6-20, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multiple data stream architectures, interconnections, processor architectures, I/O and data communication |
17 | Rodney Van Meter, Kae Nemoto, W. J. Munro |
Communication Links for Distributed Quantum Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(12), pp. 1643-1653, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Interconnections (Subsystems), Emerging technologies, Emerging technologies, Error-checking, Interconnection architectures |
17 | Jason D. Bakos, Donald M. Chiarulli, Steven P. Levitan |
Lightweight Error Correction Coding for System-Level Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(3), pp. 289-304, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Interconnections (subsystems), coding and information theory, error control codes, interconnection architectures, code design, coding tools and techniques |
17 | Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter |
Leveraging Wire Properties at the Microarchitecture Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 26(6), pp. 40-52, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnections, multiprocessor systems, interprocessor communications, energy-aware systems, interconnection architectures, advanced technologies |
17 | Alessandro Mei, Romeo Rizzi |
Online Permutation Routing in Partitioned Optical Passive Star Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(12), pp. 1557-1571, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
partitioned optical passive star network, Optical interconnections, permutation routing |
17 | Juan Rubio 0001, Lizy Kurian John |
Reducing Server Data Traffic Using a Hierarchical Computation Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(10), pp. 933-943, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
I/O interconnections topology, modeling, evaluation, databases, measurement, Distributed architectures, simulation of multiple-processor systems |
17 | Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret |
Impact of Low-K on Crosstalk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 298-303, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Low-k, interconnections, Crosstalk, electromagnetic analysis |
17 | Guoping Liu 0004, Kyungsook Y. Lee, Harry F. Jordan |
n-Dimensional Processor Arrays with Optical dBuses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 16(3), pp. 149-163, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
de Bruijn digraph, wavelength division multiplexing, optical interconnections, processor array, time division multiplexing |
17 | Brian Webb, Ahmed Louri |
A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 11(5), pp. 444-458, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
scalability, networks, parallel architectures, hypercubes, wavelength division multiplexing, Optical interconnections, crossbars, multiprocessor interconnection |
17 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 311-316, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
17 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
BIST TPG for SRAM cluster interconnect testing at board level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 58-65, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SRAM cluster interconnect testing, BIST TPG, static random access memory, board-level interconnects, test pattern generation architecture, IEEE 1149.1 boundary scan architecture, prohibited conditions, testable SRAM cluster interconnect fault detection, logic testing, built-in self test, automatic test pattern generation, test pattern generation, boundary scan testing, integrated circuit interconnections, SRAM chips, printed circuit testing |
17 | Abby A. Ilumoka |
Efficient prediction of interconnect crosstalk using neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTAI ![In: 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 13-15 November 2000, Vancouver, BC, Canada, pp. 122-125, 2000, IEEE Computer Society, 0-7695-0909-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect crosstalk prediction, deep submicron downscaling, wirecells, modular artificial neural networks, multiparadigm prototyping system, equicoupling contours, isocouples, transconductance amplifier, neural networks, delays, delay, finite element method, neural nets, crosstalk, experimental results, circuit CAD, finite element analysis, circuit simulation, circuit simulator, integrated circuit interconnections, wafer-scale integration, wafer scale integration |
17 | Prasasth Palnati, Mario Gerla, Emilio Leonardi |
Deadlock-free routing in an optical interconnect for high-speed wormhole routing networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 256-264, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high-speed wormhole routing networks, Supercomputer SuperNet, two-level hierarchical high-speed network, electronic mesh fabric, WDM optical backbone network, metropolitan area, campus area, backpressure hop-by-hop flow control mechanism, shufflenet multihop virtual topology, physical channels, up/down deadlock free routing scheme, bidirectional shufflenet, optical backbone, multiprocessor interconnection networks, network routing, virtual channels, wavelength division multiplexing, optical interconnections, optical interconnect, deadlock-free routing, deadlock prevention |
17 | I-Shyan Hwang |
Performance evaluation of a WDMA OIDSM multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 162-168, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
WDMA OIDSM, WDMA, photonic network, reservation requests, coherence level control signals, performance evaluation, performance evaluation, interconnection network, multiprocessor interconnection networks, shared memory multiprocessors, shared memory systems, distributed shared memory, distributed memory systems, wavelength division multiplexing, optical interconnections, optically interconnected, access protocols, media access protocol |
17 | Steven M. P. Yip, Nicholas Bambos |
Scalable routing schemes for massively parallel processing using reconfigurable optical interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 500-, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scalable routing schemes, reconfigurable optical interconnect, message broadcasting, massively parallel processing system, randomly generated packets, device capabilities, parallel processing, reconfigurable architectures, optical interconnections, message routing, massively parallel processing |
17 | Shigeki Shibayama, Kazumasa Hamaguchi, Toshiyuki Fukui, Yoshiaki Sudo, Tomohiko Shimoyama, Shuichi Nakamura |
An Optical Bus Computer Cluster with a deferred cache coherence protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 175-182, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Optical Bus Computer Cluster, deferred cache coherence protocol, optical star-coupler, one-hop simultaneous broadcasting, wavelength multiplexing, deferred cache coherence, coherence maintenance, protocols, wavelength-division multiplexing, optical interconnections, cache storage |
17 | Mounir Hamdi, J. Tong, C. W. Kin |
Fast sorting algorithms on reconfigurable array of processors with optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 183-188, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm |
17 | Lutz J. Micheel, Hans L. Hartnagel |
Interband RTDs with Nanoelectronic HBT-LED Structures for Multiple-Valued Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 80-85, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
heterojunction bipolar transistors, resonant tunnelling devices, light emitting devices, interband RTDs, resonant tunnelling devices, nanoelectronic HBT-LED structures, multiple-valued computation, nanoelectronic arrays, complex signal processing methods, HBT-LED-RTD circuitry, heterojunction bipolar transistors, light emitting devices, internal optical methods, signal summation, precision photon streams, positive-digit radix-2 MVL, A/D conversion capability, optical isolation, buried optical interconnects, microcavity lasers, signal processing, optical interconnections, optical interconnects, multiple-valued logic, multivalued logic circuits, thresholding functions, analogue-digital conversion |
17 | Wei-Kang Huang, Xiao-Tao Chen, Fabrizio Lombardi |
On the diagnosis of programmable interconnect systems: Theory and application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 204-211, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
field programmable interconnect system, switch grid, FPIS, Xilinx 3000, field programmable gate arrays, FPGA, fault diagnosis, logic testing, diagnosis, integrated circuit interconnections |
17 | Lizy Kurian John |
VaWiRAM: a variable width random access memory module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 219-224, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
17 | Santonu Sarkar, Anupam Basu, Arun K. Majumdar |
Representation and Synthesis of Interface of a Circuit for its Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 140-145, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VaWiRAM, variable width random access memory, flexible memory systems, configuration pins, pass gates, reconfigurability, reconfigurable architectures, memory architecture, programmable logic, random-access storage, integrated circuit interconnections, programmable logic devices, programmable interconnect |
17 | Mounir Hamdi, Yi Pan 0001 |
Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 440-446, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations |
17 | Gregory Gravenstreter, Rami G. Melhem, Donald M. Chiarulli, Steven P. Levitan, James P. Teza |
The Partitioned Optical Passive Stars (POPS) topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 4-10, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optical couplers, Partitioned Optical Passive Stars topology, POPS topology, multiple data channels, all-optical interconnection architecture, multiple nonhierarchical couplers, power budget, control overhead, random communication patterns, performance evaluation, optimization, parallel architectures, optimisation, multiprocessor interconnection networks, configurability, reconfigurable architectures, high performance, optical interconnections, network throughput, large systems, system complexity |
17 | Mike Chou, Jacob K. White 0001 |
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 40-44, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Arnoldi method, SPICE-level simulation, Taylor series terms, surface-volume methods, three-dimensional interconnect, circuit analysis computing, transient analysis, integrated circuit interconnect, integrated circuit interconnections, reduced-order modeling, reduced-order models, transient simulation, series (mathematics) |
17 | Steven E. Butner, David A. Skirmont |
Architecture and design of a 40 gigabit per second ATM switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 352-357, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATM links, buffering scheme, 40 Gbit/s, asynchronous transfer mode, multiprocessor interconnection networks, optical interconnections, ATM switch, optical communication, switch architecture |
17 | Nikolaos G. Bourbakis, Mohammad Mortazavi |
An efficient building block layout methodology for compact placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 118-123, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
building block layout methodology, compact placement, synthesis placement, GEOMETRIA, geometric reshapings, VLSI regulation, functional performance, connection lines, occupied chip area, neighboring relations, dead space, open holes, channels merging process, legal overlapping, VLSI, formal languages, formal language, network routing, circuit layout CAD, compaction, global routing, integrated circuit layout, integrated circuit interconnections, local routing |
17 | Tong Liu 0007, Fabrizio Lombardi, José Salinas |
Diagnosis of interconnects and FPICs using a structured walking-1 approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 256-261, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections |
17 | Patrick W. Dowd, James A. Perreault, John C. Chu, David C. Hoffmeister, Dan Crouse |
LIGHTNING: A Scalable Dynamically Reconfigurable Hierarchical WDM Network for High-Performance Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 4th International Symposium on High Performance Distributed Computing (HPDC '95), Washington, DC, USA, August 2-4, 1995., pp. 220-229, 1995, IEEE Computer Society, 0-8186-7088-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scalable dynamically reconfigurable hierarchical WDM network, high-performance clustering, supercomputer interconnection, optical network testbed, distributed shared memory environment, single-hop all-optical communication, n-level hierarchy, highly fault tolerant system behavior, memory interface, optical devices, scalability, parallel processing, reconfigurable architectures, system architecture, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, optical information processing, LIGHTNING, traffic intensities |
17 | Anirudh Devgan, Ronald A. Rohrer |
Efficient simulation of interconnect and mixed analog-digital circuits in ACES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 229-233, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation |
17 | S. Y. Kulkarni, K. D. Patil, K. V. V. Murthy |
Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 260-263, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
very high speed integrated circuits, transmission line theory, integrated circuit packaging, transmission line model parameters, very high speed VLSI interconnects, higher order isoparametric elements, 2D interconnect/dielectric packaging structures, quadrilateral infinite elements, signal conductor boundaries, sharp corners, finite element method, finite element analysis, computation time, multichip modules, multichip modules, FEM, MCM, integrated circuit interconnections, VLSI interconnects |
17 | P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
VLSI floorplan generation and area optimization using AND-OR graph search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 370-375, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph |
17 | Dinesh Bhatia, James Haralambides |
Resource requirements for field programmable interconnection chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 376-380, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
field programmable interconnection chips, n-permutation graph, network property, routing delays, programmable switches, routing paths, specific I/O permutations, user-configured interconnection, VLSI, VLSI, graph theory, network routing, permutation networks, integrated circuit interconnections, Benes network |
17 | Patrick W. Dowd, Kalyani Bogineni, Khaled A. Aly, James A. Perreault |
Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(9), pp. 1105-1120, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
photonic architectures, optical structures, processor interconnection, single-hop, optical fiber communication, parallel architectures, discrete-event simulation, discrete event simulation, analytic models, wavelength division multiplexing, wavelength division multiplexing, optical interconnections, hierarchical, parallel computer architecture, hierarchical architectures |
17 | Wen-Jing Hsu |
Fibonacci Cubes-A New Interconnection Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(1), pp. 3-12, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
subgraph embedding, recurrent structures, sparse interconnections, Boolean cube, supergraph, node connectivity, system communication primitives, graph theory, fault-tolerant computing, topology, hypercube, multiprocessorinterconnection networks, interconnection topology, Fibonacci cube |
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