Search results for "BIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Christophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault	A Ring Architecture Strategy for BIST Test Pattern Generation.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	pseudo-random testing, deterministic BIST, logic BIST
47	Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig	Mixed-Mode BIST Using Embedded Processors.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	random pattern testing, embedded systems, BIST, deterministic BIST
47	Vishal Suthar, Shantanu Dutt	Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults.	DATE	2006	DBLP DOI BibTeX RDF
47	Baosheng Wang, Yuejian Wu, André Ivanov	Designs for Reducing Test Time of Distributed Small Embedded SRAMs.	DFT	2004	DBLP DOI BibTeX RDF	Distributed Small Embedded SRAMs, Data Retention Fault Test, Response Analysis, Test Time
47	Chien-In Henry Chen, Kiran George	Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns.	ISQED	2003	DBLP DOI BibTeX RDF
47	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
45	Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara	A memory grouping method for sharing memory BIST logic.	ASP-DAC	2006	DBLP DOI BibTeX RDF
45	Milos Krstic, Eckhard Grass	BIST Technique for GALS Systems.	DSD	2005	DBLP DOI BibTeX RDF
45	Danghui Wang, Xiaoya Fan, Deyuan Gao, Shengbing Zhang, Jianfeng An	Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.	ICESS	2005	DBLP DOI BibTeX RDF
45	Mohammed Y. Niamat, Surya S. Hejeebu, Mansoor Alam	A BIST Approach for Testing FPGAs Using JBITS.	FCCM	2005	DBLP DOI BibTeX RDF
45	Lei Li 0036, Krishnendu Chakrabarty	Test set embedding for deterministic BIST using a reconfigurable interconnection network.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
45	Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos	Multiphase BIST: a new reseeding technique for high test-data compression.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
45	Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng	A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
45	Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk	Memory BIST Using ESP.	VTS	2004	DBLP DOI BibTeX RDF
45	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
45	Qiushuang Zhang, Ian G. Harris	Partial BIST insertion to eliminate data correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
45	Chien-In Henry Chen, Kiran George	Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].	ISCAS (5)	2003	DBLP DOI BibTeX RDF
45	Lei Li 0036, Krishnendu Chakrabarty	Deterministic BIST Based on a Reconfigurable Interconnection Network.	ITC	2003	DBLP DOI BibTeX RDF
45	Rubin A. Parekhji	Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.	VLSI Design	2003	DBLP DOI BibTeX RDF
45	Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi	Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE.	DFT	2002	DBLP DOI BibTeX RDF
45	Miron Abramovici, Charles E. Stroud	BIST-based test and diagnosis of FPGA logic blocks.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
45	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Introducing redundant computations in RTL data paths for reducing BIST resources.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	behavioral synthesis built-in self-test, redundant operations, data flow graphs
45	Dongkyu Youn, Taehyung Kim, Sungju Park	A Microcode-Based Memory BIST Implementing Modified March Algorithm.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
45	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
45	Yuejian Wu, Saman Adham	Scan-based BIST fault diagnosis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
45	Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang	A Programmable BIST Core for Embedded DRAM.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
45	Qiushuang Zhang, Ian G. Harris	Partial BIST insertion to eliminate data correlation.	ICCAD	1999	DBLP DOI BibTeX RDF
45	Xiaowei Li 0001, Paul Y. S. Cheung	An approach to behavioral synthesis for loop-based BIST.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
45	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Scheduling and Module Assignment for Reducing Bist Resources.	DATE	1998	DBLP DOI BibTeX RDF	Built-in Self-test, High-level synthesis
45	José M. Miranda	A BIST and Boundary-Scan Economics Framework.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
45	Shambhu J. Upadhyaya, John A. Thodiyil	BIST PLAs, Pass or Fail - A Case Study.	DAC	1990	DBLP DOI BibTeX RDF
45	Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya	BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays.	DAC	1987	DBLP DOI BibTeX RDF
44	Zhanglei Wang, Krishnendu Chakrabarty	Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	nanofabric, CAEN, chemically assembled, reconfiguration, BIST, nanotechnology, defect tolerance, molecular electronics
44	Sunil Rafeeque, Vinita Vasudevan	A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	digital to analog converters, nonlinearity test, analog testing, mixed-signal BIST
44	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.	DSD	2004	DBLP DOI BibTeX RDF	BIST insertion, wiring area, test synthesis
42	Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens	Reversible online BIST using bidirectional BILBO.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	bilbo, bist, testing, reversible logic
42	Stephen K. Sunter, Aubin Roy	Noise-Insensitive Digital BIST for any PLL or DLL.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL
42	Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers	Deterministic Logic BIST for Transition Fault Testing.	ETS	2006	DBLP DOI BibTeX RDF	Deterministic logic BIST, delay test
42	Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento	Low Cost BIST for Static and Dynamic Testing of ADCs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	ADC BIST, noise based testing, mixed-signal test
42	Nicola Nicolici, Bashir M. Al-Hashimi	Testability Trade-Offs for BIST Data Paths.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	power-constrained test, BIST
42	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
42	Hongjoong Shin, Hak-soo Yu, Jacob A. Abraham	LFSR-based BIST for analog circuits using slope detection.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	slope detection, BIST, LFSR, analog testing, mixed-signal testing
42	L. Cassol, O. Betat, Luigi Carro, Marcelo Lubaszewski	The SigmaDelta-BIST Method Applied to Analog Filters.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	BIST, analog test, mixed signal testing, sigma-delta modulator
42	Takahisa Hiraide, Kwame Osei Boateng, Hideaki Konishi, Koichi Itaya, Michiaki Emori, Hitoshi Yamanaka, Takashi Mochiyama	BIST-Aided Scan Test - A New Method for Test Cost Reduction.	VTS	2003	DBLP DOI BibTeX RDF	ATPG, BIST, fault coverage, ATE, test cost reduction
42	Ilia Polian, Bernd Becker 0001	Stop & Go BIST.	IOLTW	2002	DBLP DOI BibTeX RDF	Thermal constraints, BIST, Delay testing, IP cores
42	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
42	Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston	Effective diagnostics through interval unloads in a BIST environment.	DAC	2002	DBLP DOI BibTeX RDF	fault diagnosis, built-in self-test (BIST)
42	Janusz Sosnowski	Analyzing BIST Robustness.	DFT	2001	DBLP DOI BibTeX RDF	fault effects, BIST, fault simulation, signature analysis
42	Gundolf Kiefer, Hans-Joachim Wunderlich	Deterministic BIST with Partial Scan.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	deterministic scan-based BIST, partial scan
42	Bechir Ayari, Prab Varma	Test Cycle Count Reduction in a Parallel Scan BIST Environment.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	ATP6, fault sumulation, BIST
42	Lijian Li, Yinghua Min	An efficient BIST design using LFSR-ROM architecture.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	read-only storage, BIST design, LFSR-ROM architecture, built-in self test, logic design, automatic test pattern generation, test pattern generation, integrated circuit design, shift registers, hardware overhead, ROM, integrated circuit economics
42	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations.	VTS	2000	DBLP DOI BibTeX RDF	BIST, Analog Test, Transient Analysis
42	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	General BIST-Amenable Method of Test Generation for Iterative Logic Arrays.	VTS	2000	DBLP DOI BibTeX RDF	fixed-coverage fixed-size test set, test generation, BIST, iterative logic arrays
42	Chauchin Su, Shyh-Jye Jou	Decentralized BIST Methodology for System Level Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, BIST, DFT, boundary scan
42	Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante	Optimal Vector Selection for Low Power BIST.	DFT	1999	DBLP DOI BibTeX RDF	Test, Low-Power, BIST
42	Rainer Dorsch, Hans-Joachim Wunderlich	Accumulator based deterministic BIST.	ITC	1998	DBLP DOI BibTeX RDF	hardware pattern generator, BIST, embedded cores
42	Patrick Girard 0001, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
42	Christian Dufaza, Hassan Ihs	A BIST-DFT technique for DC test of analog modules.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	current and voltage self-testing, Built-In Voltage Sensor, Built-In Self Test, Design For Testability, analog BIST
42	Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin	Fast fault simulation for BIST applications.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	signature computation, BIST applications, combinational fault simulation, BISTSIM, demand-driven logic simulation algorithm, fault propagation methods, bit-array computation, parallel-pattern sequential simulation, speedup ratio, VLSI, VLSI, logic testing, built-in self test, integrated circuit testing, combinational circuits, digital simulation, circuit analysis computing, aliasing, test patterns, MISR
42	Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich	Pattern generation for a deterministic BIST scheme.	ICCAD	1995	DBLP DOI BibTeX RDF	ATPG, BIST, Test Synthesis
42	Joan Carletta, Christos A. Papachristou	Testability analysis and insertion for RTL circuits based on pseudorandom BIST.	ICCD	1995	DBLP DOI BibTeX RDF	pseudorandom BIST, indirect feedback, preprocessing transformation, word-level correlation, modeling, logic testing, probability, built-in self test, built-in self-test, integrated circuit testing, Markov processes, automatic testing, Markov model, insertion, testability analysis, test point insertion, iterative technique, RTL circuits, register transfer level circuits
39	Alvernon Walker, Parag K. Lala	A Transition Based BIST Approach for Passive Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Built-in Self Test, Analog Test, Analog BIST, Mixed-Signal BIST
39	Michael Nicolaidis	Theory of Transparent BIST for RAMs.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	RAM test algorithms, transparent BIST, BIST, signature analysis, pattern sensitive faults, coupling faults
39	Mimi Yiu, Chris Winstead, Vincent C. Gaudet, Christian Schlegel	Digital built-in self-test of CMOS analog iterative decoders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
39	Vishal Suthar, Shantanu Dutt	High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
39	Abdil Rashid Mohamed, Zebo Peng, Petru Eles	A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead.	DELTA	2004	DBLP DOI BibTeX RDF
39	K. Y. Ko, Mike W. T. Wong, Yim-Shu Lee	Testing System-On-Chip by Summations of Cores? Test Output Voltages.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
39	Li Chen, Sujit Dey	Software-based self-testing methodology for processor cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
39	Janusz Rajski, Jerzy Tyszer	Modular logic built-in self-test for IP cores.	ITC	1998	DBLP DOI BibTeX RDF
39	Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik	Integration of partial scan and built-in self-test.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	test points, built-in self-test, design for testability, partial scan
37	Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar	WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.	VLSI Design	2009	DBLP DOI BibTeX RDF
37	Myung-Hoon Yang, YongJoon Kim, Sunghoon Chun, Sungho Kang 0001	An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Built-in self-test, Power consumption, Linear feedback shift register, Reseeding
37	Artur Jutman, Anton Tsertov, Raimund Ubar	Calculation of LFSR Seed and Polynomial Pair for BIST Applications.	DDECS	2008	DBLP DOI BibTeX RDF
37	Jie Qin, Charles E. Stroud, Foster F. Dai	Noise Figure Measurement Using Mixed-Signal BIST.	ISCAS	2007	DBLP DOI BibTeX RDF
37	Ioannis Voyiatzis	Embedding test patterns into Low-Power BIST sequences.	IOLTS	2007	DBLP DOI BibTeX RDF	Test set embedding, Gray sequences, Low power sequences, Built-In Self Test
37	Uthman Alsaiari, Resve A. Saleh	Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy.	ISQED	2007	DBLP DOI BibTeX RDF
37	Suresh Kumar Devanathan, Michael L. Bushnell	Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BIST.	VLSI Design	2007	DBLP DOI BibTeX RDF
37	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
37	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving test effectiveness of scan-based BIST by scan chain partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
37	Jee-Youl Ryu, Bruce C. Kim	Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	output DC voltage, built-in self-test, low noise amplifier, RFIC
37	Yongsheng Wang, Jinxiang Wang 0001, Fengchang Lai, Yizheng Ye	Optimal Schemes for ADC BIST Based on Histogram.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
37	Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu	A BIST Scheme for FPGA Interconnect Delay Faults.	VTS	2005	DBLP DOI BibTeX RDF
37	Ling Zhang, Jishun Kuang	A New BIST Solution for System-on-Chip.	PRDC	2005	DBLP DOI BibTeX RDF
37	Abhijit Jas, C. V. Krishna, Nur A. Touba	Weighted pseudorandom hybrid BIST.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
37	Andrew B. Kahng, Sherief Reda	Combinatorial group testing methods for the BIST diagnosis problem.	ASP-DAC	2004	DBLP DOI BibTeX RDF
37	Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara	Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
37	Guan-Xun Chen, Chung-Len Lee 0001, Jwu E. Chen	A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
37	Saman Adham, Benoit Nadeau-Dostie	A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.	MTDT	2004	DBLP DOI BibTeX RDF
37	Bryan Nelson, Mani Soma	On-chip calibration technique for delay line based BIST jitter measurement.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
37	Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura 0001	A BIST-based Charge Analysis for Embedded Memories.	IOLTS	2004	DBLP DOI BibTeX RDF	Current based testing, charge based testing, Embedded memories test, built-in current monitors
37	Gang Zeng, Hideo Ito	Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core.	VTS	2004	DBLP DOI BibTeX RDF
37	Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi	Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.	ITC	2004	DBLP DOI BibTeX RDF
37	Mitrajit Chatterjee, Dhiraj K. Pradhan	A BIST Pattern Generator Design for Near-Perfect Fault Coverage.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC
37	Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL Test Pattern Generation for High Quality Loosely Deterministic BIST.	DATE	2003	DBLP DOI BibTeX RDF
37	Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng	A Sigma-Delta Modulation Based BIST Scheme for A/D Converters.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
37	Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara	Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
37	Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita	A BIST Circuit for IDDQ Tests.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
37	Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen	BIST for clock jitter measurements.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
37	Bai Hong Fang, Nicola Nicolici	Power-Constrained Embedded Memory BIST Architecture.	DFT	2003	DBLP DOI BibTeX RDF
37	Kedarnath J. Balakrishnan, Nur A. Touba	Scan-Based BIST Diagnosis Using an Embedded Processor.	DFT	2003	DBLP DOI BibTeX RDF