Search results for "Current"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
31	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators.	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
30	Maged Marghany, Mazlan Hashim, Arthur P. Cracknell	Volterra Algorithm for Modelling Sea Surface Current Circulation from Satellite Altimetry Data.	ICCSA (2)	2008	DBLP DOI BibTeX RDF	JASON-1 satellite altimetry data, Volterra model, Lax-Wendorff schemes, Sea surface current, Finite element model
30	Dennis J. Ciplickas, Ronald A. Rohrer	Expected current distributions for CMOS circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	switching current, expected waveform, mean estimation, static analysis, statistical analysis, CMOS, autocorrelation, random processes, power spectral density
30	G. G. Somjen, H. Kager, Wytse J. Wadman	Calcium sensitive non-selective cation current promotes seizure-like discharges and spreading depression in a model neuron.	J. Comput. Neurosci.	2009	DBLP DOI BibTeX RDF	Calcium depletion, Calcium dependent current, Non-specific cation current, Seizure mechanisms, Spreading depression, Epilepsy
30	Mustafa Altun, Hakan Kuntman	High CMRR current mode operational amplifier with a novel class AB input stage.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	current-mode operational amplifier, current-mode circuits
30	Yu-Yau Guo, Jien-Chung Lo	Challenges of Built-In Current Sensor Designs.	DFT	1998	DBLP DOI BibTeX RDF	voltage regulator, built-in current sensor, Current testing, decoupling capacitor
30	Adriano M. Pereira, Tales Cleber Pimenta, Robson L. Moreno, Edgar Charry R., Alberto M. Jorge	Design of a Measurement and Interface Integrated Circuit for Characterization of Switched Current Memory Cells.	VLSI Design	1998	DBLP DOI BibTeX RDF	switched current, behaviour simulation, voltage-to-current converter
30	Josep Rius 0001, Joan Figueras	Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	I DDQ testability, Built-in Current Sensors, current testing
30	Shyang-Tai Su, Rafic Z. Makki, H. Troy Nagle	Transient power supply current monitoring - A new test method for CMOS VLSI circuits.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	Design for current-testability, drain/source opens, floating gates, shorts, transient power supply current
30	A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm.	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
29	André Mansano, Andre Vilas Boas, Alfredo Olmos, Jefferson Soldera	Zero quiescent current startup circuit with automatic turning-off for low power current and voltage reference.	SBCCI	2009	DBLP DOI BibTeX RDF	power-up, starter, initialization, start-up, current reference
29	Srinivas Bodapati, Farid N. Najm	High-level current macro-model for power-grid analysis.	DAC	2002	DBLP DOI BibTeX RDF	current macro-model, DCT, power grid
29	Annie A. M. Cuyt, Walter Krämer, Wolfram Luther, Peter W. Markstein	08021 Summary - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
29	Wolfram Luther, Annie A. M. Cuyt, Walter Krämer, Peter W. Markstein	08021 Abstracts Collection - Numerical Validation in Current Hardware Architectures.	Numerical Validation in Current Hardware Architectures	2008	DBLP BibTeX RDF
29	Amir Pnueli	Applications of Temporal Logic to the Specification and Verification of Reactive Systems: A Survey of Current Trends.	Current Trends in Concurrency	1986	DBLP DOI BibTeX RDF
29	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
29	John Johansen, Uday S. Karmarkar, Dhananjay Nanda, Abraham Seidmann	Business experience with computer integrated manufacturing. A survey of current strategy and practice.	HICSS (4)	1995	DBLP DOI BibTeX RDF	current strategy, current practice, business experience, US manufacturing firms, adoption policy, manufacturing process characteristics, CIM development process, CIM architecture, plant-wide integration, competitive missions, information technologies, value, strategic planning, computer integrated manufacturing, computer integrated manufacturing, benefits, temporal pattern, commerce
29	Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001	High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design
29	Takeshi Yamakawa, Tsutomu Miki	The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	semicustom IC, fuzzy computer, fuzzy integrated circuit, fuzzy logic array, fuzzy logic building block, MOS current mirror, ratioless circuit, Current mode circuit
28	Srdjan Dragic, Martin Margala	A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test.	ISVLSI	2002	DBLP DOI BibTeX RDF	Current Amplifier, On-Line Testing, Iddq, delta Iddq, Current Monitoring
28	Manoj Sachdev	SeparateIDDQ testing of signal and bias paths in CMOS ICs for defect diagnosis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	junction leakage current, diagnostics, deep sub-micron, I DDQ testing, subthreshold leakage current
27	Radu Muresan, Catherine H. Gebotys	Current flattening in software and hardware for security applications.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	current flattening, hardware architecture, power analysis attacks
27	Fei Li 0003, Lei He 0001, Kewal K. Saluja	Estimation of Maximum Power-Up Current.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	current estimation, ATPG algorithm, leakage reduction
27	Chintan Patel, Abhishek Singh 0001, Jim Plusquellic	Defect Detection Using Quiescent Signal Analysis.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	multiple current measurements, Quiescent Signal Analysis, IDDQ, current testing, defect-based testing, parametric testing
27	Sagar S. Sabade, D. M. H. Walker	Use of Multiple IDDQ Test Metrics for Outlier Identification.	VTS	2003	DBLP DOI BibTeX RDF	Current ratio, neighbor current ratio, outlier identification, spatial correlation, IDDQ testing
27	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Fully Source-Coupled Logic Based Multiple-Valued VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic
27	Mengmeng Du, Hoi Lee	A 2.5MHz, 97%-accuracy on-chip current sensor with dynamically-biased shunt feedback for current-mode switching DC-DC converters.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Qadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri	Low power startup circuits for voltage and current reference with zero steady state current.	ISLPED	2003	DBLP DOI BibTeX RDF	low power integrated circuits, startup circuit, voltage reference, current reference
26	Jader A. De Lima, Wallace A. Pimenta	A current limiter for DC/DC regulators with internal compensation for process and temperature.	SBCCI	2008	DBLP DOI BibTeX RDF	DC/DC converter, LDO, PVT compensation, current limitation, switcher
26	Jiri Misurec	Non-linear circuits with CCII+/-current conveyors. (PDF / PS)	PWC	2007	DBLP DOI BibTeX RDF	current conveyor, non-linear circuits, rectifiers
26	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
26	Thorsten Adler, Hiltrud Brocke, Lars Hedrich, Erich Barke	A current driven routing and verification methodology for analog applications.	DAC	2000	DBLP DOI BibTeX RDF	multiterminal signal nets, routing, verification, design methodology, Steiner tree, electromigration, current density
26	Javier Argüelles, Salvador Bracho	Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	mixed-signal IC testing, design for test in mixed-signal IC, built-in current sensors
26	Teruhiko Yamada, Tsuyoshi Sasaki	On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	4JL gate, Josephson logic circuit, current testing, defect coverage
26	Anne E. Gattiker, Wojciech Maly	Current signatures [VLSI circuit testing].	VTS	1996	DBLP DOI BibTeX RDF	VLSI circuit testing, current signature, passive defects, active defects, VLSI, integrated circuit testing, CMOS integrated circuits, I/sub DDQ/ testing
25	Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
25	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
25	Hans A. R. Manhaeve, Stefaan Kerckenaere	An On-Chip Detection Circuit for the Verification of IC Supply Connections.	DFT	2001	DBLP DOI BibTeX RDF	IC connections, connection verification, supply current measurements, on-chip monitor, reliability, DFT, CMOS, Scan, Boundary Scan, IP core, Current monitor
25	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
25	Claude Thibeault	Detection and location of faults and defects using digital signal processing.	VTS	1995	DBLP DOI BibTeX RDF	sampled current, sampled voltage, quiescent current, parasitic resistive contacts, DSP technique, fault diagnosis, logic testing, integrated circuit testing, fault detection, diagnosis, signal processing, digital signal processing, fault location, fault location, defects, digital integrated circuits, test method
25	Seong-Kweon Kim, Shigehito Saigusa, Suguru Kameda, Hiroyuki Nakase, Kazuo Tsubouchi	New current attenuator circuit in the current mode FFT LSI for OFDM.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
24	Wei Wang, Yu Hu 0001, Yinhe Han 0001, Xiaowei Li 0001, You-Sheng Zhang	Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	don’t care bits, minimum leakage vector, leakage power, leakage current
24	Michael D. Powell, T. N. Vijaykumar	Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise.	ISLPED	2003	DBLP DOI BibTeX RDF	a priori current ramping, pipeline muffling, leakage, decoupling capacitors, inductive noise
24	Rajeev R. Rao, Ashish Srivastava, David T. Blaauw, Dennis Sylvester	Statistical estimation of leakage current considering inter- and intra-die process variation.	ISLPED	2003	DBLP DOI BibTeX RDF	variability, Monte Carlo, leakage current
24	Montree Kumngern, Fabian Khateb, Tomasz Kulej, Martin Kyselak, Somkiat Lerkvaranyu, Boonying Knobnob	Current-Mode Shadow Filter with Single-Input Multiple-Output Using Current-Controlled Current Conveyors with Controlled Current Gain.	Sensors	2024	DBLP DOI BibTeX RDF
24	Mahdi Jalili-Kharaajoo	Design of a Speed Drive Based on Fuzzy Logic for a Dual Three-Phase Induction Motor.	Rough Sets and Current Trends in Computing	2004	DBLP DOI BibTeX RDF
24	Zbigniew Suraj, Piotr Grochowalski	The Rough Set Database System: An Overview.	Rough Sets and Current Trends in Computing	2004	DBLP DOI BibTeX RDF	data mining, neural networks, machine learning, pattern recognition, rough sets, evolutionary computing, knowledge discovery, database systems, fuzzy systems
24	Witold R. Rudnicki, Henryk Jan Komorowski	Feature Synthesis and Extraction for the Construction of Generalized Properties of Amino Acids.	Rough Sets and Current Trends in Computing	2004	DBLP DOI BibTeX RDF
24	Arkadiusz Wojna	Constraint Based Incremental Learning of Classification Rules.	Rough Sets and Current Trends in Computing	2000	DBLP DOI BibTeX RDF	machine learning, rough sets, incremental learning, decision algorithms
24	Wojciech Ziarko	Rough Sets: Trends, Challenges, and Prospects.	Rough Sets and Current Trends in Computing	2000	DBLP DOI BibTeX RDF
24	Tom R. Burns, Anna Gomolinska	Modelling Social Game Systems by Rule Complexes.	Rough Sets and Current Trends in Computing	1998	DBLP DOI BibTeX RDF
24	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
24	Mohammad M. Ahmadi, Reza Lotfi	A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiers.	ISLPED	2003	DBLP DOI BibTeX RDF	current summation, floating current source, input stage, rail-to-rail, transconductance, operational transconductance amplifier
24	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I2L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
24	Walter W. Weber, Adit D. Singh	An experimental evaluation of the differential BICS for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	differential BICS, CMOS test chips, inter-layer shorts, intra-layer shorts, fault diagnosis, integrated circuit testing, fault coverage, CMOS integrated circuits, opens, built-in current sensor, IC testing, I/sub DDQ/ testing, electric current measurement, electric sensing devices
23	P. V. Ratna Kumar, Kaushik Bhattacharyya, Tamal Das, Pradip Mandal	Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination.	ISLPED	2009	DBLP DOI BibTeX RDF	shoot-through current, switched capacitor converter, time interleaving
23	Vikas Kaushal, Quentin Diduck, Martin Margala	Study of leakage current mechanisms in ballistic deflection transistors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation
23	Taufik, Makbul Anwari	Modeling and Simulation of Current Ripple in DC Link Connecting Two PWM Inverters Using Matlab/Simulink.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	DC bus Current Ripple, PWM Inverter
23	Tsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen	A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost.	ASP-DAC	2007	DBLP DOI BibTeX RDF	MLV controller, probability-based algorithm, leakage current reduction, minimum leakage vector
23	Zhiyuan Cai, Shaohua Ma, Yangyang Ge, Erzhi Wang	Time Series Prediction of Short Circuit Current for Synchronous Control of Synthetic Test Based on Delay Coordinate Embedding.	ICIC (3)	2007	DBLP DOI BibTeX RDF	short circuit current, synthetic test, time series prediction, synchronous control
23	Stephen C. Terry, Mohammad M. Mojarradi, Benjamin J. Blalock, Jesse A. Richmond	Adaptive gate biasing: a new solution for body-driven current mirrors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	SOI analog, body driving, current mirrors, ultra-low-voltage analog circuit design
23	Sudhakar Bobba, Ibrahim N. Hajj	Maximum Current Estimation in Programmable Logic Arrays.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	maximum current, PLA
23	Claude Thibeault	Increasing Current Testing Resolution.	DFT	1998	DBLP DOI BibTeX RDF	current signatures, test, Integrated circuits, Iddq testing
23	José Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor	Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	mixed current/voltage testing, design for testability, mixed-signal testing, cross-correlation
23	Udo Mahlstedt, Jürgen Alt, Matthias Heinitz	CURRENT: a test generation system for IDDQ testing.	VTS	1995	DBLP DOI BibTeX RDF	CURRENT test system, test generation system, scan-based circuits, library-based fault modeling strategy, intra-gate shorts, inter-gate shorts, gate-drain shorts, deterministic test generator, test set compaction technique, fault diagnosis, logic testing, integrated circuit testing, automatic testing, fault simulator, fault coverage, fault location, CMOS logic circuits, bridging faults, boundary scan testing, I/sub DDQ/ testing, test application time reduction, stuck-on faults, leakage faults
23	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
23	Hector Ouilhet	Google Sky Map: using your phone as an interface.	Mobile HCI	2010	DBLP DOI BibTeX RDF
23	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
23	Violet Ka I Pun, Volker Stolz	Enforced Dependencies for Active Objects.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Roberto Casadei, Ferruccio Damiani, Gianluca Torta, Mirko Viroli	Actor-Based Designs for Distributed Self-organisation Programming.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Chinmayi Prabhu Baramashetru, Silvia Lizeth Tapia Tarifa, Olaf Owe	Integrating Data Privacy Compliance in Active Object Languages.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Eduard Kamburjan, Michael Lienhardt	Type-Based Verification of Delegated Control in Hybrid Systems.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Guido Salvaneschi, Pascal Weisenburger	Bridging Between Active Objects: Multitier Programming for Distributed, Concurrent Systems.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Nobuko Yoshida	Programming Language Implementations with Multiparty Session Types.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Jonas Spenger, Paris Carbone, Philipp Haller	A Survey of Actor-Like Programming Models for Serverless Computing.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Reiner Hähnle, Eduard Kamburjan, Marco Scaletta	Context-Aware Trace Contracts.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Elias Castegren, Tobias Wrigstad	Encore: Coda.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Martin Andrieux, Ludovic Henrio, Gabriel Radanne	Active Objects Based on Algebraic Effects.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Paul Kobialka, Rudolf Schlatte, Gunnar Rye Bergersen, Einar Broch Johnsen, Silvia Lizeth Tapia Tarifa	Simulating User Journeys with Active Objects.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Lorenzo Bacchiani, Mario Bravetti, Saverio Giallorenzo, Jacopo Mauro, Gianluigi Zavattaro	Integrated Timed Architectural Modeling/Execution Language.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	Ramtin Khosravi, Ehsan Khamespanah, Fatemeh Ghassemi, Marjan Sirjani	Actors Upgraded for Variability, Adaptability, and Determinism.	Active Object Languages: Current Research Trends	2024	DBLP DOI BibTeX RDF
23	John I. Tait, Barou Diallo	Future Patent Search.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Stephen Tomlinson, Bruce Hedin	Measuring Effectiveness in the TREC Legal Track.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Hidetsugu Nanba, Hideaki Kamaya, Toshiyuki Takezawa, Manabu Okumura, Akihiro Shinmori, Hidekazu Tanigawa	Automatic Translation of Scholarly Terms into Patent Terms.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Cornelis H. A. Koster, Jean G. Beney, Suzan Verberne, Merijn Vogel	Phrase-Based Document Categorization.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Steffen Koch 0001, Harald Bosch	From Static Textual Display of Patents to Graphical Interactions.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Hany Azzam, Iraklis A. Klampanos, Thomas Roelleke	Large-Scale Logical Retrieval: Technology for Semantic Modelling of Patent Search.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Richard Bache	Measuring and Improving Access to the Corpus.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Veronika Stefanov, John I. Tait	An Introduction to Contemporary Search Technology.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Florina Piroi, Veronika Zenz	Evaluating Information Retrieval in the Intellectual Property Domain: The Clef-Ip Campaign.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Ted Briscoe, Karl Harrison, Andrew Naish, Andy Parker, Marek Rei, Advaith Siddharthan, David Sinclair, Mark Slater, Rebecca Watson	Intelligent Information Access from Scientific Papers.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Christopher G. Harris 0001, Robert Arens, Padmini Srinivasan	Using Classification Code Hierarchies for Patent Prior Art Searches.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Hamish Cunningham, Valentin Tablan, Ian Roberts, Mark A. Greenwood, Niraj Aswani	Information Extraction and Semantic Annotation for Multi-Paradigm Information Management.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Ben Carterette, Ellen M. Voorhees	Overview of Information Retrieval Evaluation.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Andreas Pesenhofer, Helmut Berger, Michael Dittenbach	Offering New Insights by Harmonizing Patents, Taxonomies and Linked Data.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Mihai Lupu, Jimmy X. Huang, Jianhan Zhu	Evaluation of Chemical Information Retrieval Tools.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Karim Benzineb, Jacques Guyot	Automated Patent Classification.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Peter Parapatics, Michael Dittenbach	Patent Claim Decomposition for Improved Information Extraction.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Anthony J. Trippe, Ian Ruthven	Evaluating Real Patent Retrieval Effectiveness.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF
23	Doreen Alberts, Cynthia Barcelon Yang, Denise Fobare-DePonio, Ken Koubek, Suzanne Robins, Matthew Rodgers, Edlyn Simmons, Dominic DeMarco	Introduction to Patent Searching.	Current Challenges in Patent Information Retrieval	2011	DBLP DOI BibTeX RDF